222 lines
8.9 KiB
C
222 lines
8.9 KiB
C
/* spi.c
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Copyright 2021 Carl John Kugler III
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Licensed under the Apache License, Version 2.0 (the License); you may not use
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this file except in compliance with the License. You may obtain a copy of the
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License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software distributed
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under the License is distributed on an AS IS BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, either express or implied. See the License for the
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specific language governing permissions and limitations under the License.
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*/
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#include <stdbool.h>
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//
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#include "pico/stdlib.h"
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#include "pico/mutex.h"
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#include "pico/sem.h"
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//
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#include "my_debug.h"
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//
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#include "spi.h"
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static bool irqChannel1 = false;
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static bool irqShared = true;
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void spi_irq_handler(spi_t *pSPI) {
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if (irqChannel1) {
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if (dma_hw->ints1 & 1u << pSPI->rx_dma) { // Ours?
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dma_hw->ints1 = 1u << pSPI->rx_dma; // clear it
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myASSERT(!dma_channel_is_busy(pSPI->rx_dma));
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sem_release(&pSPI->sem);
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}
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} else {
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if (dma_hw->ints0 & 1u << pSPI->rx_dma) { // Ours?
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dma_hw->ints0 = 1u << pSPI->rx_dma; // clear it
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myASSERT(!dma_channel_is_busy(pSPI->rx_dma));
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sem_release(&pSPI->sem);
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}
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}
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}
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void set_spi_dma_irq_channel(bool useChannel1, bool shared) {
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irqChannel1 = useChannel1;
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irqShared = shared;
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}
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// SPI Transfer: Read & Write (simultaneously) on SPI bus
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// If the data that will be received is not important, pass NULL as rx.
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// If the data that will be transmitted is not important,
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// pass NULL as tx and then the SPI_FILL_CHAR is sent out as each data
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// element.
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bool spi_transfer(spi_t *pSPI, const uint8_t *tx, uint8_t *rx, size_t length) {
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// myASSERT(512 == length || 1 == length);
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myASSERT(tx || rx);
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// myASSERT(!(tx && rx));
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// tx write increment is already false
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if (tx) {
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channel_config_set_read_increment(&pSPI->tx_dma_cfg, true);
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} else {
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static const uint8_t dummy = SPI_FILL_CHAR;
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tx = &dummy;
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channel_config_set_read_increment(&pSPI->tx_dma_cfg, false);
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}
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// rx read increment is already false
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if (rx) {
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channel_config_set_write_increment(&pSPI->rx_dma_cfg, true);
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} else {
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static uint8_t dummy = 0xA5;
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rx = &dummy;
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channel_config_set_write_increment(&pSPI->rx_dma_cfg, false);
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}
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// Clear the interrupt request.
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dma_hw->ints0 = 1u << pSPI->rx_dma;
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dma_channel_configure(pSPI->tx_dma, &pSPI->tx_dma_cfg,
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&spi_get_hw(pSPI->hw_inst)->dr, // write address
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tx, // read address
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length, // element count (each element is of
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// size transfer_data_size)
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false); // start
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dma_channel_configure(pSPI->rx_dma, &pSPI->rx_dma_cfg,
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rx, // write address
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&spi_get_hw(pSPI->hw_inst)->dr, // read address
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length, // element count (each element is of
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// size transfer_data_size)
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false); // start
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// start them exactly simultaneously to avoid races (in extreme cases
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// the FIFO could overflow)
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dma_start_channel_mask((1u << pSPI->tx_dma) | (1u << pSPI->rx_dma));
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/* Timeout 1 sec */
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uint32_t timeOut = 1000;
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/* Wait until master completes transfer or time out has occured. */
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bool rc = sem_acquire_timeout_ms(
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&pSPI->sem, timeOut); // Wait for notification from ISR
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if (!rc) {
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// If the timeout is reached the function will return false
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DBG_PRINTF("Notification wait timed out in %s\n", __FUNCTION__);
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return false;
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}
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// Shouldn't be necessary:
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dma_channel_wait_for_finish_blocking(pSPI->tx_dma);
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dma_channel_wait_for_finish_blocking(pSPI->rx_dma);
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myASSERT(!dma_channel_is_busy(pSPI->tx_dma));
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myASSERT(!dma_channel_is_busy(pSPI->rx_dma));
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return true;
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}
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void spi_lock(spi_t *pSPI) {
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myASSERT(mutex_is_initialized(&pSPI->mutex));
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mutex_enter_blocking(&pSPI->mutex);
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}
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void spi_unlock(spi_t *pSPI) {
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myASSERT(mutex_is_initialized(&pSPI->mutex));
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mutex_exit(&pSPI->mutex);
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}
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bool my_spi_init(spi_t *pSPI) {
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auto_init_mutex(my_spi_init_mutex);
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mutex_enter_blocking(&my_spi_init_mutex);
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if (!pSPI->initialized) {
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//// The SPI may be shared (using multiple SSs); protect it
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//pSPI->mutex = xSemaphoreCreateRecursiveMutex();
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//xSemaphoreTakeRecursive(pSPI->mutex, portMAX_DELAY);
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if (!mutex_is_initialized(&pSPI->mutex)) mutex_init(&pSPI->mutex);
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spi_lock(pSPI);
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// For the IRQ notification:
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sem_init(&pSPI->sem, 0, 1);
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/* Configure component */
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// Enable SPI at 100 kHz and connect to GPIOs
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spi_init(pSPI->hw_inst, 100 * 1000);
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spi_set_format(pSPI->hw_inst, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
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gpio_set_function(pSPI->miso_gpio, GPIO_FUNC_SPI);
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gpio_set_function(pSPI->mosi_gpio, GPIO_FUNC_SPI);
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gpio_set_function(pSPI->sck_gpio, GPIO_FUNC_SPI);
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// ss_gpio is initialized in sd_init_driver()
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// Slew rate limiting levels for GPIO outputs.
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// enum gpio_slew_rate { GPIO_SLEW_RATE_SLOW = 0, GPIO_SLEW_RATE_FAST = 1 }
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// void gpio_set_slew_rate (uint gpio,enum gpio_slew_rate slew)
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// Default appears to be GPIO_SLEW_RATE_SLOW.
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// Drive strength levels for GPIO outputs.
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// enum gpio_drive_strength { GPIO_DRIVE_STRENGTH_2MA = 0, GPIO_DRIVE_STRENGTH_4MA = 1, GPIO_DRIVE_STRENGTH_8MA = 2,
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// GPIO_DRIVE_STRENGTH_12MA = 3 }
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// enum gpio_drive_strength gpio_get_drive_strength (uint gpio)
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if (pSPI->set_drive_strength) {
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gpio_set_drive_strength(pSPI->mosi_gpio, pSPI->mosi_gpio_drive_strength);
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gpio_set_drive_strength(pSPI->sck_gpio, pSPI->sck_gpio_drive_strength);
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}
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// SD cards' DO MUST be pulled up.
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gpio_pull_up(pSPI->miso_gpio);
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// Grab some unused dma channels
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pSPI->tx_dma = dma_claim_unused_channel(true);
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pSPI->rx_dma = dma_claim_unused_channel(true);
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pSPI->tx_dma_cfg = dma_channel_get_default_config(pSPI->tx_dma);
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pSPI->rx_dma_cfg = dma_channel_get_default_config(pSPI->rx_dma);
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channel_config_set_transfer_data_size(&pSPI->tx_dma_cfg, DMA_SIZE_8);
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channel_config_set_transfer_data_size(&pSPI->rx_dma_cfg, DMA_SIZE_8);
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// We set the outbound DMA to transfer from a memory buffer to the SPI
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// transmit FIFO paced by the SPI TX FIFO DREQ The default is for the
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// read address to increment every element (in this case 1 byte -
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// DMA_SIZE_8) and for the write address to remain unchanged.
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channel_config_set_dreq(&pSPI->tx_dma_cfg, spi_get_index(pSPI->hw_inst)
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? DREQ_SPI1_TX
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: DREQ_SPI0_TX);
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channel_config_set_write_increment(&pSPI->tx_dma_cfg, false);
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// We set the inbound DMA to transfer from the SPI receive FIFO to a
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// memory buffer paced by the SPI RX FIFO DREQ We coinfigure the read
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// address to remain unchanged for each element, but the write address
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// to increment (so data is written throughout the buffer)
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channel_config_set_dreq(&pSPI->rx_dma_cfg, spi_get_index(pSPI->hw_inst)
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? DREQ_SPI1_RX
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: DREQ_SPI0_RX);
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channel_config_set_read_increment(&pSPI->rx_dma_cfg, false);
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/* Theory: we only need an interrupt on rx complete,
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since if rx is complete, tx must also be complete. */
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// Configure the processor to run dma_handler() when DMA IRQ 0/1 is
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// asserted:
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int irq = irqChannel1 ? DMA_IRQ_1 : DMA_IRQ_0;
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if (irqShared) {
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irq_add_shared_handler(
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irq, pSPI->dma_isr,
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PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY);
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} else {
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irq_set_exclusive_handler(irq, pSPI->dma_isr);
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}
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// Tell the DMA to raise IRQ line 0/1 when the channel finishes a block
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if (irqChannel1) {
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dma_channel_set_irq1_enabled(pSPI->rx_dma, true);
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} else {
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dma_channel_set_irq0_enabled(pSPI->rx_dma, true);
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}
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irq_set_enabled(irq, true);
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LED_INIT();
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pSPI->initialized = true;
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spi_unlock(pSPI);
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}
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mutex_exit(&my_spi_init_mutex);
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return true;
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}
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/* [] END OF FILE */
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