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added bulk caps

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willem
2021-04-07 17:16:17 +02:00
parent 504d6337e9
commit 7417011aba
8 changed files with 4073 additions and 89868 deletions
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4
CAD/PCB/clockclock.sch-bak
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@@ -646,7 +646,7 @@ Wire Wire Line
6250 3200 6150 3200
Wire Wire Line
6250 3100 6150 3100
Text GLabel 4950 3800 0 50 Input ~ 0
Text GLabel 4950 3900 0 50 Input ~ 0
MOT_EN1
Text GLabel 6250 3800 2 50 Input ~ 0
MOT_DIR1
@@ -1590,7 +1590,7 @@ NoConn ~ 5050 4400
NoConn ~ 5050 4500
NoConn ~ 5050 4600
NoConn ~ 6150 4600
Text GLabel 4950 3900 0 50 Input ~ 0
Text GLabel 4950 3800 0 50 Input ~ 0
MOT_RST1
Wire Wire Line
5050 3900 4950 3900