added bulk caps

CAD/PCB/clockclock.pro

@@ -1,4 +1,4 @@
-update=2021 April 06, Tuesday 21:13:59
+update=2021 April 07, Wednesday 15:13:24
 version=1
 last_client=kicad
 [general]
@@ -244,7 +244,7 @@ dPairViaGap=0.25
 [pcbnew/Netclasses/1]
 Name=5v
 Clearance=0.2032
-TrackWidth=0.8128
+TrackWidth=0.4572
 ViaDiameter=1.016
 ViaDrill=0.6096
 uViaDiameter=0.3048

CAD/PCB/clockclock.sch

@@ -1442,8 +1442,12 @@ U 1 1 60EA9977
 P 8650 5500
 F 0 "C12" H 8768 5546 50  0000 L CNN
 F 1 "10uF" H 8768 5455 50  0000 L CNN
-F 2 "" H 8688 5350 50  0001 C CNN
+F 2 "Capacitor_SMD:C_Elec_4x5.4" H 8688 5350 50  0001 C CNN
 F 3 "~" H 8650 5500 50  0001 C CNN
+F 4 "Panasonic" H 8650 5500 50  0001 C CNN "mfr"
+F 5 "MCVVT016M100CA1L" H 8650 5500 50  0001 C CNN "partnr"
+F 6 "farnell" H 8650 5500 50  0001 C CNN "supplier"
+F 7 "2611355" H 8650 5500 50  0001 C CNN "ordercode"
 	1    8650 5500
 	1    0    0    -1  
 $EndComp
@@ -1496,7 +1500,7 @@ U 1 1 60EF845D
 P 7500 1050
 F 0 "C10" H 7618 1096 50  0000 L CNN
 F 1 "10uF" H 7618 1005 50  0000 L CNN
-F 2 "" H 7538 900 50  0001 C CNN
+F 2 "Capacitor_SMD:C_Elec_4x5.4" H 7538 900 50  0001 C CNN
 F 3 "~" H 7500 1050 50  0001 C CNN
 	1    7500 1050
 	1    0    0    -1  

CAD/PCB/clockclock.sch-bak

@@ -646,7 +646,7 @@ Wire Wire Line
 	6250 3200 6150 3200
 Wire Wire Line
 	6250 3100 6150 3100
-Text GLabel 4950 3800 0    50   Input ~ 0
+Text GLabel 4950 3900 0    50   Input ~ 0
 MOT_EN1
 Text GLabel 6250 3800 2    50   Input ~ 0
 MOT_DIR1
@@ -1590,7 +1590,7 @@ NoConn ~ 5050 4400
 NoConn ~ 5050 4500
 NoConn ~ 5050 4600
 NoConn ~ 6150 4600
-Text GLabel 4950 3900 0    50   Input ~ 0
+Text GLabel 4950 3800 0    50   Input ~ 0
 MOT_RST1
 Wire Wire Line
 	5050 3900 4950 3900