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added bulk caps

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willem
2021-04-07 17:16:17 +02:00
parent 504d6337e9
commit 7417011aba
8 changed files with 4073 additions and 89868 deletions
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4
CAD/PCB/clockclock.pro
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@@ -1,4 +1,4 @@
update=2021 April 06, Tuesday 21:13:59
update=2021 April 07, Wednesday 15:13:24
version=1
last_client=kicad
[general]
@@ -244,7 +244,7 @@ dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=5v
Clearance=0.2032
TrackWidth=0.8128
TrackWidth=0.4572
ViaDiameter=1.016
ViaDrill=0.6096
uViaDiameter=0.3048