release V1.0
This commit is contained in:
@@ -1,4 +1,4 @@
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update=2021 February 26, Friday 22:11:16
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update=2021 March 01, Monday 21:41:52
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version=1
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last_client=kicad
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[general]
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@@ -22,7 +22,7 @@ AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.2
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MinTrackWidth=0.2032
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MinViaDiameter=0.4
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MinViaDrill=0.3
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MinMicroViaDiameter=0.2
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@@ -31,8 +31,8 @@ MinHoleToHole=0.25
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TrackWidth1=0.254
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ViaDiameter1=0.8128
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ViaDrill1=0.4064
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairWidth1=0.2032
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dPairGap1=0.2032
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dPairViaGap1=0.25
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SilkLineWidth=0.12
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SilkTextSizeV=1
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@@ -231,10 +231,10 @@ Clearance=0.2032
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TrackWidth=0.254
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ViaDiameter=0.8128
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ViaDrill=0.4064
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.2
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dPairGap=0.25
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uViaDiameter=0.3048
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uViaDrill=0.1016
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dPairWidth=0.2032
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dPairGap=0.2032
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dPairViaGap=0.25
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[pcbnew/Netclasses/1]
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Name=POWER
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@@ -242,8 +242,18 @@ Clearance=0.2032
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TrackWidth=0.4064
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ViaDiameter=0.8128
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ViaDrill=0.4064
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uViaDiameter=0.3
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uViaDrill=0.1
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dPairWidth=0.2
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dPairGap=0.25
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uViaDiameter=0.3048
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uViaDrill=0.1016
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dPairWidth=0.2032
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dPairGap=0.2032
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dPairViaGap=0.25
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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