release V1.0

This commit is contained in:
2021-03-01 21:55:41 +01:00
parent a980dceeae
commit 17a1bb1ffc
22 changed files with 5179 additions and 544 deletions

View File

@@ -1,4 +1,4 @@
update=2021 February 26, Friday 22:11:16
update=2021 March 01, Monday 21:41:52
version=1
last_client=kicad
[general]
@@ -22,7 +22,7 @@ AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinTrackWidth=0.2032
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
@@ -31,8 +31,8 @@ MinHoleToHole=0.25
TrackWidth1=0.254
ViaDiameter1=0.8128
ViaDrill1=0.4064
dPairWidth1=0.2
dPairGap1=0.25
dPairWidth1=0.2032
dPairGap1=0.2032
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
@@ -231,10 +231,10 @@ Clearance=0.2032
TrackWidth=0.254
ViaDiameter=0.8128
ViaDrill=0.4064
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
uViaDiameter=0.3048
uViaDrill=0.1016
dPairWidth=0.2032
dPairGap=0.2032
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=POWER
@@ -242,8 +242,18 @@ Clearance=0.2032
TrackWidth=0.4064
ViaDiameter=0.8128
ViaDrill=0.4064
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
uViaDiameter=0.3048
uViaDrill=0.1016
dPairWidth=0.2032
dPairGap=0.2032
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1