69 lines
2.0 KiB
C
69 lines
2.0 KiB
C
/* util.h
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Copyright 2021 Carl John Kugler III
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Licensed under the Apache License, Version 2.0 (the License); you may not use
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this file except in compliance with the License. You may obtain a copy of the
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License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software distributed
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under the License is distributed on an AS IS BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, either express or implied. See the License for the
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specific language governing permissions and limitations under the License.
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*/
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#ifndef _UTIL_H_
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#define _UTIL_H_
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#include <stddef.h>
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#include <stdint.h>
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#include "hardware/structs/scb.h"
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// works with negative index
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static inline int wrap_ix(int index, int n)
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{
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return ((index % n) + n) % n;
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}
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__attribute__((always_inline)) static inline uint32_t calculate_checksum(uint32_t const *p, size_t const size){
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uint32_t checksum = 0;
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for (uint32_t i = 0; i < (size/sizeof(uint32_t))-1; i++){
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checksum ^= *p;
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p++;
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}
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return checksum;
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}
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// from Google Chromium's codebase:
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#ifndef COUNT_OF
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#define COUNT_OF(x) ((sizeof(x)/sizeof(0[x])) / ((size_t)(!(sizeof(x) % sizeof(0[x])))))
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#endif
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__attribute__((always_inline)) static inline void __DSB(void) {
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__asm volatile("dsb 0xF" ::: "memory");
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}
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// Patterned after CMSIS NVIC_SystemReset
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__attribute__((__noreturn__)) static inline void system_reset() {
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__DSB(); /* Ensure all outstanding memory accesses included
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buffered write are completed before reset */
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scb_hw->aircr = ((0x5FAUL << 16U) | (1UL << 2U));
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__DSB(); /* Ensure completion of memory access */
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for (;;) {
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__asm volatile("nop");
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}
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}
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/**
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\brief Disable IRQ Interrupts
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\details Disables IRQ interrupts by setting the I-bit in the CPSR.
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Can only be executed in Privileged modes.
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*/
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__attribute__((always_inline)) static inline void __disable_irq(void) {
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__asm volatile("cpsid i" : : : "memory");
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}
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#endif
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/* [] END OF FILE */
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