555 lines
16 KiB
C
555 lines
16 KiB
C
/**
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* Copyright (C) 2019-2022 by Mahyar Koshkouei <mk@deltabeard.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
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* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
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* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
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* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
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* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <assert.h>
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#include "mk_ili9225.h"
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/* Register Descriptions. */
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/**
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* The index register (IR) stored the register address.
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* The register selection signal (RS) selects register access.
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* The read/write signals (nRD/nWR) select read or write command, respectively.
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* The data bus D0-D17 are used to read or write data. Register access is
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* 16-bit, so 18-bit bus is reduced to 16-bit only (see page 45).
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* On writing data GRAM, the internal address is automatically incremented.
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*/
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/* ILI9225 Registers. */
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/**
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* [Register Name] ([RO,WO, or WR])
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* R ([Read mask]): [Description of what can be read at mask]
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* W ([Write mask]): [Description of what can be written at mask]
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*/
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/**
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* Driver Code Read (RW)
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* R (0xFFFF): Reads the device code integer 0x9225.
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* W: (0xXXX1): Starts (0x1) or stops (0x0) internal oscillator.
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* At least 10ms must pass after starting the internal oscillator to allow it
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* to stabilise.
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*/
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#define MK_ILI9225_REG_DRIVER_CODE_READ 0x00
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#define MK_ILI9225_REG_START_OSCILLATION 0x00
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/**
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* Driver Output Control (WO)
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* W (0x8XXX): VSPL: Inverts the polarity of VSYNC pin. "1" is high active.
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* W (0x4XXX): HSPL: Inverts the polarity of HSYNC pin. "1" is high active.
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* W (0x2XXX): DPL: Same as above for DOTCLK.
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* W (0x1XXX): EPL: Same as above for ENABLE.
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* W (0xX4XX): SM: Scan order by gate driver.
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* W (0xX2XX): GS: Shift direction of gate driver.
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* W (0xX1XX): SS: Shift direction from source driver.
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* W (0xXX1F): NL: Set active gate driver line. Default: 0b11011.
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*/
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#define MK_ILI9225_REG_DRIVER_OUTPUT_CTRL 0x01
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/**
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* LCD Driving Waveform Control (WO)
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* Set LCD inversion method.
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* W (0xX3XX): INV: Sets inversion method.
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* W (0xXXX1): FLD: 3-field interlaced scanning function.
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*/
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#define MK_ILI9225_REG_LCD_AC_DRIVING_CTRL 0x02
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/**
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* Entry Mode (WO)
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* W (0x1XXX): BGR: Swap Red with Blue.
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* W (0xX3XX): MDT: Data transmission format for 80-mode.
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* W (0xXX2X): ID1: Control horizontal address counter increment (1) or
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* decrement (0).
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* W (0xXX1X): ID0: Control vertical address counter increment (1) or
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* decrement (0).
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* W (0xXXX8): AM: GRAM update direction. "1" is horizontal.
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*/
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#define MK_ILI9225_REG_ENTRY_MODE 0x03
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/**
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* Display Control 1 (WO)
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* W (0x1XXX): TEMON: Sets the frame flag output signal FLM.
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* W (0xXX1X): GON: Set output level of gate driver. VGL = 0, Normal = 1.
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* W (0xXXX8): CL: Selects 8-colour display mode when 1. Else 2^18 colours.
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* W (0xXXX4): REV: Reverses greyscale levels if set.
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* W (0xXXX3): D: Control display output. 0b11 to turn on display, else display
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* is off.
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*/
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#define MK_ILI9225_REG_DISPLAY_CTRL 0x07
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/**
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* Display Control 2 (WO)
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* Used for I80, M68, and RGB modes only.
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* W (0xXFXX): FP: Specify number of front porch lines.
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* W (0xXXXF): BP: Specify number of back porch lines.
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*/
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#define MK_ILI9225_REG_BLANK_PERIOD_CTRL 0x08
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/**
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* Frame Cycle Control (WO)
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* Used for RGB mode only.
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* W (0xFXXX): NO: Set amount of non-overlay for gate output.
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* W (0xXFXX): SDT: Set delay from gate edge to source output.
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* W (0xXXXF): RTN: Set number of clock cycles for one display line.
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*/
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#define MK_ILI9225_REG_FRAME_CYCLE_CTRL 0x0B
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/**
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* RGB Input Interface Control (W)
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* Used for RGB mode only.
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*/
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#define MK_ILI9225_REG_INTERFACE_CTRL 0x0C
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/**
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* Oscillator Control (W)
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* W (0xXFXX): FOSC: Oscillation frequency.
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* W (0xXXX1): OSC_EN: Starts oscillation from halt state. 10ms wait required.
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*/
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#define MK_ILI9225_REG_OSC_CTRL 0x0F
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/**
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* Power Control 1 (W)
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* W (0xXFXX): SAP: Set current level of driver.
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* W (0xXXX2): DSTB: Enable deep standby mode. Writing to GRAM is prohibited.
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* W (0xXXX1): STB: Enable sleep mode. Stops display and internal oscillator.
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*/
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#define MK_ILI9225_REG_PWR_CTRL1 0x10
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/**
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* Power Control 2 (W)
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* W (0x1XXX): APON: Use automatic boosting operation.
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* W (0xXFXX): PON: Set boosting operation for specific circuits.
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* W (0xXX2X): AON: Set operation of amplifier.
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* W (0xXX1X): VCL1EN: Set operation of generation amplifier.
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* W (0xXXXF): VC: Set VCl1 voltage output.
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*/
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#define MK_ILI9225_REG_PWR_CTRL2 0x11
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/**
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* Power Control 3 (W)
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* W (0x7XXX): BT: Set output factor of boost converter.
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* W (0xX7XX): DC1: Operation frequency of circuit 1 boost converter.
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* W (0xXX7X): DC2: Operation frequency of circuit 2 boost converter.
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* W (0XXXX7): DC3: Operation frequency of circuit 3 boost converter.
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*/
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#define MK_ILI9225_REG_PWR_CTRL3 0x12
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/**
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* Power Control 4 (W)
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* W (0xXX7F): GVD: Set gamma voltage (GVDD) from 2.66V to 5.5V.
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*/
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#define MK_ILI9225_REG_PWR_CTRL4 0x13
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/**
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* Power Control 5 (W)
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* W (0x8XXX): VCOMG: Sets amplitude of VCOM signal.
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* W (0x7FXX): VCM: Sets VCOMH voltage, from 0.4015 to 1.1000 * GVDD.
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* W (0xXX7F): VML: Sets alternate amplitudes of VCOM from 0.534 to 1.200*GVDD.
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*/
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#define MK_ILI9225_REG_PWR_CTRL5 0x14
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/**
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* VCI Recycling (W)
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* W (0xXX7X): VCIR: Number of clock cycles in VCI recycling period.
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*/
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#define MK_ILI9225_REG_VCI_RECYCLING 0x15
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/**
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* RAM Address Set 1 (W)
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* W (0xXXFF): AD[7:0]: Set the initial value of the address counter.
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*/
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#define MK_ILI9225_REG_RAM_ADDR_SET1 0x20
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/**
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* RAM Address Set 2 (W)
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* W (0xXXFF): AD[15:8]: Set the initial value of the address counter.
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*/
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#define MK_ILI9225_REG_RAM_ADDR_SET2 0x21
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/**
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* Read/Write GRAM Data (RW)
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* W (0x3FFFF): Write data to GRAM.
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* R (0x3FFFF): Read data from GRAM.
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*/
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#define MK_ILI9225_REG_GRAM_RW 0x22
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/**
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* Software Reset (W)
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* W (0xFFFF): Perform software reset when 0x00CE is written.
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*/
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#define MK_ILI9225_REG_SOFT_RESET 0x28
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/**
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* Gate Scan Control (W)
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* W (0xXX1F): SCN: Line to start gate scan from.
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*/
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#define MK_ILI9225_REG_GATE_SCAN_CTRL 0x30
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/**
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* Vertical Scroll Control 1 (W)
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* W (0xXXFF): SEA: Scroll end address.
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*/
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#define MK_ILI9225_REG_VERT_SCROLL_CTRL1 0x31
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/**
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* Vertical Scroll Control 2 (W)
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* W (0xXXFF): SSA: Scroll start address.
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*/
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#define MK_ILI9225_REG_VERT_SCROLL_CTRL2 0x32
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/**
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* Vertical Scroll Control 3 (W)
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* W (0xXXFF): SST: Scroll step.
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*/
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#define MK_ILI9225_REG_VERT_SCROLL_CTRL3 0x33
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/**
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* Partial Screen Driving Position (W)
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* W (0xXXFF): SE: High byte of screen end position.
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*/
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#define MK_ILI9225_REG_PART_DRIVING_POS1 0x34
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/**
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* Partial Screen Driving Position (W)
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* W (0xXXFF): SS: High byte of screen start position.
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*/
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#define MK_ILI9225_REG_PART_DRIVING_POS2 0x35
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/**
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* Horizontal RAM Address Position (W)
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* W (0xXXFF): HEA: End horizontal position.
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*/
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#define MK_ILI9225_REG_HORI_WIN_ADDR1 0x36
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/**
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* Horizontal RAM Address Position (W)
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* W (0xXXFF): HSA: Start horizontal position.
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*/
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#define MK_ILI9225_REG_HORI_WIN_ADDR2 0x37
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/**
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* Vertical RAM Address Position (W)
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* W (0xXXFF): VEA: End vertical position.
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*/
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#define MK_ILI9225_REG_VERT_WIN_ADDR1 0x38
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/**
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* Vertical RAM Address Position (W)
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* W (0xXXFF): VSA: Start vertical position.
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*/
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#define MK_ILI9225_REG_VERT_WIN_ADDR2 0x39
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/**
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* Gamma Control (W)
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*/
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#define MK_ILI9225_REG_GAMMA_CTRL1 0x50
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#define MK_ILI9225_REG_GAMMA_CTRL2 0x51
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#define MK_ILI9225_REG_GAMMA_CTRL3 0x52
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#define MK_ILI9225_REG_GAMMA_CTRL4 0x53
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#define MK_ILI9225_REG_GAMMA_CTRL5 0x54
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#define MK_ILI9225_REG_GAMMA_CTRL6 0x55
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#define MK_ILI9225_REG_GAMMA_CTRL7 0x56
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#define MK_ILI9225_REG_GAMMA_CTRL8 0x57
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#define MK_ILI9225_REG_GAMMA_CTRL9 0x58
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#define MK_ILI9225_REG_GAMMA_CTRL10 0x59
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#define MK_ILI9225_NV_MEM_DATA_PROG 0x60
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#define MK_ILI9225_NV_MEM_CTRL 0x61
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#define MK_ILI9225_NV_MEM_STAT 0x62
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#define MK_ILI9225_NV_MEM_PROTECTION_KEY 0x63
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#define MK_ILI9225_NV_MEM_ID_CODE 0x65
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#define MK_ILI9225_REG_MTP_TEST_KEY 0x80
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#define MK_ILI9225_REG_MTP_CTRL_REG 0x81
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#define MK_ILI9225_REG_MTP_DATA_READ 0x82
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/* Useful macros. */
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#define ARRAYSIZE(array) (sizeof(array)/sizeof(array[0]))
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/* Structure definitions. */
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struct reg_dat_pair {
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uint16_t reg;
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uint16_t dat;
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};
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/* Local functions. */
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static void write_register(uint16_t cmd);
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static void write_data(uint16_t dat);
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#if MK_ILI9225_READ_AVAILABLE
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static uint16_t read_data(void);
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static uint16_t get_register(uint16_t reg);
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#endif
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static void write_register(uint16_t cmd)
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{
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mk_ili9225_set_rs(0);
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mk_ili9225_set_cs(0);
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mk_ili9225_spi_write16(&cmd, 1);
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mk_ili9225_set_cs(1);
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}
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static void write_data(uint16_t dat)
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{
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mk_ili9225_set_rs(1);
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mk_ili9225_set_cs(0);
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mk_ili9225_spi_write16(&dat, 1);
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mk_ili9225_set_cs(1);
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}
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#if MK_ILI9225_READ_AVAILABLE
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static uint16_t read_data(void)
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{
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uint16_t ret;
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mk_ili9225_set_rs(1);
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mk_ili9225_set_cs(0);
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ret = mk_ili9225_spi_read16();
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mk_ili9225_set_cs(1);
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return ret;
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}
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static uint16_t get_register(uint16_t reg)
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{
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write_register(reg);
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return read_data();
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}
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#endif
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static void set_register(uint16_t reg, uint16_t dat)
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{
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write_register(reg);
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write_data(dat);
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}
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#if MK_ILI9225_READ_AVAILABLE
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unsigned mk_ili9225_read_driving_line(void)
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{
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unsigned line;
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mk_ili9225_set_rs(0);
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mk_ili9225_set_cs(0);
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line = read_data();
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mk_ili9225_set_cs(1);
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return (line >> 8);
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}
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#endif
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/* Public functions. */
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unsigned mk_ili9225_init(void)
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{
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unsigned ret = 0x9225;
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/* Initialise reset pin as not reset. RST must be high before reset. */
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mk_ili9225_set_rst(1);
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/* Initialise other pins too. */
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mk_ili9225_set_cs(1);
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mk_ili9225_set_rs(0);
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/* Make sure pin is initialised by setting small delay. */
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mk_ili9225_delay_ms(1);
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/* Put ILI9225 into reset. */
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mk_ili9225_set_rst(0);
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/* Reset low-level width (Tres) is at least 1ms. */
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mk_ili9225_delay_ms(10);
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/* Bring ILI9225 out of reset. */
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mk_ili9225_set_rst(1);
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mk_ili9225_delay_ms(50);
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/* Initialise power registers. */
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/* FIXME: This may not be required. All are initialised to 0x00,
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* FIXME: but VCOMG is set to 1 on init apparently. */
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{
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const uint8_t regs[] = {
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MK_ILI9225_REG_PWR_CTRL1, MK_ILI9225_REG_PWR_CTRL2,
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MK_ILI9225_REG_PWR_CTRL3, MK_ILI9225_REG_PWR_CTRL4,
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MK_ILI9225_REG_PWR_CTRL5
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};
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for(uint8_t i = 0; i < sizeof(regs); i++)
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set_register(regs[i], 0x0000);
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}
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mk_ili9225_delay_ms(40);
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/* Switch on power control. */
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{
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/* VCI set to 2.58V. */
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/* FIXME: CTRL3 VGH is set to 2.58*6=15.48, but it could be
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* FIXME: lower ( 9 < VGH < 16.5).
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* FIXME: CTRL3 VGL is set to 2.58*-4=-10.32, but it could be
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* FIXME: higher ( -4 < VGL < -16.5).
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* FIXME: BT could be set to 0b000 for VGH=10, VGL=-7.5. */
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/* CTRL4: GVDD is set to 4.68V. */
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/* CTRL5: Set VCM to 0.8030V. Set VML to 1.104V. */
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/* CTRL1: Set driving capability to "Medium Fast 1". */
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const uint8_t regs[] = {
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MK_ILI9225_REG_PWR_CTRL2, MK_ILI9225_REG_PWR_CTRL3,
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MK_ILI9225_REG_PWR_CTRL4, MK_ILI9225_REG_PWR_CTRL5,
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MK_ILI9225_REG_PWR_CTRL1
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};
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const uint16_t dat[] = {
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0x0018, 0x6121, 0x006F, 0x495F, 0x0800
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};
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for(uint8_t i = 0; i < sizeof(regs); i++)
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set_register(regs[i], dat[i]);
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}
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mk_ili9225_delay_ms(10);
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/* Enable automatic booster operation, and amplifiers.
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* Set VCI1 to 2.76V.
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* FIXME: why is VCI1 changed from 2.58 to 2.76V? */
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set_register(MK_ILI9225_REG_PWR_CTRL2, 0x103B);
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mk_ili9225_delay_ms(50);
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{
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const struct reg_dat_pair cmds[] = {
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/* Set shift direction SS from S528 to S1.
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* Set active lines NL to 528 * 220 dots. */
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{ MK_ILI9225_REG_DRIVER_OUTPUT_CTRL, 0x011C },
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/* Set LCD inversion to disabled. */
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{ MK_ILI9225_REG_LCD_AC_DRIVING_CTRL, 0x0100 },
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/* Increment vertical and horizontal address.
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* Use vertical image. */
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{ MK_ILI9225_REG_ENTRY_MODE, 0x0018 },
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/* Turn off all display outputs. */
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{ MK_ILI9225_REG_DISPLAY_CTRL, 0x0000 },
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/* Set porches to 8 lines. */
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{ MK_ILI9225_REG_BLANK_PERIOD_CTRL, 0x0808 },
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/* Use 1-clock delay to gate output and edge. */
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{ MK_ILI9225_REG_FRAME_CYCLE_CTRL, 0x1100 },
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/* Ignore RGB interface settings. */
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{ MK_ILI9225_REG_INTERFACE_CTRL, 0x0000 },
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/* Set oscillation frequency to 266.6 kHz. */
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{ MK_ILI9225_REG_OSC_CTRL, 0x0701 },
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/* Set VCI recycling to 2 clocks. */
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{ MK_ILI9225_REG_VCI_RECYCLING, 0x0020 },
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/* Initialise RAM Address to 0x0 px. */
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{ MK_ILI9225_REG_RAM_ADDR_SET1, 0x0000 },
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{ MK_ILI9225_REG_RAM_ADDR_SET2, 0x0000 },
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/* Set scanning position to full screen. */
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{ MK_ILI9225_REG_GATE_SCAN_CTRL, 0x0000 },
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/* Set end scan position to 219 + 1 px (0xDB). */
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{ MK_ILI9225_REG_VERT_SCROLL_CTRL1, 0x00DB },
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/* Set start scan position to 0 px. */
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{ MK_ILI9225_REG_VERT_SCROLL_CTRL2, 0x0000 },
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/* Set scroll step to 0 px (no scrolling). */
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{ MK_ILI9225_REG_VERT_SCROLL_CTRL3, 0x0000 },
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/* Set partial screen driving end to 219 + 1 px
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* (0xDB). */
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{ MK_ILI9225_REG_PART_DRIVING_POS1, 0x00DB },
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/* Set partial screen driving start to 0 px. */
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{ MK_ILI9225_REG_PART_DRIVING_POS2, 0x0000 },
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/* Set window to 176 x 220 px (full screen). */
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{ MK_ILI9225_REG_HORI_WIN_ADDR1, 0x00AF },
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{ MK_ILI9225_REG_HORI_WIN_ADDR2, 0x0000 },
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{ MK_ILI9225_REG_VERT_WIN_ADDR1, 0x00DB },
|
|
{ MK_ILI9225_REG_VERT_WIN_ADDR2, 0x0000 },
|
|
|
|
/* Gamma curve data. */
|
|
{ MK_ILI9225_REG_GAMMA_CTRL1, 0x0000 },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL2, 0x0808 },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL3, 0x080A },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL4, 0x000A },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL5, 0x0A08 },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL6, 0x0808 },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL7, 0x0000 },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL8, 0x0A00 },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL9, 0x0710 },
|
|
{ MK_ILI9225_REG_GAMMA_CTRL10, 0x0710 },
|
|
|
|
/* Enable full colour display. */
|
|
{ MK_ILI9225_REG_DISPLAY_CTRL, 0x0012 }
|
|
};
|
|
|
|
for(uint_fast8_t i = 0; i < (uint_fast8_t)ARRAYSIZE(cmds); i++)
|
|
set_register(cmds[i].reg, cmds[i].dat);
|
|
}
|
|
mk_ili9225_delay_ms(50);
|
|
|
|
/**
|
|
* FIXME: TEMON is enabled but FLM isn't exposed?
|
|
* GON: Enable display.
|
|
* CL: Use full colour.
|
|
* REV: reverse greyscale levels.
|
|
* D: Switch on display.
|
|
*/
|
|
set_register(MK_ILI9225_REG_DISPLAY_CTRL, 0x1017);
|
|
mk_ili9225_delay_ms(50);
|
|
|
|
#if MK_ILI9225_READ_AVAILABLE
|
|
/* ret should be 0 if the returned ID was 0x9225. */
|
|
ret -= get_register(MK_ILI9225_REG_DRIVER_CODE_READ);
|
|
#else
|
|
ret = 0;
|
|
#endif
|
|
|
|
return ret;
|
|
}
|
|
|
|
void mk_ili9225_display_control(bool invert, ili9225_color_mode_e colour_mode)
|
|
{
|
|
uint16_t dat = 0x0013;
|
|
dat |= ((uint16_t)invert << 2);
|
|
dat |= ((uint16_t)colour_mode << 3);
|
|
set_register(MK_ILI9225_REG_DISPLAY_CTRL, dat);
|
|
}
|
|
|
|
void mk_ili9225_set_window(uint16_t hor_start, uint16_t hor_end,
|
|
uint16_t vert_start, uint16_t vert_end)
|
|
{
|
|
assert(hor_start < hor_end);
|
|
assert(hor_end < SCREEN_SIZE_X);
|
|
assert(vert_start < vert_end);
|
|
assert(vert_end < SCREEN_SIZE_Y);
|
|
|
|
set_register(MK_ILI9225_REG_RAM_ADDR_SET1, hor_start);
|
|
set_register(MK_ILI9225_REG_RAM_ADDR_SET2, vert_start);
|
|
set_register(MK_ILI9225_REG_HORI_WIN_ADDR1, hor_end);
|
|
set_register(MK_ILI9225_REG_HORI_WIN_ADDR2, hor_start);
|
|
set_register(MK_ILI9225_REG_VERT_WIN_ADDR1, vert_end);
|
|
set_register(MK_ILI9225_REG_VERT_WIN_ADDR2, vert_start);
|
|
}
|
|
|
|
void mk_ili9225_set_x(uint8_t x)
|
|
{
|
|
set_register(MK_ILI9225_REG_RAM_ADDR_SET1, x);
|
|
}
|
|
|
|
void mk_ili9225_set_address(uint8_t x, uint8_t y)
|
|
{
|
|
set_register(MK_ILI9225_REG_RAM_ADDR_SET1, x);
|
|
set_register(MK_ILI9225_REG_RAM_ADDR_SET2, y);
|
|
}
|
|
|
|
void mk_ili9225_write_pixels(const uint16_t *pixels, uint_fast16_t nmemb)
|
|
{
|
|
assert(pixels != NULL);
|
|
assert(nmemb > 0);
|
|
|
|
write_register(MK_ILI9225_REG_GRAM_RW);
|
|
mk_ili9225_set_rs(1);
|
|
mk_ili9225_set_cs(0);
|
|
mk_ili9225_spi_write16(pixels, nmemb);
|
|
mk_ili9225_set_cs(1);
|
|
}
|
|
|
|
void mk_ili9225_write_pixels_start(void)
|
|
{
|
|
write_register(MK_ILI9225_REG_GRAM_RW);
|
|
mk_ili9225_set_rs(1);
|
|
mk_ili9225_set_cs(0);
|
|
}
|
|
|
|
void mk_ili9225_write_pixels_end(void)
|
|
{
|
|
mk_ili9225_set_cs(1);
|
|
}
|
|
|
|
void mk_ili9225_power_control(uint8_t drive_power, bool sleep)
|
|
{
|
|
uint16_t data;
|
|
data = (uint16_t)drive_power << 8;
|
|
data |= sleep;
|
|
set_register(MK_ILI9225_REG_PWR_CTRL1, data);
|
|
}
|
|
|
|
void mk_ili9225_set_gate_scan(uint16_t hor_start, uint16_t hor_end)
|
|
{
|
|
uint16_t dat = 0x0100;
|
|
uint16_t lcd_line_start = hor_end / 8;
|
|
set_register(MK_ILI9225_REG_DRIVER_OUTPUT_CTRL, dat | lcd_line_start);
|
|
set_register(MK_ILI9225_REG_GATE_SCAN_CTRL, hor_start / 8);
|
|
}
|
|
|
|
void mk_ili9225_set_drive_freq(uint16_t f)
|
|
{
|
|
f &= 0x000F;
|
|
f <<= 8;
|
|
f |= 1;
|
|
set_register(MK_ILI9225_REG_OSC_CTRL, f);
|
|
}
|
|
|
|
void mk_ili9225_exit(void)
|
|
{
|
|
}
|