Incorporate latest peanut_gb.h from deltabeard (3d5ee50)
This commit is contained in:
+49
-15
@@ -549,7 +549,7 @@ struct gb_s
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uint8_t cart_ram;
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/* Number of ROM banks in cartridge. */
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uint16_t num_rom_banks_mask;
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/* Number of RAM banks in cartridge. */
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/* Number of RAM banks in cartridge. Ignore for MBC2. */
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uint8_t num_ram_banks;
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uint16_t selected_rom_bank;
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@@ -694,7 +694,7 @@ struct gb_s
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* Internal function used to read bytes.
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* addr is host platform endian.
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*/
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uint8_t __gb_read(struct gb_s *gb, const uint16_t addr)
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uint8_t __gb_read(struct gb_s *gb, uint16_t addr)
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{
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switch(PEANUT_GB_GET_MSN16(addr))
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{
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@@ -732,6 +732,12 @@ uint8_t __gb_read(struct gb_s *gb, const uint16_t addr)
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{
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if(gb->mbc == 3 && gb->cart_ram_bank >= 0x08)
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return gb->cart_rtc[gb->cart_ram_bank - 0x08];
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else if(gb->mbc == 2)
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{
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/* Only 9 bits are available in address. */
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addr &= 0x1FF;
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return gb->gb_cart_ram_read(gb, addr);
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}
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else if((gb->cart_mode_select || gb->mbc != 1) &&
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gb->cart_ram_bank < gb->num_ram_banks)
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{
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@@ -796,19 +802,20 @@ uint8_t __gb_read(struct gb_s *gb, const uint16_t addr)
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/**
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* Internal function used to write bytes.
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*/
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void __gb_write(struct gb_s *gb, const uint_fast16_t addr, const uint8_t val)
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void __gb_write(struct gb_s *gb, uint_fast16_t addr, uint8_t val)
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{
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switch(PEANUT_GB_GET_MSN16(addr))
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{
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case 0x0:
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case 0x1:
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if(gb->mbc == 2 && addr & 0x10)
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return;
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else if(gb->mbc > 0 && gb->cart_ram)
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/* Set RAM enable bit. MBC2 is handled in fall-through. */
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if(gb->mbc > 0 && gb->mbc != 2 && gb->cart_ram)
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{
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gb->enable_cart_ram = ((val & 0x0F) == 0x0A);
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return;
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}
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return;
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/* Intentional fall through. */
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case 0x2:
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if(gb->mbc == 5)
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{
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@@ -819,7 +826,6 @@ void __gb_write(struct gb_s *gb, const uint_fast16_t addr, const uint8_t val)
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}
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/* Intentional fall through. */
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case 0x3:
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if(gb->mbc == 1)
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{
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@@ -829,12 +835,22 @@ void __gb_write(struct gb_s *gb, const uint_fast16_t addr, const uint8_t val)
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if((gb->selected_rom_bank & 0x1F) == 0x00)
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gb->selected_rom_bank++;
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}
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else if(gb->mbc == 2 && addr & 0x10)
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else if(gb->mbc == 2)
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{
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gb->selected_rom_bank = val & 0x0F;
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if(!gb->selected_rom_bank)
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gb->selected_rom_bank++;
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/* If bit 8 is 1, then set ROM bank number. */
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if(addr & 0x100)
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{
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gb->selected_rom_bank = val & 0x0F;
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/* Setting ROM bank to 0, sets it to 1. */
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if(!gb->selected_rom_bank)
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gb->selected_rom_bank++;
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}
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/* Otherwise set whether RAM is enabled or not. */
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else
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{
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gb->enable_cart_ram = ((val & 0x0F) == 0x0A);
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return;
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}
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}
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else if(gb->mbc == 3)
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{
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@@ -876,10 +892,19 @@ void __gb_write(struct gb_s *gb, const uint_fast16_t addr, const uint8_t val)
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case 0xA:
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case 0xB:
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/* Do not write to RAM if unavailable or disabled. */
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if(gb->cart_ram && gb->enable_cart_ram)
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{
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if(gb->mbc == 3 && gb->cart_ram_bank >= 0x08)
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gb->cart_rtc[gb->cart_ram_bank - 0x08] = val;
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else if(gb->mbc == 2)
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{
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/* Only 9 bits are available in address. */
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addr &= 0x1FF;
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/* Data is only 4 bits wide in MBC2 RAM. */
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val &= 0x0F;
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gb->gb_cart_ram_write(gb, addr, val);
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}
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else if(gb->cart_mode_select &&
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gb->cart_ram_bank < gb->num_ram_banks)
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{
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@@ -3380,6 +3405,11 @@ uint_fast32_t gb_get_save_size(struct gb_s *gb)
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0x00, 0x800, 0x2000, 0x8000, 0x20000
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};
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uint8_t ram_size = gb->gb_rom_read(gb, ram_size_location);
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/* MBC2 always has 512 half-bytes of cart RAM. */
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if(gb->mbc == 2)
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return 0x200;
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return ram_sizes[ram_size];
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}
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@@ -3511,7 +3541,7 @@ enum gb_init_error_e gb_init(struct gb_s *gb,
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};
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const uint8_t cart_ram[] =
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{
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0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
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1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0
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};
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const uint16_t num_rom_banks_mask[] =
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@@ -3558,6 +3588,10 @@ enum gb_init_error_e gb_init(struct gb_s *gb,
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gb->num_rom_banks_mask = num_rom_banks_mask[gb->gb_rom_read(gb, bank_count_location)] - 1;
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gb->num_ram_banks = num_ram_banks[gb->gb_rom_read(gb, ram_size_location)];
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/* Note that MBC2 will appear to have no RAM banks, but it actually
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* always has 512 half-bytes of RAM. Hence, gb->num_ram_banks must be
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* ignored for MBC2. */
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gb->lcd_blank = 0;
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gb->display.lcd_draw_line = NULL;
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