578 lines
17 KiB
C++
578 lines
17 KiB
C++
/*!
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* @file Adafruit_ZeroI2S.cpp
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*
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* @mainpage Adafruit I2S peripheral driver for SAMD21 and SAMD51 chips
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*
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* @section intro_sec Introduction
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*
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* I2S peripheral driver for SAMD21 and SAMD51 chips
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*
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*
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* Adafruit invests time and resources providing this open source code,
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* please support Adafruit and open-source hardware by purchasing
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* products from Adafruit!
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*
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* @section author Author
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*
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* Written by Dean Miller for Adafruit Industries.
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*
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* @section license License
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*
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* BSD license, all text here must be included in any redistribution.
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*
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*/
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#include "I2S.h"
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#include "wiring_private.h"
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#ifndef DEBUG_PRINTLN
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#define DEBUG_PRINTLN Serial.println ///< where to print the debug output
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#endif
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/**************************************************************************/
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/*!
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@brief Class Constructor
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@param FS_PIN frame sync pin
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@param SCK_PIN bit clock pin
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@param TX_PIN data output pin
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@param RX_PIN data input pin
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*/
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/**************************************************************************/
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I2S_class::I2S_class(uint8_t FS_PIN, uint8_t SCK_PIN,
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uint8_t TX_PIN, uint8_t RX_PIN)
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: _fs(FS_PIN), _sck(SCK_PIN), _tx(TX_PIN), _rx(RX_PIN) {}
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#if defined(PIN_I2S_SDI) && defined(PIN_I2S_SDO)
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/**************************************************************************/
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/*!
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@brief Class Constructor with defaults
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*/
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/**************************************************************************/
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I2S_class::I2S_class()
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: _fs(PIN_I2S_FS), _sck(PIN_I2S_SCK), _tx(PIN_I2S_SDO), _rx(PIN_I2S_SDI) {}
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#else
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/**************************************************************************/
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/*!
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@brief Class Constructor with defaults
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*/
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/**************************************************************************/
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Adafruit_ZeroI2S::Adafruit_ZeroI2S()
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: _fs(PIN_I2S_FS), _sck(PIN_I2S_SCK), _tx(PIN_I2S_SD) {
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_rx = -1;
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}
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#endif
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/**************************************************************************/
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/*!
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@brief start up the I2S peripheral
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@param width the width of each I2S frame
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@param fs_freq the frame sync frequency (a.k.a. sample rate)
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@param mck_mult master clock output will be fs_freq * mck_mult for chips
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that have a mclk.
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@returns true on success, false on any error
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*/
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/**************************************************************************/
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bool I2S_class::begin(I2SSlotSize width, int fs_freq, int mck_mult) {
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#if defined(__SAMD51__)
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pinPeripheral(_fs, PIO_I2S);
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pinPeripheral(_sck, PIO_I2S);
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pinPeripheral(_rx, PIO_I2S);
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pinPeripheral(_tx, PIO_I2S);
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I2S->CTRLA.bit.ENABLE = 0;
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// initialize clock control
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_I2S;
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uint32_t mckFreq = (fs_freq * mck_mult);
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uint32_t sckFreq = fs_freq * I2S_NUM_SLOTS * ((width + 1) << 3);
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uint32_t gclkval = GCLK_PCHCTRL_GEN_GCLK1_Val;
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uint32_t gclkFreq = VARIANT_GCLK1_FREQ;
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uint8_t mckoutdiv = min((gclkFreq / mckFreq) - 1U, 63U);
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uint8_t mckdiv = min((gclkFreq / sckFreq) - 1U, 63U);
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if (((VARIANT_GCLK1_FREQ / mckFreq) - 1) > 63) {
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gclkval = GCLK_PCHCTRL_GEN_GCLK4_Val;
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gclkFreq = 12000000;
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}
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GCLK->PCHCTRL[I2S_GCLK_ID_0].reg = gclkval | (1 << GCLK_PCHCTRL_CHEN_Pos);
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GCLK->PCHCTRL[I2S_GCLK_ID_1].reg = gclkval | (1 << GCLK_PCHCTRL_CHEN_Pos);
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// software reset
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I2S->CTRLA.bit.SWRST = 1;
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while (I2S->SYNCBUSY.bit.SWRST || I2S->SYNCBUSY.bit.ENABLE)
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; // wait for sync
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// CLKCTRL[0] is used for the tx channel
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I2S->CLKCTRL[0].reg =
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I2S_CLKCTRL_MCKSEL_GCLK | I2S_CLKCTRL_MCKOUTDIV(mckoutdiv) |
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I2S_CLKCTRL_MCKDIV(mckdiv) | I2S_CLKCTRL_SCKSEL_MCKDIV |
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I2S_CLKCTRL_MCKEN | I2S_CLKCTRL_FSSEL_SCKDIV | I2S_CLKCTRL_BITDELAY_I2S |
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I2S_CLKCTRL_FSWIDTH_HALF | I2S_CLKCTRL_NBSLOTS(I2S_NUM_SLOTS - 1) |
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I2S_CLKCTRL_SLOTSIZE(width);
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uint8_t wordSize=0;
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switch (width) {
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case I2S_8_BIT:
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wordSize = I2S_TXCTRL_DATASIZE_8_Val;
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break;
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case I2S_16_BIT:
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wordSize = I2S_TXCTRL_DATASIZE_16_Val;
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break;
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case I2S_24_BIT:
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wordSize = I2S_TXCTRL_DATASIZE_24_Val;
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break;
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case I2S_32_BIT:
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wordSize = I2S_TXCTRL_DATASIZE_32_Val;
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break;
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}
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I2S->TXCTRL.reg = I2S_TXCTRL_DMA_SINGLE | I2S_TXCTRL_MONO_STEREO |
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I2S_TXCTRL_BITREV_MSBIT | I2S_TXCTRL_EXTEND_ZERO |
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I2S_TXCTRL_WORDADJ_RIGHT | I2S_TXCTRL_DATASIZE(wordSize) |
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I2S_TXCTRL_TXSAME_ZERO | I2S_TXCTRL_TXDEFAULT_ZERO;
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I2S->RXCTRL.reg = I2S_RXCTRL_DMA_SINGLE | I2S_RXCTRL_MONO_STEREO |
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I2S_RXCTRL_BITREV_MSBIT | I2S_RXCTRL_EXTEND_ZERO |
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I2S_RXCTRL_WORDADJ_RIGHT | I2S_RXCTRL_DATASIZE(wordSize) |
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I2S_RXCTRL_SLOTADJ_RIGHT | I2S_RXCTRL_CLKSEL_CLK0 |
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I2S_RXCTRL_SERMODE_RX;
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while (I2S->SYNCBUSY.bit.ENABLE)
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; // wait for sync
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I2S->CTRLA.bit.ENABLE = 1;
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return true;
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#else // SAMD21
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_i2sserializer = -1;
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_i2sclock = -1;
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uint32_t _clk_pin, _clk_mux, _data_pin, _data_mux, _fs_pin, _fs_mux;
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// Clock pin, can only be one of 3 options
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uint32_t clockport = g_APinDescription[_sck].ulPort;
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uint32_t clockpin = g_APinDescription[_sck].ulPin;
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if ((clockport == 0) && (clockpin == 10)) {
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// PA10
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_i2sclock = 0;
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_clk_pin = PIN_PA10G_I2S_SCK0;
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_clk_mux = MUX_PA10G_I2S_SCK0;
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#if defined(PIN_PB11G_I2S_SCK1)
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} else if ((clockport == 1) && (clockpin == 11)) {
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// PB11
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_i2sclock = 1;
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_clk_pin = PIN_PB11G_I2S_SCK1;
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_clk_mux = MUX_PB11G_I2S_SCK1;
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#endif
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#if defined(PIN_PA20G_I2S_SCK0)
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} else if ((clockport == 0) && (clockpin == 20)) {
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// PA20
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_i2sclock = 0;
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_clk_pin = PIN_PA20G_I2S_SCK0;
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_clk_mux = MUX_PA20G_I2S_SCK0;
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#endif
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} else {
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DEBUG_PRINTLN("Clock isnt on a valid pin");
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return false;
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}
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pinPeripheral(_sck, (EPioType)_clk_mux);
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// FS pin, can only be one of 2 options
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uint32_t fsport = g_APinDescription[_fs].ulPort;
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uint32_t fspin = g_APinDescription[_fs].ulPin;
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if ((fsport == 0) && (fspin == 11)) {
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// PA11
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_fs_pin = PIN_PA11G_I2S_FS0;
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_fs_mux = MUX_PA11G_I2S_FS0;
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#if defined(PIN_PA21G_I2S_FS0)
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} else if ((fsport == 0) && (fspin == 21)) {
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// PA21
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_fs_pin = PIN_PA21G_I2S_FS0;
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_fs_mux = MUX_PA21G_I2S_FS0;
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#endif
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} else {
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DEBUG_PRINTLN("FS isnt on a valid pin");
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return false;
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}
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pinPeripheral(_fs, (EPioType)_fs_mux);
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uint32_t i2sGCLK;
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if (_i2sclock == 0)
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i2sGCLK = I2S_GCLK_ID_0;
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else
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i2sGCLK = I2S_GCLK_ID_1;
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uint32_t divider = fs_freq * 2 * (width + 1) * 8;
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// configure the clock divider
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while (GCLK->STATUS.bit.SYNCBUSY)
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;
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GCLK->GENDIV.bit.ID = I2S_CLOCK_GENERATOR;
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GCLK->GENDIV.bit.DIV = SystemCoreClock / divider;
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// use the DFLL as the source
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while (GCLK->STATUS.bit.SYNCBUSY)
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;
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GCLK->GENCTRL.bit.ID = I2S_CLOCK_GENERATOR;
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GCLK->GENCTRL.bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val;
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GCLK->GENCTRL.bit.IDC = 1;
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GCLK->GENCTRL.bit.GENEN = 1;
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// enable
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while (GCLK->STATUS.bit.SYNCBUSY)
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;
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GCLK->CLKCTRL.bit.ID = i2sGCLK;
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GCLK->CLKCTRL.bit.GEN = I2S_CLOCK_GENERATOR;
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GCLK->CLKCTRL.bit.CLKEN = 1;
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while (GCLK->STATUS.bit.SYNCBUSY)
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;
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// Data pin, can only be one of 3 options
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uint32_t datapin = g_APinDescription[_tx].ulPin;
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uint32_t dataport = g_APinDescription[_tx].ulPort;
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if ((dataport == 0) && (datapin == 7)) {
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// PA07
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_i2sserializer = 0;
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_data_pin = PIN_PA07G_I2S_SD0;
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_data_mux = MUX_PA07G_I2S_SD0;
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} else if ((dataport == 0) && (datapin == 8)) {
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// PA08
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_i2sserializer = 1;
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_data_pin = PIN_PA08G_I2S_SD1;
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_data_mux = MUX_PA08G_I2S_SD1;
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} else if ((dataport == 0) && (datapin == 19)) {
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// PA19
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_i2sserializer = 0;
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_data_pin = PIN_PA19G_I2S_SD0;
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_data_mux = MUX_PA19G_I2S_SD0;
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} else {
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DEBUG_PRINTLN("Data isnt on a valid pin");
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return false;
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}
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pinPeripheral(_tx, (EPioType)_data_mux);
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PM->APBCMASK.reg |= PM_APBCMASK_I2S;
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I2S->CTRLA.bit.ENABLE = 0;
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while (I2S->SYNCBUSY.bit.ENABLE)
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;
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if (_i2sclock == 0)
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I2S->CTRLA.bit.CKEN0 = 0;
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else
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I2S->CTRLA.bit.CKEN1 = 0;
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while (I2S->SYNCBUSY.bit.CKEN0 || I2S->SYNCBUSY.bit.CKEN1)
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;
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I2S->CLKCTRL[_i2sclock].reg =
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I2S_CLKCTRL_MCKSEL_GCLK | I2S_CLKCTRL_SCKSEL_MCKDIV |
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I2S_CLKCTRL_FSSEL_SCKDIV | I2S_CLKCTRL_BITDELAY_I2S |
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I2S_CLKCTRL_NBSLOTS(I2S_NUM_SLOTS - 1) | I2S_CLKCTRL_SLOTSIZE(width);
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uint8_t wordSize;
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switch (width) {
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case I2S_8_BIT:
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wordSize = I2S_SERCTRL_DATASIZE_8_Val;
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break;
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case I2S_16_BIT:
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wordSize = I2S_SERCTRL_DATASIZE_16_Val;
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break;
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case I2S_24_BIT:
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wordSize = I2S_SERCTRL_DATASIZE_24_Val;
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break;
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case I2S_32_BIT:
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wordSize = I2S_SERCTRL_DATASIZE_32_Val;
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break;
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default:
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DEBUG_PRINTLN("invalid width!");
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return false;
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}
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if (_i2sserializer == 0)
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I2S->CTRLA.bit.SEREN0 = 0;
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else
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I2S->CTRLA.bit.SEREN1 = 0;
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while (I2S->SYNCBUSY.bit.SEREN0 || I2S->SYNCBUSY.bit.SEREN1)
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;
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I2S->SERCTRL[_i2sserializer].reg =
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I2S_SERCTRL_DMA_SINGLE | I2S_SERCTRL_MONO_STEREO |
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I2S_SERCTRL_BITREV_MSBIT | I2S_SERCTRL_EXTEND_ZERO |
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I2S_SERCTRL_WORDADJ_RIGHT | I2S_SERCTRL_DATASIZE(wordSize) |
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I2S_SERCTRL_SLOTADJ_RIGHT |
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((uint32_t)_i2sclock << I2S_SERCTRL_CLKSEL_Pos);
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return true;
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#endif
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}
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/**************************************************************************/
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/*!
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@brief enable data output. Note that on SAMD21 chips either rx or tx can be
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enabled on an Adafruit_ZeroI2S instance, while on SAMD51 the same
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Adafruit_ZeroI2S instance can have both rx and tx channels enabled.
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*/
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/**************************************************************************/
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void I2S_class::enableTx() {
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#if defined(__SAMD51__)
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I2S->CTRLA.bit.CKEN0 = 1;
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while (I2S->SYNCBUSY.bit.CKEN0)
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;
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I2S->CTRLA.bit.TXEN = 1;
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while (I2S->SYNCBUSY.bit.TXEN)
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;
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#else
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if (_i2sserializer > -1 && _i2sclock > -1) {
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I2S->CTRLA.bit.ENABLE = 0;
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while (I2S->SYNCBUSY.bit.ENABLE)
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;
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I2S->SERCTRL[_i2sserializer].bit.SERMODE = I2S_SERCTRL_SERMODE_TX;
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if (_i2sserializer == 0)
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I2S->CTRLA.bit.SEREN0 = 1;
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else
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I2S->CTRLA.bit.SEREN1 = 1;
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if (_i2sclock == 0)
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I2S->CTRLA.bit.CKEN0 = 1;
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else
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I2S->CTRLA.bit.CKEN1 = 1;
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I2S->CTRLA.bit.ENABLE = 1;
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while (I2S->SYNCBUSY.bit.ENABLE || I2S->SYNCBUSY.bit.CKEN0 ||
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I2S->SYNCBUSY.bit.CKEN1 || I2S->SYNCBUSY.bit.SEREN0 ||
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I2S->SYNCBUSY.bit.SEREN1)
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;
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}
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#endif
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}
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/**************************************************************************/
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/*!
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@brief disable data output
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*/
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/**************************************************************************/
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void I2S_class::disableTx() {
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#if defined(__SAMD51__)
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I2S->CTRLA.bit.TXEN = 0;
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while (I2S->SYNCBUSY.bit.TXEN)
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;
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#else
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#endif
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}
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/**************************************************************************/
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/*!
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@brief enable data input. Note that on SAMD21 chips either rx or tx can be
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enabled on an Adafruit_ZeroI2S instance, while on SAMD51 the same
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Adafruit_ZeroI2S instance can have both rx and tx channels enabled.
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*/
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/**************************************************************************/
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void I2S_class::enableRx() {
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#if defined(__SAMD51__)
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I2S->CTRLA.bit.CKEN0 = 1;
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while (I2S->SYNCBUSY.bit.CKEN0)
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;
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I2S->CTRLA.bit.RXEN = 1;
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while (I2S->SYNCBUSY.bit.RXEN)
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;
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#else
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if (_i2sserializer > -1 && _i2sclock > -1) {
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I2S->CTRLA.bit.ENABLE = 0;
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while (I2S->SYNCBUSY.bit.ENABLE)
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;
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I2S->SERCTRL[_i2sserializer].bit.SERMODE = I2S_SERCTRL_SERMODE_RX;
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if (_i2sserializer == 0)
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I2S->CTRLA.bit.SEREN0 = 1;
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else
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I2S->CTRLA.bit.SEREN1 = 1;
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if (_i2sclock == 0)
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I2S->CTRLA.bit.CKEN0 = 1;
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else
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I2S->CTRLA.bit.CKEN1 = 1;
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I2S->CTRLA.bit.ENABLE = 1;
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while (I2S->SYNCBUSY.bit.ENABLE || I2S->SYNCBUSY.bit.CKEN0 ||
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I2S->SYNCBUSY.bit.CKEN1 || I2S->SYNCBUSY.bit.SEREN0 ||
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I2S->SYNCBUSY.bit.SEREN1)
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;
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}
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#endif
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}
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/**************************************************************************/
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/*!
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@brief disable data input
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*/
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/**************************************************************************/
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void I2S_class::disableRx() {
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#if defined(__SAMD51__)
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I2S->CTRLA.bit.RXEN = 0;
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while (I2S->SYNCBUSY.bit.RXEN)
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;
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#else
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#endif
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}
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/**************************************************************************/
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/*!
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@brief enable master clock output on devices that have a master clock
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output.
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*/
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/**************************************************************************/
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void I2S_class::enableMCLK() {
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#ifdef PIN_I2S_MCK
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pinPeripheral(PIN_I2S_MCK, PIO_I2S);
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#endif
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}
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/**************************************************************************/
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/*!
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@brief disable master clock output on devices that have a master clock
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output.
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*/
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/**************************************************************************/
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void I2S_class::disableMCLK() {
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#ifdef PIN_I2S_MCK
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pinMode(PIN_I2S_MCK, INPUT);
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#endif
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}
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/**************************************************************************/
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/*!
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@brief check if data can be written to the TX data register
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@returns true if data can be written, false otherwise
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*/
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/**************************************************************************/
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bool I2S_class::txReady() {
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#if defined(__SAMD51__)
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return !((!I2S->INTFLAG.bit.TXRDY0) || I2S->SYNCBUSY.bit.TXDATA);
|
|
#else
|
|
if (_i2sserializer > -1) {
|
|
if (_i2sserializer == 0) {
|
|
return !((!I2S->INTFLAG.bit.TXRDY0) || I2S->SYNCBUSY.bit.DATA0);
|
|
} else {
|
|
return !((!I2S->INTFLAG.bit.TXRDY1) || I2S->SYNCBUSY.bit.DATA1);
|
|
}
|
|
} else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
/**************************************************************************/
|
|
/*!
|
|
@brief check if data is available to be read from the RX data register
|
|
@returns true if data is available, false otherwise
|
|
*/
|
|
/**************************************************************************/
|
|
bool I2S_class::rxReady() {
|
|
#if defined(__SAMD51__)
|
|
return !((!I2S->INTFLAG.bit.RXRDY0) || I2S->SYNCBUSY.bit.RXDATA);
|
|
#else
|
|
if (_i2sserializer > -1) {
|
|
if (_i2sserializer == 0) {
|
|
return !((!I2S->INTFLAG.bit.RXRDY0) || I2S->SYNCBUSY.bit.DATA0);
|
|
} else {
|
|
return !((!I2S->INTFLAG.bit.RXRDY1) || I2S->SYNCBUSY.bit.DATA1);
|
|
}
|
|
} else
|
|
return false;
|
|
#endif
|
|
}
|
|
|
|
/**************************************************************************/
|
|
/*!
|
|
@brief perform a blocking write to the I2S peripheral. This function will
|
|
only return once all data has been sent.
|
|
@param left the left channel data
|
|
@param right the right channel data
|
|
*/
|
|
/**************************************************************************/
|
|
void I2S_class::write(int32_t left, int32_t right) {
|
|
#if defined(__SAMD51__)
|
|
while ((!I2S->INTFLAG.bit.TXRDY0) || I2S->SYNCBUSY.bit.TXDATA)
|
|
;
|
|
I2S->INTFLAG.bit.TXUR0 = 1;
|
|
I2S->TXDATA.reg = left;
|
|
|
|
while ((!I2S->INTFLAG.bit.TXRDY0) || I2S->SYNCBUSY.bit.TXDATA)
|
|
;
|
|
I2S->INTFLAG.bit.TXUR0 = 1;
|
|
I2S->TXDATA.reg = right;
|
|
#else
|
|
if (_i2sserializer > -1) {
|
|
if (_i2sserializer == 0) {
|
|
while ((!I2S->INTFLAG.bit.TXRDY0) || I2S->SYNCBUSY.bit.DATA0)
|
|
;
|
|
I2S->INTFLAG.bit.TXUR0 = 1;
|
|
I2S->DATA[0].reg = left;
|
|
|
|
while ((!I2S->INTFLAG.bit.TXRDY0) || I2S->SYNCBUSY.bit.DATA0)
|
|
;
|
|
I2S->INTFLAG.bit.TXUR0 = 1;
|
|
I2S->DATA[0].reg = right;
|
|
} else {
|
|
while ((!I2S->INTFLAG.bit.TXRDY1) || I2S->SYNCBUSY.bit.DATA1)
|
|
;
|
|
I2S->INTFLAG.bit.TXUR1 = 1;
|
|
I2S->DATA[1].reg = left;
|
|
|
|
while ((!I2S->INTFLAG.bit.TXRDY1) || I2S->SYNCBUSY.bit.DATA1)
|
|
;
|
|
I2S->INTFLAG.bit.TXUR1 = 1;
|
|
I2S->DATA[1].reg = right;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/**************************************************************************/
|
|
/*!
|
|
@brief perform a blocking read to the I2S peripheral. This function will
|
|
only return once all data has been read.
|
|
@param left pointer to where the left channel data will be written
|
|
@param right pointer to where the right channel data will be written
|
|
*/
|
|
/**************************************************************************/
|
|
void I2S_class::read(int32_t *left, int32_t *right) {
|
|
#if defined(__SAMD51__)
|
|
while ((!I2S->INTFLAG.bit.RXRDY0) || I2S->SYNCBUSY.bit.RXDATA)
|
|
;
|
|
*left = I2S->RXDATA.reg;
|
|
|
|
while ((!I2S->INTFLAG.bit.RXRDY0) || I2S->SYNCBUSY.bit.RXDATA)
|
|
;
|
|
*right = I2S->RXDATA.reg;
|
|
#else
|
|
if (_i2sserializer > -1) {
|
|
if (_i2sserializer == 0) {
|
|
while ((!I2S->INTFLAG.bit.RXRDY0) || I2S->SYNCBUSY.bit.DATA0)
|
|
;
|
|
*left = I2S->DATA[0].reg;
|
|
|
|
while ((!I2S->INTFLAG.bit.RXRDY0) || I2S->SYNCBUSY.bit.DATA0)
|
|
;
|
|
*right = I2S->DATA[0].reg;
|
|
} else {
|
|
while ((!I2S->INTFLAG.bit.RXRDY1) || I2S->SYNCBUSY.bit.DATA1)
|
|
;
|
|
*left = I2S->DATA[1].reg;
|
|
|
|
while ((!I2S->INTFLAG.bit.RXRDY1) || I2S->SYNCBUSY.bit.DATA1)
|
|
;
|
|
*right = I2S->DATA[1].reg;
|
|
}
|
|
}
|
|
#endif
|
|
}
|