projects_leo/muziekdoos
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8f776b818a2a90a84a6a79dc3bd8c2d61b68659f
muziekdoos/STM32Cube/leo_muziekdoos/Debug/leo_muziekdoos.list
Willem Oldemans 155b302765 pcb routing ready
2021-08-08 21:15:37 +02:00

15866 lines
580 KiB
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leo_muziekdoos.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000198 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 0000597c 08000198 08000198 00010198 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000002c 08005b14 08005b14 00015b14 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08005b40 08005b40 0002000c 2**0
CONTENTS
4 .ARM 00000008 08005b40 08005b40 00015b40 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08005b48 08005b48 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08005b48 08005b48 00015b48 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08005b4c 08005b4c 00015b4c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08005b50 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000950 2000000c 08005b5c 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000095c 08005b5c 0002095c 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .debug_info 00016ce1 00000000 00000000 0002003c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003561 00000000 00000000 00036d1d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000012a8 00000000 00000000 0003a280 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00001150 00000000 00000000 0003b528 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00019ef3 00000000 00000000 0003c678 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00017416 00000000 00000000 0005656b 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0009bc88 00000000 00000000 0006d981 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 00109609 2**0
CONTENTS, READONLY
20 .debug_frame 00004d8c 00000000 00000000 0010965c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000198 <__do_global_dtors_aux>:
8000198: b510 push {r4, lr}
800019a: 4c05 ldr r4, [pc, #20] ; (80001b0 <__do_global_dtors_aux+0x18>)
800019c: 7823 ldrb r3, [r4, #0]
800019e: b933 cbnz r3, 80001ae <__do_global_dtors_aux+0x16>
80001a0: 4b04 ldr r3, [pc, #16] ; (80001b4 <__do_global_dtors_aux+0x1c>)
80001a2: b113 cbz r3, 80001aa <__do_global_dtors_aux+0x12>
80001a4: 4804 ldr r0, [pc, #16] ; (80001b8 <__do_global_dtors_aux+0x20>)
80001a6: f3af 8000 nop.w
80001aa: 2301 movs r3, #1
80001ac: 7023 strb r3, [r4, #0]
80001ae: bd10 pop {r4, pc}
80001b0: 2000000c .word 0x2000000c
80001b4: 00000000 .word 0x00000000
80001b8: 08005afc .word 0x08005afc
080001bc <frame_dummy>:
80001bc: b508 push {r3, lr}
80001be: 4b03 ldr r3, [pc, #12] ; (80001cc <frame_dummy+0x10>)
80001c0: b11b cbz r3, 80001ca <frame_dummy+0xe>
80001c2: 4903 ldr r1, [pc, #12] ; (80001d0 <frame_dummy+0x14>)
80001c4: 4803 ldr r0, [pc, #12] ; (80001d4 <frame_dummy+0x18>)
80001c6: f3af 8000 nop.w
80001ca: bd08 pop {r3, pc}
80001cc: 00000000 .word 0x00000000
80001d0: 20000010 .word 0x20000010
80001d4: 08005afc .word 0x08005afc
080001d8 <__aeabi_uldivmod>:
80001d8: b953 cbnz r3, 80001f0 <__aeabi_uldivmod+0x18>
80001da: b94a cbnz r2, 80001f0 <__aeabi_uldivmod+0x18>
80001dc: 2900 cmp r1, #0
80001de: bf08 it eq
80001e0: 2800 cmpeq r0, #0
80001e2: bf1c itt ne
80001e4: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff
80001e8: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff
80001ec: f000 b96e b.w 80004cc <__aeabi_idiv0>
80001f0: f1ad 0c08 sub.w ip, sp, #8
80001f4: e96d ce04 strd ip, lr, [sp, #-16]!
80001f8: f000 f806 bl 8000208 <__udivmoddi4>
80001fc: f8dd e004 ldr.w lr, [sp, #4]
8000200: e9dd 2302 ldrd r2, r3, [sp, #8]
8000204: b004 add sp, #16
8000206: 4770 bx lr
08000208 <__udivmoddi4>:
8000208: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800020c: 9d08 ldr r5, [sp, #32]
800020e: 4604 mov r4, r0
8000210: 468c mov ip, r1
8000212: 2b00 cmp r3, #0
8000214: f040 8083 bne.w 800031e <__udivmoddi4+0x116>
8000218: 428a cmp r2, r1
800021a: 4617 mov r7, r2
800021c: d947 bls.n 80002ae <__udivmoddi4+0xa6>
800021e: fab2 f282 clz r2, r2
8000222: b142 cbz r2, 8000236 <__udivmoddi4+0x2e>
8000224: f1c2 0020 rsb r0, r2, #32
8000228: fa24 f000 lsr.w r0, r4, r0
800022c: 4091 lsls r1, r2
800022e: 4097 lsls r7, r2
8000230: ea40 0c01 orr.w ip, r0, r1
8000234: 4094 lsls r4, r2
8000236: ea4f 4817 mov.w r8, r7, lsr #16
800023a: 0c23 lsrs r3, r4, #16
800023c: fbbc f6f8 udiv r6, ip, r8
8000240: fa1f fe87 uxth.w lr, r7
8000244: fb08 c116 mls r1, r8, r6, ip
8000248: ea43 4301 orr.w r3, r3, r1, lsl #16
800024c: fb06 f10e mul.w r1, r6, lr
8000250: 4299 cmp r1, r3
8000252: d909 bls.n 8000268 <__udivmoddi4+0x60>
8000254: 18fb adds r3, r7, r3
8000256: f106 30ff add.w r0, r6, #4294967295 ; 0xffffffff
800025a: f080 8119 bcs.w 8000490 <__udivmoddi4+0x288>
800025e: 4299 cmp r1, r3
8000260: f240 8116 bls.w 8000490 <__udivmoddi4+0x288>
8000264: 3e02 subs r6, #2
8000266: 443b add r3, r7
8000268: 1a5b subs r3, r3, r1
800026a: b2a4 uxth r4, r4
800026c: fbb3 f0f8 udiv r0, r3, r8
8000270: fb08 3310 mls r3, r8, r0, r3
8000274: ea44 4403 orr.w r4, r4, r3, lsl #16
8000278: fb00 fe0e mul.w lr, r0, lr
800027c: 45a6 cmp lr, r4
800027e: d909 bls.n 8000294 <__udivmoddi4+0x8c>
8000280: 193c adds r4, r7, r4
8000282: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
8000286: f080 8105 bcs.w 8000494 <__udivmoddi4+0x28c>
800028a: 45a6 cmp lr, r4
800028c: f240 8102 bls.w 8000494 <__udivmoddi4+0x28c>
8000290: 3802 subs r0, #2
8000292: 443c add r4, r7
8000294: ea40 4006 orr.w r0, r0, r6, lsl #16
8000298: eba4 040e sub.w r4, r4, lr
800029c: 2600 movs r6, #0
800029e: b11d cbz r5, 80002a8 <__udivmoddi4+0xa0>
80002a0: 40d4 lsrs r4, r2
80002a2: 2300 movs r3, #0
80002a4: e9c5 4300 strd r4, r3, [r5]
80002a8: 4631 mov r1, r6
80002aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002ae: b902 cbnz r2, 80002b2 <__udivmoddi4+0xaa>
80002b0: deff udf #255 ; 0xff
80002b2: fab2 f282 clz r2, r2
80002b6: 2a00 cmp r2, #0
80002b8: d150 bne.n 800035c <__udivmoddi4+0x154>
80002ba: 1bcb subs r3, r1, r7
80002bc: ea4f 4e17 mov.w lr, r7, lsr #16
80002c0: fa1f f887 uxth.w r8, r7
80002c4: 2601 movs r6, #1
80002c6: fbb3 fcfe udiv ip, r3, lr
80002ca: 0c21 lsrs r1, r4, #16
80002cc: fb0e 331c mls r3, lr, ip, r3
80002d0: ea41 4103 orr.w r1, r1, r3, lsl #16
80002d4: fb08 f30c mul.w r3, r8, ip
80002d8: 428b cmp r3, r1
80002da: d907 bls.n 80002ec <__udivmoddi4+0xe4>
80002dc: 1879 adds r1, r7, r1
80002de: f10c 30ff add.w r0, ip, #4294967295 ; 0xffffffff
80002e2: d202 bcs.n 80002ea <__udivmoddi4+0xe2>
80002e4: 428b cmp r3, r1
80002e6: f200 80e9 bhi.w 80004bc <__udivmoddi4+0x2b4>
80002ea: 4684 mov ip, r0
80002ec: 1ac9 subs r1, r1, r3
80002ee: b2a3 uxth r3, r4
80002f0: fbb1 f0fe udiv r0, r1, lr
80002f4: fb0e 1110 mls r1, lr, r0, r1
80002f8: ea43 4401 orr.w r4, r3, r1, lsl #16
80002fc: fb08 f800 mul.w r8, r8, r0
8000300: 45a0 cmp r8, r4
8000302: d907 bls.n 8000314 <__udivmoddi4+0x10c>
8000304: 193c adds r4, r7, r4
8000306: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
800030a: d202 bcs.n 8000312 <__udivmoddi4+0x10a>
800030c: 45a0 cmp r8, r4
800030e: f200 80d9 bhi.w 80004c4 <__udivmoddi4+0x2bc>
8000312: 4618 mov r0, r3
8000314: eba4 0408 sub.w r4, r4, r8
8000318: ea40 400c orr.w r0, r0, ip, lsl #16
800031c: e7bf b.n 800029e <__udivmoddi4+0x96>
800031e: 428b cmp r3, r1
8000320: d909 bls.n 8000336 <__udivmoddi4+0x12e>
8000322: 2d00 cmp r5, #0
8000324: f000 80b1 beq.w 800048a <__udivmoddi4+0x282>
8000328: 2600 movs r6, #0
800032a: e9c5 0100 strd r0, r1, [r5]
800032e: 4630 mov r0, r6
8000330: 4631 mov r1, r6
8000332: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000336: fab3 f683 clz r6, r3
800033a: 2e00 cmp r6, #0
800033c: d14a bne.n 80003d4 <__udivmoddi4+0x1cc>
800033e: 428b cmp r3, r1
8000340: d302 bcc.n 8000348 <__udivmoddi4+0x140>
8000342: 4282 cmp r2, r0
8000344: f200 80b8 bhi.w 80004b8 <__udivmoddi4+0x2b0>
8000348: 1a84 subs r4, r0, r2
800034a: eb61 0103 sbc.w r1, r1, r3
800034e: 2001 movs r0, #1
8000350: 468c mov ip, r1
8000352: 2d00 cmp r5, #0
8000354: d0a8 beq.n 80002a8 <__udivmoddi4+0xa0>
8000356: e9c5 4c00 strd r4, ip, [r5]
800035a: e7a5 b.n 80002a8 <__udivmoddi4+0xa0>
800035c: f1c2 0320 rsb r3, r2, #32
8000360: fa20 f603 lsr.w r6, r0, r3
8000364: 4097 lsls r7, r2
8000366: fa01 f002 lsl.w r0, r1, r2
800036a: ea4f 4e17 mov.w lr, r7, lsr #16
800036e: 40d9 lsrs r1, r3
8000370: 4330 orrs r0, r6
8000372: 0c03 lsrs r3, r0, #16
8000374: fbb1 f6fe udiv r6, r1, lr
8000378: fa1f f887 uxth.w r8, r7
800037c: fb0e 1116 mls r1, lr, r6, r1
8000380: ea43 4301 orr.w r3, r3, r1, lsl #16
8000384: fb06 f108 mul.w r1, r6, r8
8000388: 4299 cmp r1, r3
800038a: fa04 f402 lsl.w r4, r4, r2
800038e: d909 bls.n 80003a4 <__udivmoddi4+0x19c>
8000390: 18fb adds r3, r7, r3
8000392: f106 3cff add.w ip, r6, #4294967295 ; 0xffffffff
8000396: f080 808d bcs.w 80004b4 <__udivmoddi4+0x2ac>
800039a: 4299 cmp r1, r3
800039c: f240 808a bls.w 80004b4 <__udivmoddi4+0x2ac>
80003a0: 3e02 subs r6, #2
80003a2: 443b add r3, r7
80003a4: 1a5b subs r3, r3, r1
80003a6: b281 uxth r1, r0
80003a8: fbb3 f0fe udiv r0, r3, lr
80003ac: fb0e 3310 mls r3, lr, r0, r3
80003b0: ea41 4103 orr.w r1, r1, r3, lsl #16
80003b4: fb00 f308 mul.w r3, r0, r8
80003b8: 428b cmp r3, r1
80003ba: d907 bls.n 80003cc <__udivmoddi4+0x1c4>
80003bc: 1879 adds r1, r7, r1
80003be: f100 3cff add.w ip, r0, #4294967295 ; 0xffffffff
80003c2: d273 bcs.n 80004ac <__udivmoddi4+0x2a4>
80003c4: 428b cmp r3, r1
80003c6: d971 bls.n 80004ac <__udivmoddi4+0x2a4>
80003c8: 3802 subs r0, #2
80003ca: 4439 add r1, r7
80003cc: 1acb subs r3, r1, r3
80003ce: ea40 4606 orr.w r6, r0, r6, lsl #16
80003d2: e778 b.n 80002c6 <__udivmoddi4+0xbe>
80003d4: f1c6 0c20 rsb ip, r6, #32
80003d8: fa03 f406 lsl.w r4, r3, r6
80003dc: fa22 f30c lsr.w r3, r2, ip
80003e0: 431c orrs r4, r3
80003e2: fa20 f70c lsr.w r7, r0, ip
80003e6: fa01 f306 lsl.w r3, r1, r6
80003ea: ea4f 4e14 mov.w lr, r4, lsr #16
80003ee: fa21 f10c lsr.w r1, r1, ip
80003f2: 431f orrs r7, r3
80003f4: 0c3b lsrs r3, r7, #16
80003f6: fbb1 f9fe udiv r9, r1, lr
80003fa: fa1f f884 uxth.w r8, r4
80003fe: fb0e 1119 mls r1, lr, r9, r1
8000402: ea43 4101 orr.w r1, r3, r1, lsl #16
8000406: fb09 fa08 mul.w sl, r9, r8
800040a: 458a cmp sl, r1
800040c: fa02 f206 lsl.w r2, r2, r6
8000410: fa00 f306 lsl.w r3, r0, r6
8000414: d908 bls.n 8000428 <__udivmoddi4+0x220>
8000416: 1861 adds r1, r4, r1
8000418: f109 30ff add.w r0, r9, #4294967295 ; 0xffffffff
800041c: d248 bcs.n 80004b0 <__udivmoddi4+0x2a8>
800041e: 458a cmp sl, r1
8000420: d946 bls.n 80004b0 <__udivmoddi4+0x2a8>
8000422: f1a9 0902 sub.w r9, r9, #2
8000426: 4421 add r1, r4
8000428: eba1 010a sub.w r1, r1, sl
800042c: b2bf uxth r7, r7
800042e: fbb1 f0fe udiv r0, r1, lr
8000432: fb0e 1110 mls r1, lr, r0, r1
8000436: ea47 4701 orr.w r7, r7, r1, lsl #16
800043a: fb00 f808 mul.w r8, r0, r8
800043e: 45b8 cmp r8, r7
8000440: d907 bls.n 8000452 <__udivmoddi4+0x24a>
8000442: 19e7 adds r7, r4, r7
8000444: f100 31ff add.w r1, r0, #4294967295 ; 0xffffffff
8000448: d22e bcs.n 80004a8 <__udivmoddi4+0x2a0>
800044a: 45b8 cmp r8, r7
800044c: d92c bls.n 80004a8 <__udivmoddi4+0x2a0>
800044e: 3802 subs r0, #2
8000450: 4427 add r7, r4
8000452: ea40 4009 orr.w r0, r0, r9, lsl #16
8000456: eba7 0708 sub.w r7, r7, r8
800045a: fba0 8902 umull r8, r9, r0, r2
800045e: 454f cmp r7, r9
8000460: 46c6 mov lr, r8
8000462: 4649 mov r1, r9
8000464: d31a bcc.n 800049c <__udivmoddi4+0x294>
8000466: d017 beq.n 8000498 <__udivmoddi4+0x290>
8000468: b15d cbz r5, 8000482 <__udivmoddi4+0x27a>
800046a: ebb3 020e subs.w r2, r3, lr
800046e: eb67 0701 sbc.w r7, r7, r1
8000472: fa07 fc0c lsl.w ip, r7, ip
8000476: 40f2 lsrs r2, r6
8000478: ea4c 0202 orr.w r2, ip, r2
800047c: 40f7 lsrs r7, r6
800047e: e9c5 2700 strd r2, r7, [r5]
8000482: 2600 movs r6, #0
8000484: 4631 mov r1, r6
8000486: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800048a: 462e mov r6, r5
800048c: 4628 mov r0, r5
800048e: e70b b.n 80002a8 <__udivmoddi4+0xa0>
8000490: 4606 mov r6, r0
8000492: e6e9 b.n 8000268 <__udivmoddi4+0x60>
8000494: 4618 mov r0, r3
8000496: e6fd b.n 8000294 <__udivmoddi4+0x8c>
8000498: 4543 cmp r3, r8
800049a: d2e5 bcs.n 8000468 <__udivmoddi4+0x260>
800049c: ebb8 0e02 subs.w lr, r8, r2
80004a0: eb69 0104 sbc.w r1, r9, r4
80004a4: 3801 subs r0, #1
80004a6: e7df b.n 8000468 <__udivmoddi4+0x260>
80004a8: 4608 mov r0, r1
80004aa: e7d2 b.n 8000452 <__udivmoddi4+0x24a>
80004ac: 4660 mov r0, ip
80004ae: e78d b.n 80003cc <__udivmoddi4+0x1c4>
80004b0: 4681 mov r9, r0
80004b2: e7b9 b.n 8000428 <__udivmoddi4+0x220>
80004b4: 4666 mov r6, ip
80004b6: e775 b.n 80003a4 <__udivmoddi4+0x19c>
80004b8: 4630 mov r0, r6
80004ba: e74a b.n 8000352 <__udivmoddi4+0x14a>
80004bc: f1ac 0c02 sub.w ip, ip, #2
80004c0: 4439 add r1, r7
80004c2: e713 b.n 80002ec <__udivmoddi4+0xe4>
80004c4: 3802 subs r0, #2
80004c6: 443c add r4, r7
80004c8: e724 b.n 8000314 <__udivmoddi4+0x10c>
80004ca: bf00 nop
080004cc <__aeabi_idiv0>:
80004cc: 4770 bx lr
80004ce: bf00 nop
080004d0 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80004d0: b580 push {r7, lr}
80004d2: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004d4: f000 fce2 bl 8000e9c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004d8: f000 f812 bl 8000500 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004dc: f000 f99c bl 8000818 <MX_GPIO_Init>
MX_SDIO_SD_Init();
80004e0: f000 f8f8 bl 80006d4 <MX_SDIO_SD_Init>
MX_USART1_UART_Init();
80004e4: f000 f94c bl 8000780 <MX_USART1_UART_Init>
MX_FATFS_Init();
80004e8: f005 f84e bl 8005588 <MX_FATFS_Init>
MX_I2S4_Init();
80004ec: f000 f8c6 bl 800067c <MX_I2S4_Init>
MX_SPI1_Init();
80004f0: f000 f910 bl 8000714 <MX_SPI1_Init>
MX_USB_OTG_FS_HCD_Init();
80004f4: f000 f96e bl 80007d4 <MX_USB_OTG_FS_HCD_Init>
MX_ADC1_Init();
80004f8: f000 f86e bl 80005d8 <MX_ADC1_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
80004fc: e7fe b.n 80004fc <main+0x2c>
...
08000500 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000500: b580 push {r7, lr}
8000502: b094 sub sp, #80 ; 0x50
8000504: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000506: f107 0320 add.w r3, r7, #32
800050a: 2230 movs r2, #48 ; 0x30
800050c: 2100 movs r1, #0
800050e: 4618 mov r0, r3
8000510: f005 faec bl 8005aec <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000514: f107 030c add.w r3, r7, #12
8000518: 2200 movs r2, #0
800051a: 601a str r2, [r3, #0]
800051c: 605a str r2, [r3, #4]
800051e: 609a str r2, [r3, #8]
8000520: 60da str r2, [r3, #12]
8000522: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000524: 2300 movs r3, #0
8000526: 60bb str r3, [r7, #8]
8000528: 4b29 ldr r3, [pc, #164] ; (80005d0 <SystemClock_Config+0xd0>)
800052a: 6c1b ldr r3, [r3, #64] ; 0x40
800052c: 4a28 ldr r2, [pc, #160] ; (80005d0 <SystemClock_Config+0xd0>)
800052e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000532: 6413 str r3, [r2, #64] ; 0x40
8000534: 4b26 ldr r3, [pc, #152] ; (80005d0 <SystemClock_Config+0xd0>)
8000536: 6c1b ldr r3, [r3, #64] ; 0x40
8000538: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800053c: 60bb str r3, [r7, #8]
800053e: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000540: 2300 movs r3, #0
8000542: 607b str r3, [r7, #4]
8000544: 4b23 ldr r3, [pc, #140] ; (80005d4 <SystemClock_Config+0xd4>)
8000546: 681b ldr r3, [r3, #0]
8000548: 4a22 ldr r2, [pc, #136] ; (80005d4 <SystemClock_Config+0xd4>)
800054a: f443 4340 orr.w r3, r3, #49152 ; 0xc000
800054e: 6013 str r3, [r2, #0]
8000550: 4b20 ldr r3, [pc, #128] ; (80005d4 <SystemClock_Config+0xd4>)
8000552: 681b ldr r3, [r3, #0]
8000554: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000558: 607b str r3, [r7, #4]
800055a: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
800055c: 2303 movs r3, #3
800055e: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000560: f44f 3380 mov.w r3, #65536 ; 0x10000
8000564: 627b str r3, [r7, #36] ; 0x24
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000566: 2301 movs r3, #1
8000568: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800056a: 2310 movs r3, #16
800056c: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
800056e: 2302 movs r3, #2
8000570: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000572: f44f 0380 mov.w r3, #4194304 ; 0x400000
8000576: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 12;
8000578: 230c movs r3, #12
800057a: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 72;
800057c: 2348 movs r3, #72 ; 0x48
800057e: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000580: 2302 movs r3, #2
8000582: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 3;
8000584: 2303 movs r3, #3
8000586: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000588: f107 0320 add.w r3, r7, #32
800058c: 4618 mov r0, r3
800058e: f001 ffbd bl 800250c <HAL_RCC_OscConfig>
8000592: 4603 mov r3, r0
8000594: 2b00 cmp r3, #0
8000596: d001 beq.n 800059c <SystemClock_Config+0x9c>
{
Error_Handler();
8000598: f000 f99e bl 80008d8 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800059c: 230f movs r3, #15
800059e: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
80005a0: 2300 movs r3, #0
80005a2: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80005a4: 2300 movs r3, #0
80005a6: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80005a8: 2300 movs r3, #0
80005aa: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80005ac: 2300 movs r3, #0
80005ae: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
80005b0: f107 030c add.w r3, r7, #12
80005b4: 2100 movs r1, #0
80005b6: 4618 mov r0, r3
80005b8: f002 fa20 bl 80029fc <HAL_RCC_ClockConfig>
80005bc: 4603 mov r3, r0
80005be: 2b00 cmp r3, #0
80005c0: d001 beq.n 80005c6 <SystemClock_Config+0xc6>
{
Error_Handler();
80005c2: f000 f989 bl 80008d8 <Error_Handler>
}
}
80005c6: bf00 nop
80005c8: 3750 adds r7, #80 ; 0x50
80005ca: 46bd mov sp, r7
80005cc: bd80 pop {r7, pc}
80005ce: bf00 nop
80005d0: 40023800 .word 0x40023800
80005d4: 40007000 .word 0x40007000
080005d8 <MX_ADC1_Init>:
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
80005d8: b580 push {r7, lr}
80005da: b084 sub sp, #16
80005dc: af00 add r7, sp, #0
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80005de: 463b mov r3, r7
80005e0: 2200 movs r2, #0
80005e2: 601a str r2, [r3, #0]
80005e4: 605a str r2, [r3, #4]
80005e6: 609a str r2, [r3, #8]
80005e8: 60da str r2, [r3, #12]
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc1.Instance = ADC1;
80005ea: 4b21 ldr r3, [pc, #132] ; (8000670 <MX_ADC1_Init+0x98>)
80005ec: 4a21 ldr r2, [pc, #132] ; (8000674 <MX_ADC1_Init+0x9c>)
80005ee: 601a str r2, [r3, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
80005f0: 4b1f ldr r3, [pc, #124] ; (8000670 <MX_ADC1_Init+0x98>)
80005f2: 2200 movs r2, #0
80005f4: 605a str r2, [r3, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
80005f6: 4b1e ldr r3, [pc, #120] ; (8000670 <MX_ADC1_Init+0x98>)
80005f8: 2200 movs r2, #0
80005fa: 609a str r2, [r3, #8]
hadc1.Init.ScanConvMode = DISABLE;
80005fc: 4b1c ldr r3, [pc, #112] ; (8000670 <MX_ADC1_Init+0x98>)
80005fe: 2200 movs r2, #0
8000600: 611a str r2, [r3, #16]
hadc1.Init.ContinuousConvMode = DISABLE;
8000602: 4b1b ldr r3, [pc, #108] ; (8000670 <MX_ADC1_Init+0x98>)
8000604: 2200 movs r2, #0
8000606: 761a strb r2, [r3, #24]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000608: 4b19 ldr r3, [pc, #100] ; (8000670 <MX_ADC1_Init+0x98>)
800060a: 2200 movs r2, #0
800060c: f883 2020 strb.w r2, [r3, #32]
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000610: 4b17 ldr r3, [pc, #92] ; (8000670 <MX_ADC1_Init+0x98>)
8000612: 2200 movs r2, #0
8000614: 62da str r2, [r3, #44] ; 0x2c
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000616: 4b16 ldr r3, [pc, #88] ; (8000670 <MX_ADC1_Init+0x98>)
8000618: 4a17 ldr r2, [pc, #92] ; (8000678 <MX_ADC1_Init+0xa0>)
800061a: 629a str r2, [r3, #40] ; 0x28
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800061c: 4b14 ldr r3, [pc, #80] ; (8000670 <MX_ADC1_Init+0x98>)
800061e: 2200 movs r2, #0
8000620: 60da str r2, [r3, #12]
hadc1.Init.NbrOfConversion = 1;
8000622: 4b13 ldr r3, [pc, #76] ; (8000670 <MX_ADC1_Init+0x98>)
8000624: 2201 movs r2, #1
8000626: 61da str r2, [r3, #28]
hadc1.Init.DMAContinuousRequests = DISABLE;
8000628: 4b11 ldr r3, [pc, #68] ; (8000670 <MX_ADC1_Init+0x98>)
800062a: 2200 movs r2, #0
800062c: f883 2030 strb.w r2, [r3, #48] ; 0x30
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000630: 4b0f ldr r3, [pc, #60] ; (8000670 <MX_ADC1_Init+0x98>)
8000632: 2201 movs r2, #1
8000634: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000636: 480e ldr r0, [pc, #56] ; (8000670 <MX_ADC1_Init+0x98>)
8000638: f000 fcc6 bl 8000fc8 <HAL_ADC_Init>
800063c: 4603 mov r3, r0
800063e: 2b00 cmp r3, #0
8000640: d001 beq.n 8000646 <MX_ADC1_Init+0x6e>
{
Error_Handler();
8000642: f000 f949 bl 80008d8 <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_2;
8000646: 2302 movs r3, #2
8000648: 603b str r3, [r7, #0]
sConfig.Rank = 1;
800064a: 2301 movs r3, #1
800064c: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
800064e: 2300 movs r3, #0
8000650: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000652: 463b mov r3, r7
8000654: 4619 mov r1, r3
8000656: 4806 ldr r0, [pc, #24] ; (8000670 <MX_ADC1_Init+0x98>)
8000658: f000 fcfa bl 8001050 <HAL_ADC_ConfigChannel>
800065c: 4603 mov r3, r0
800065e: 2b00 cmp r3, #0
8000660: d001 beq.n 8000666 <MX_ADC1_Init+0x8e>
{
Error_Handler();
8000662: f000 f939 bl 80008d8 <Error_Handler>
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
8000666: bf00 nop
8000668: 3710 adds r7, #16
800066a: 46bd mov sp, r7
800066c: bd80 pop {r7, pc}
800066e: bf00 nop
8000670: 2000003c .word 0x2000003c
8000674: 40012000 .word 0x40012000
8000678: 0f000001 .word 0x0f000001
0800067c <MX_I2S4_Init>:
* @brief I2S4 Initialization Function
* @param None
* @retval None
*/
static void MX_I2S4_Init(void)
{
800067c: b580 push {r7, lr}
800067e: af00 add r7, sp, #0
/* USER CODE END I2S4_Init 0 */
/* USER CODE BEGIN I2S4_Init 1 */
/* USER CODE END I2S4_Init 1 */
hi2s4.Instance = SPI4;
8000680: 4b12 ldr r3, [pc, #72] ; (80006cc <MX_I2S4_Init+0x50>)
8000682: 4a13 ldr r2, [pc, #76] ; (80006d0 <MX_I2S4_Init+0x54>)
8000684: 601a str r2, [r3, #0]
hi2s4.Init.Mode = I2S_MODE_SLAVE_TX;
8000686: 4b11 ldr r3, [pc, #68] ; (80006cc <MX_I2S4_Init+0x50>)
8000688: 2200 movs r2, #0
800068a: 605a str r2, [r3, #4]
hi2s4.Init.Standard = I2S_STANDARD_PHILIPS;
800068c: 4b0f ldr r3, [pc, #60] ; (80006cc <MX_I2S4_Init+0x50>)
800068e: 2200 movs r2, #0
8000690: 609a str r2, [r3, #8]
hi2s4.Init.DataFormat = I2S_DATAFORMAT_16B;
8000692: 4b0e ldr r3, [pc, #56] ; (80006cc <MX_I2S4_Init+0x50>)
8000694: 2200 movs r2, #0
8000696: 60da str r2, [r3, #12]
hi2s4.Init.MCLKOutput = I2S_MCLKOUTPUT_DISABLE;
8000698: 4b0c ldr r3, [pc, #48] ; (80006cc <MX_I2S4_Init+0x50>)
800069a: 2200 movs r2, #0
800069c: 611a str r2, [r3, #16]
hi2s4.Init.AudioFreq = I2S_AUDIOFREQ_32K;
800069e: 4b0b ldr r3, [pc, #44] ; (80006cc <MX_I2S4_Init+0x50>)
80006a0: f44f 42fa mov.w r2, #32000 ; 0x7d00
80006a4: 615a str r2, [r3, #20]
hi2s4.Init.CPOL = I2S_CPOL_LOW;
80006a6: 4b09 ldr r3, [pc, #36] ; (80006cc <MX_I2S4_Init+0x50>)
80006a8: 2200 movs r2, #0
80006aa: 619a str r2, [r3, #24]
hi2s4.Init.ClockSource = I2S_CLOCK_PLL;
80006ac: 4b07 ldr r3, [pc, #28] ; (80006cc <MX_I2S4_Init+0x50>)
80006ae: 2200 movs r2, #0
80006b0: 61da str r2, [r3, #28]
hi2s4.Init.FullDuplexMode = I2S_FULLDUPLEXMODE_DISABLE;
80006b2: 4b06 ldr r3, [pc, #24] ; (80006cc <MX_I2S4_Init+0x50>)
80006b4: 2200 movs r2, #0
80006b6: 621a str r2, [r3, #32]
if (HAL_I2S_Init(&hi2s4) != HAL_OK)
80006b8: 4804 ldr r0, [pc, #16] ; (80006cc <MX_I2S4_Init+0x50>)
80006ba: f001 fa87 bl 8001bcc <HAL_I2S_Init>
80006be: 4603 mov r3, r0
80006c0: 2b00 cmp r3, #0
80006c2: d001 beq.n 80006c8 <MX_I2S4_Init+0x4c>
{
Error_Handler();
80006c4: f000 f908 bl 80008d8 <Error_Handler>
}
/* USER CODE BEGIN I2S4_Init 2 */
/* USER CODE END I2S4_Init 2 */
}
80006c8: bf00 nop
80006ca: bd80 pop {r7, pc}
80006cc: 20000084 .word 0x20000084
80006d0: 40013400 .word 0x40013400
080006d4 <MX_SDIO_SD_Init>:
* @brief SDIO Initialization Function
* @param None
* @retval None
*/
static void MX_SDIO_SD_Init(void)
{
80006d4: b480 push {r7}
80006d6: af00 add r7, sp, #0
/* USER CODE END SDIO_Init 0 */
/* USER CODE BEGIN SDIO_Init 1 */
/* USER CODE END SDIO_Init 1 */
hsd.Instance = SDIO;
80006d8: 4b0c ldr r3, [pc, #48] ; (800070c <MX_SDIO_SD_Init+0x38>)
80006da: 4a0d ldr r2, [pc, #52] ; (8000710 <MX_SDIO_SD_Init+0x3c>)
80006dc: 601a str r2, [r3, #0]
hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
80006de: 4b0b ldr r3, [pc, #44] ; (800070c <MX_SDIO_SD_Init+0x38>)
80006e0: 2200 movs r2, #0
80006e2: 605a str r2, [r3, #4]
hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
80006e4: 4b09 ldr r3, [pc, #36] ; (800070c <MX_SDIO_SD_Init+0x38>)
80006e6: 2200 movs r2, #0
80006e8: 609a str r2, [r3, #8]
hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
80006ea: 4b08 ldr r3, [pc, #32] ; (800070c <MX_SDIO_SD_Init+0x38>)
80006ec: 2200 movs r2, #0
80006ee: 60da str r2, [r3, #12]
hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
80006f0: 4b06 ldr r3, [pc, #24] ; (800070c <MX_SDIO_SD_Init+0x38>)
80006f2: 2200 movs r2, #0
80006f4: 611a str r2, [r3, #16]
hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
80006f6: 4b05 ldr r3, [pc, #20] ; (800070c <MX_SDIO_SD_Init+0x38>)
80006f8: 2200 movs r2, #0
80006fa: 615a str r2, [r3, #20]
hsd.Init.ClockDiv = 0;
80006fc: 4b03 ldr r3, [pc, #12] ; (800070c <MX_SDIO_SD_Init+0x38>)
80006fe: 2200 movs r2, #0
8000700: 619a str r2, [r3, #24]
/* USER CODE BEGIN SDIO_Init 2 */
/* USER CODE END SDIO_Init 2 */
}
8000702: bf00 nop
8000704: 46bd mov sp, r7
8000706: f85d 7b04 ldr.w r7, [sp], #4
800070a: 4770 bx lr
800070c: 20000110 .word 0x20000110
8000710: 40012c00 .word 0x40012c00
08000714 <MX_SPI1_Init>:
* @brief SPI1 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI1_Init(void)
{
8000714: b580 push {r7, lr}
8000716: af00 add r7, sp, #0
/* USER CODE BEGIN SPI1_Init 1 */
/* USER CODE END SPI1_Init 1 */
/* SPI1 parameter configuration*/
hspi1.Instance = SPI1;
8000718: 4b17 ldr r3, [pc, #92] ; (8000778 <MX_SPI1_Init+0x64>)
800071a: 4a18 ldr r2, [pc, #96] ; (800077c <MX_SPI1_Init+0x68>)
800071c: 601a str r2, [r3, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
800071e: 4b16 ldr r3, [pc, #88] ; (8000778 <MX_SPI1_Init+0x64>)
8000720: f44f 7282 mov.w r2, #260 ; 0x104
8000724: 605a str r2, [r3, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
8000726: 4b14 ldr r3, [pc, #80] ; (8000778 <MX_SPI1_Init+0x64>)
8000728: 2200 movs r2, #0
800072a: 609a str r2, [r3, #8]
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
800072c: 4b12 ldr r3, [pc, #72] ; (8000778 <MX_SPI1_Init+0x64>)
800072e: 2200 movs r2, #0
8000730: 60da str r2, [r3, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
8000732: 4b11 ldr r3, [pc, #68] ; (8000778 <MX_SPI1_Init+0x64>)
8000734: 2200 movs r2, #0
8000736: 611a str r2, [r3, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
8000738: 4b0f ldr r3, [pc, #60] ; (8000778 <MX_SPI1_Init+0x64>)
800073a: 2200 movs r2, #0
800073c: 615a str r2, [r3, #20]
hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
800073e: 4b0e ldr r3, [pc, #56] ; (8000778 <MX_SPI1_Init+0x64>)
8000740: f44f 2280 mov.w r2, #262144 ; 0x40000
8000744: 619a str r2, [r3, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8000746: 4b0c ldr r3, [pc, #48] ; (8000778 <MX_SPI1_Init+0x64>)
8000748: 2200 movs r2, #0
800074a: 61da str r2, [r3, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
800074c: 4b0a ldr r3, [pc, #40] ; (8000778 <MX_SPI1_Init+0x64>)
800074e: 2200 movs r2, #0
8000750: 621a str r2, [r3, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000752: 4b09 ldr r3, [pc, #36] ; (8000778 <MX_SPI1_Init+0x64>)
8000754: 2200 movs r2, #0
8000756: 625a str r2, [r3, #36] ; 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8000758: 4b07 ldr r3, [pc, #28] ; (8000778 <MX_SPI1_Init+0x64>)
800075a: 2200 movs r2, #0
800075c: 629a str r2, [r3, #40] ; 0x28
hspi1.Init.CRCPolynomial = 10;
800075e: 4b06 ldr r3, [pc, #24] ; (8000778 <MX_SPI1_Init+0x64>)
8000760: 220a movs r2, #10
8000762: 62da str r2, [r3, #44] ; 0x2c
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000764: 4804 ldr r0, [pc, #16] ; (8000778 <MX_SPI1_Init+0x64>)
8000766: f003 fcfe bl 8004166 <HAL_SPI_Init>
800076a: 4603 mov r3, r0
800076c: 2b00 cmp r3, #0
800076e: d001 beq.n 8000774 <MX_SPI1_Init+0x60>
{
Error_Handler();
8000770: f000 f8b2 bl 80008d8 <Error_Handler>
}
/* USER CODE BEGIN SPI1_Init 2 */
/* USER CODE END SPI1_Init 2 */
}
8000774: bf00 nop
8000776: bd80 pop {r7, pc}
8000778: 20000194 .word 0x20000194
800077c: 40013000 .word 0x40013000
08000780 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8000780: b580 push {r7, lr}
8000782: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8000784: 4b11 ldr r3, [pc, #68] ; (80007cc <MX_USART1_UART_Init+0x4c>)
8000786: 4a12 ldr r2, [pc, #72] ; (80007d0 <MX_USART1_UART_Init+0x50>)
8000788: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
800078a: 4b10 ldr r3, [pc, #64] ; (80007cc <MX_USART1_UART_Init+0x4c>)
800078c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000790: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8000792: 4b0e ldr r3, [pc, #56] ; (80007cc <MX_USART1_UART_Init+0x4c>)
8000794: 2200 movs r2, #0
8000796: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8000798: 4b0c ldr r3, [pc, #48] ; (80007cc <MX_USART1_UART_Init+0x4c>)
800079a: 2200 movs r2, #0
800079c: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
800079e: 4b0b ldr r3, [pc, #44] ; (80007cc <MX_USART1_UART_Init+0x4c>)
80007a0: 2200 movs r2, #0
80007a2: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
80007a4: 4b09 ldr r3, [pc, #36] ; (80007cc <MX_USART1_UART_Init+0x4c>)
80007a6: 220c movs r2, #12
80007a8: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80007aa: 4b08 ldr r3, [pc, #32] ; (80007cc <MX_USART1_UART_Init+0x4c>)
80007ac: 2200 movs r2, #0
80007ae: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
80007b0: 4b06 ldr r3, [pc, #24] ; (80007cc <MX_USART1_UART_Init+0x4c>)
80007b2: 2200 movs r2, #0
80007b4: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
80007b6: 4805 ldr r0, [pc, #20] ; (80007cc <MX_USART1_UART_Init+0x4c>)
80007b8: f003 fd5e bl 8004278 <HAL_UART_Init>
80007bc: 4603 mov r3, r0
80007be: 2b00 cmp r3, #0
80007c0: d001 beq.n 80007c6 <MX_USART1_UART_Init+0x46>
{
Error_Handler();
80007c2: f000 f889 bl 80008d8 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80007c6: bf00 nop
80007c8: bd80 pop {r7, pc}
80007ca: bf00 nop
80007cc: 200000cc .word 0x200000cc
80007d0: 40011000 .word 0x40011000
080007d4 <MX_USB_OTG_FS_HCD_Init>:
* @brief USB_OTG_FS Initialization Function
* @param None
* @retval None
*/
static void MX_USB_OTG_FS_HCD_Init(void)
{
80007d4: b580 push {r7, lr}
80007d6: af00 add r7, sp, #0
/* USER CODE END USB_OTG_FS_Init 0 */
/* USER CODE BEGIN USB_OTG_FS_Init 1 */
/* USER CODE END USB_OTG_FS_Init 1 */
hhcd_USB_OTG_FS.Instance = USB_OTG_FS;
80007d8: 4b0e ldr r3, [pc, #56] ; (8000814 <MX_USB_OTG_FS_HCD_Init+0x40>)
80007da: f04f 42a0 mov.w r2, #1342177280 ; 0x50000000
80007de: 601a str r2, [r3, #0]
hhcd_USB_OTG_FS.Init.Host_channels = 8;
80007e0: 4b0c ldr r3, [pc, #48] ; (8000814 <MX_USB_OTG_FS_HCD_Init+0x40>)
80007e2: 2208 movs r2, #8
80007e4: 609a str r2, [r3, #8]
hhcd_USB_OTG_FS.Init.speed = HCD_SPEED_FULL;
80007e6: 4b0b ldr r3, [pc, #44] ; (8000814 <MX_USB_OTG_FS_HCD_Init+0x40>)
80007e8: 2201 movs r2, #1
80007ea: 60da str r2, [r3, #12]
hhcd_USB_OTG_FS.Init.dma_enable = DISABLE;
80007ec: 4b09 ldr r3, [pc, #36] ; (8000814 <MX_USB_OTG_FS_HCD_Init+0x40>)
80007ee: 2200 movs r2, #0
80007f0: 611a str r2, [r3, #16]
hhcd_USB_OTG_FS.Init.phy_itface = HCD_PHY_EMBEDDED;
80007f2: 4b08 ldr r3, [pc, #32] ; (8000814 <MX_USB_OTG_FS_HCD_Init+0x40>)
80007f4: 2202 movs r2, #2
80007f6: 619a str r2, [r3, #24]
hhcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
80007f8: 4b06 ldr r3, [pc, #24] ; (8000814 <MX_USB_OTG_FS_HCD_Init+0x40>)
80007fa: 2200 movs r2, #0
80007fc: 61da str r2, [r3, #28]
if (HAL_HCD_Init(&hhcd_USB_OTG_FS) != HAL_OK)
80007fe: 4805 ldr r0, [pc, #20] ; (8000814 <MX_USB_OTG_FS_HCD_Init+0x40>)
8000800: f001 f981 bl 8001b06 <HAL_HCD_Init>
8000804: 4603 mov r3, r0
8000806: 2b00 cmp r3, #0
8000808: d001 beq.n 800080e <MX_USB_OTG_FS_HCD_Init+0x3a>
{
Error_Handler();
800080a: f000 f865 bl 80008d8 <Error_Handler>
}
/* USER CODE BEGIN USB_OTG_FS_Init 2 */
/* USER CODE END USB_OTG_FS_Init 2 */
}
800080e: bf00 nop
8000810: bd80 pop {r7, pc}
8000812: bf00 nop
8000814: 200001ec .word 0x200001ec
08000818 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000818: b580 push {r7, lr}
800081a: b088 sub sp, #32
800081c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800081e: f107 030c add.w r3, r7, #12
8000822: 2200 movs r2, #0
8000824: 601a str r2, [r3, #0]
8000826: 605a str r2, [r3, #4]
8000828: 609a str r2, [r3, #8]
800082a: 60da str r2, [r3, #12]
800082c: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOH_CLK_ENABLE();
800082e: 2300 movs r3, #0
8000830: 60bb str r3, [r7, #8]
8000832: 4b27 ldr r3, [pc, #156] ; (80008d0 <MX_GPIO_Init+0xb8>)
8000834: 6b1b ldr r3, [r3, #48] ; 0x30
8000836: 4a26 ldr r2, [pc, #152] ; (80008d0 <MX_GPIO_Init+0xb8>)
8000838: f043 0380 orr.w r3, r3, #128 ; 0x80
800083c: 6313 str r3, [r2, #48] ; 0x30
800083e: 4b24 ldr r3, [pc, #144] ; (80008d0 <MX_GPIO_Init+0xb8>)
8000840: 6b1b ldr r3, [r3, #48] ; 0x30
8000842: f003 0380 and.w r3, r3, #128 ; 0x80
8000846: 60bb str r3, [r7, #8]
8000848: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
800084a: 2300 movs r3, #0
800084c: 607b str r3, [r7, #4]
800084e: 4b20 ldr r3, [pc, #128] ; (80008d0 <MX_GPIO_Init+0xb8>)
8000850: 6b1b ldr r3, [r3, #48] ; 0x30
8000852: 4a1f ldr r2, [pc, #124] ; (80008d0 <MX_GPIO_Init+0xb8>)
8000854: f043 0301 orr.w r3, r3, #1
8000858: 6313 str r3, [r2, #48] ; 0x30
800085a: 4b1d ldr r3, [pc, #116] ; (80008d0 <MX_GPIO_Init+0xb8>)
800085c: 6b1b ldr r3, [r3, #48] ; 0x30
800085e: f003 0301 and.w r3, r3, #1
8000862: 607b str r3, [r7, #4]
8000864: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000866: 2300 movs r3, #0
8000868: 603b str r3, [r7, #0]
800086a: 4b19 ldr r3, [pc, #100] ; (80008d0 <MX_GPIO_Init+0xb8>)
800086c: 6b1b ldr r3, [r3, #48] ; 0x30
800086e: 4a18 ldr r2, [pc, #96] ; (80008d0 <MX_GPIO_Init+0xb8>)
8000870: f043 0302 orr.w r3, r3, #2
8000874: 6313 str r3, [r2, #48] ; 0x30
8000876: 4b16 ldr r3, [pc, #88] ; (80008d0 <MX_GPIO_Init+0xb8>)
8000878: 6b1b ldr r3, [r3, #48] ; 0x30
800087a: f003 0302 and.w r3, r3, #2
800087e: 603b str r3, [r7, #0]
8000880: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, PW_HOLD_Pin|MEAS_EN_Pin, GPIO_PIN_RESET);
8000882: 2200 movs r2, #0
8000884: f244 0108 movw r1, #16392 ; 0x4008
8000888: 4812 ldr r0, [pc, #72] ; (80008d4 <MX_GPIO_Init+0xbc>)
800088a: f001 f923 bl 8001ad4 <HAL_GPIO_WritePin>
/*Configure GPIO pins : BTN_PWR_Pin SD_DET_Pin */
GPIO_InitStruct.Pin = BTN_PWR_Pin|SD_DET_Pin;
800088e: f240 2301 movw r3, #513 ; 0x201
8000892: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000894: 2300 movs r3, #0
8000896: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000898: 2300 movs r3, #0
800089a: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800089c: f107 030c add.w r3, r7, #12
80008a0: 4619 mov r1, r3
80008a2: 480c ldr r0, [pc, #48] ; (80008d4 <MX_GPIO_Init+0xbc>)
80008a4: f000 ff7a bl 800179c <HAL_GPIO_Init>
/*Configure GPIO pins : PW_HOLD_Pin MEAS_EN_Pin */
GPIO_InitStruct.Pin = PW_HOLD_Pin|MEAS_EN_Pin;
80008a8: f244 0308 movw r3, #16392 ; 0x4008
80008ac: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80008ae: 2301 movs r3, #1
80008b0: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80008b2: 2300 movs r3, #0
80008b4: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80008b6: 2300 movs r3, #0
80008b8: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80008ba: f107 030c add.w r3, r7, #12
80008be: 4619 mov r1, r3
80008c0: 4804 ldr r0, [pc, #16] ; (80008d4 <MX_GPIO_Init+0xbc>)
80008c2: f000 ff6b bl 800179c <HAL_GPIO_Init>
}
80008c6: bf00 nop
80008c8: 3720 adds r7, #32
80008ca: 46bd mov sp, r7
80008cc: bd80 pop {r7, pc}
80008ce: bf00 nop
80008d0: 40023800 .word 0x40023800
80008d4: 40020400 .word 0x40020400
080008d8 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80008d8: b480 push {r7}
80008da: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80008dc: b672 cpsid i
}
80008de: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80008e0: e7fe b.n 80008e0 <Error_Handler+0x8>
...
080008e4 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80008e4: b480 push {r7}
80008e6: b083 sub sp, #12
80008e8: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80008ea: 2300 movs r3, #0
80008ec: 607b str r3, [r7, #4]
80008ee: 4b10 ldr r3, [pc, #64] ; (8000930 <HAL_MspInit+0x4c>)
80008f0: 6c5b ldr r3, [r3, #68] ; 0x44
80008f2: 4a0f ldr r2, [pc, #60] ; (8000930 <HAL_MspInit+0x4c>)
80008f4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80008f8: 6453 str r3, [r2, #68] ; 0x44
80008fa: 4b0d ldr r3, [pc, #52] ; (8000930 <HAL_MspInit+0x4c>)
80008fc: 6c5b ldr r3, [r3, #68] ; 0x44
80008fe: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000902: 607b str r3, [r7, #4]
8000904: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000906: 2300 movs r3, #0
8000908: 603b str r3, [r7, #0]
800090a: 4b09 ldr r3, [pc, #36] ; (8000930 <HAL_MspInit+0x4c>)
800090c: 6c1b ldr r3, [r3, #64] ; 0x40
800090e: 4a08 ldr r2, [pc, #32] ; (8000930 <HAL_MspInit+0x4c>)
8000910: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000914: 6413 str r3, [r2, #64] ; 0x40
8000916: 4b06 ldr r3, [pc, #24] ; (8000930 <HAL_MspInit+0x4c>)
8000918: 6c1b ldr r3, [r3, #64] ; 0x40
800091a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800091e: 603b str r3, [r7, #0]
8000920: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000922: bf00 nop
8000924: 370c adds r7, #12
8000926: 46bd mov sp, r7
8000928: f85d 7b04 ldr.w r7, [sp], #4
800092c: 4770 bx lr
800092e: bf00 nop
8000930: 40023800 .word 0x40023800
08000934 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8000934: b580 push {r7, lr}
8000936: b08a sub sp, #40 ; 0x28
8000938: af00 add r7, sp, #0
800093a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800093c: f107 0314 add.w r3, r7, #20
8000940: 2200 movs r2, #0
8000942: 601a str r2, [r3, #0]
8000944: 605a str r2, [r3, #4]
8000946: 609a str r2, [r3, #8]
8000948: 60da str r2, [r3, #12]
800094a: 611a str r2, [r3, #16]
if(hadc->Instance==ADC1)
800094c: 687b ldr r3, [r7, #4]
800094e: 681b ldr r3, [r3, #0]
8000950: 4a17 ldr r2, [pc, #92] ; (80009b0 <HAL_ADC_MspInit+0x7c>)
8000952: 4293 cmp r3, r2
8000954: d127 bne.n 80009a6 <HAL_ADC_MspInit+0x72>
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC1_CLK_ENABLE();
8000956: 2300 movs r3, #0
8000958: 613b str r3, [r7, #16]
800095a: 4b16 ldr r3, [pc, #88] ; (80009b4 <HAL_ADC_MspInit+0x80>)
800095c: 6c5b ldr r3, [r3, #68] ; 0x44
800095e: 4a15 ldr r2, [pc, #84] ; (80009b4 <HAL_ADC_MspInit+0x80>)
8000960: f443 7380 orr.w r3, r3, #256 ; 0x100
8000964: 6453 str r3, [r2, #68] ; 0x44
8000966: 4b13 ldr r3, [pc, #76] ; (80009b4 <HAL_ADC_MspInit+0x80>)
8000968: 6c5b ldr r3, [r3, #68] ; 0x44
800096a: f403 7380 and.w r3, r3, #256 ; 0x100
800096e: 613b str r3, [r7, #16]
8000970: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000972: 2300 movs r3, #0
8000974: 60fb str r3, [r7, #12]
8000976: 4b0f ldr r3, [pc, #60] ; (80009b4 <HAL_ADC_MspInit+0x80>)
8000978: 6b1b ldr r3, [r3, #48] ; 0x30
800097a: 4a0e ldr r2, [pc, #56] ; (80009b4 <HAL_ADC_MspInit+0x80>)
800097c: f043 0301 orr.w r3, r3, #1
8000980: 6313 str r3, [r2, #48] ; 0x30
8000982: 4b0c ldr r3, [pc, #48] ; (80009b4 <HAL_ADC_MspInit+0x80>)
8000984: 6b1b ldr r3, [r3, #48] ; 0x30
8000986: f003 0301 and.w r3, r3, #1
800098a: 60fb str r3, [r7, #12]
800098c: 68fb ldr r3, [r7, #12]
/**ADC1 GPIO Configuration
PA2 ------> ADC1_IN2
PA3 ------> ADC1_IN3
*/
GPIO_InitStruct.Pin = MEAS_VBATT_Pin|GPIO_PIN_3;
800098e: 230c movs r3, #12
8000990: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000992: 2303 movs r3, #3
8000994: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000996: 2300 movs r3, #0
8000998: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800099a: f107 0314 add.w r3, r7, #20
800099e: 4619 mov r1, r3
80009a0: 4805 ldr r0, [pc, #20] ; (80009b8 <HAL_ADC_MspInit+0x84>)
80009a2: f000 fefb bl 800179c <HAL_GPIO_Init>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
}
80009a6: bf00 nop
80009a8: 3728 adds r7, #40 ; 0x28
80009aa: 46bd mov sp, r7
80009ac: bd80 pop {r7, pc}
80009ae: bf00 nop
80009b0: 40012000 .word 0x40012000
80009b4: 40023800 .word 0x40023800
80009b8: 40020000 .word 0x40020000
080009bc <HAL_I2S_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2s: I2S handle pointer
* @retval None
*/
void HAL_I2S_MspInit(I2S_HandleTypeDef* hi2s)
{
80009bc: b580 push {r7, lr}
80009be: b090 sub sp, #64 ; 0x40
80009c0: af00 add r7, sp, #0
80009c2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80009c4: f107 032c add.w r3, r7, #44 ; 0x2c
80009c8: 2200 movs r2, #0
80009ca: 601a str r2, [r3, #0]
80009cc: 605a str r2, [r3, #4]
80009ce: 609a str r2, [r3, #8]
80009d0: 60da str r2, [r3, #12]
80009d2: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
80009d4: f107 0314 add.w r3, r7, #20
80009d8: 2200 movs r2, #0
80009da: 601a str r2, [r3, #0]
80009dc: 605a str r2, [r3, #4]
80009de: 609a str r2, [r3, #8]
80009e0: 60da str r2, [r3, #12]
80009e2: 611a str r2, [r3, #16]
80009e4: 615a str r2, [r3, #20]
if(hi2s->Instance==SPI4)
80009e6: 687b ldr r3, [r7, #4]
80009e8: 681b ldr r3, [r3, #0]
80009ea: 4a32 ldr r2, [pc, #200] ; (8000ab4 <HAL_I2S_MspInit+0xf8>)
80009ec: 4293 cmp r3, r2
80009ee: d15c bne.n 8000aaa <HAL_I2S_MspInit+0xee>
/* USER CODE BEGIN SPI4_MspInit 0 */
/* USER CODE END SPI4_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2S;
80009f0: 2301 movs r3, #1
80009f2: 617b str r3, [r7, #20]
PeriphClkInitStruct.PLLI2S.PLLI2SN = 192;
80009f4: 23c0 movs r3, #192 ; 0xc0
80009f6: 61fb str r3, [r7, #28]
PeriphClkInitStruct.PLLI2S.PLLI2SM = 16;
80009f8: 2310 movs r3, #16
80009fa: 61bb str r3, [r7, #24]
PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;
80009fc: 2302 movs r3, #2
80009fe: 623b str r3, [r7, #32]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000a00: f107 0314 add.w r3, r7, #20
8000a04: 4618 mov r0, r3
8000a06: f002 f9c9 bl 8002d9c <HAL_RCCEx_PeriphCLKConfig>
8000a0a: 4603 mov r3, r0
8000a0c: 2b00 cmp r3, #0
8000a0e: d001 beq.n 8000a14 <HAL_I2S_MspInit+0x58>
{
Error_Handler();
8000a10: f7ff ff62 bl 80008d8 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_SPI4_CLK_ENABLE();
8000a14: 2300 movs r3, #0
8000a16: 613b str r3, [r7, #16]
8000a18: 4b27 ldr r3, [pc, #156] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a1a: 6c5b ldr r3, [r3, #68] ; 0x44
8000a1c: 4a26 ldr r2, [pc, #152] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a1e: f443 5300 orr.w r3, r3, #8192 ; 0x2000
8000a22: 6453 str r3, [r2, #68] ; 0x44
8000a24: 4b24 ldr r3, [pc, #144] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a26: 6c5b ldr r3, [r3, #68] ; 0x44
8000a28: f403 5300 and.w r3, r3, #8192 ; 0x2000
8000a2c: 613b str r3, [r7, #16]
8000a2e: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000a30: 2300 movs r3, #0
8000a32: 60fb str r3, [r7, #12]
8000a34: 4b20 ldr r3, [pc, #128] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a36: 6b1b ldr r3, [r3, #48] ; 0x30
8000a38: 4a1f ldr r2, [pc, #124] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a3a: f043 0301 orr.w r3, r3, #1
8000a3e: 6313 str r3, [r2, #48] ; 0x30
8000a40: 4b1d ldr r3, [pc, #116] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a42: 6b1b ldr r3, [r3, #48] ; 0x30
8000a44: f003 0301 and.w r3, r3, #1
8000a48: 60fb str r3, [r7, #12]
8000a4a: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000a4c: 2300 movs r3, #0
8000a4e: 60bb str r3, [r7, #8]
8000a50: 4b19 ldr r3, [pc, #100] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a52: 6b1b ldr r3, [r3, #48] ; 0x30
8000a54: 4a18 ldr r2, [pc, #96] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a56: f043 0302 orr.w r3, r3, #2
8000a5a: 6313 str r3, [r2, #48] ; 0x30
8000a5c: 4b16 ldr r3, [pc, #88] ; (8000ab8 <HAL_I2S_MspInit+0xfc>)
8000a5e: 6b1b ldr r3, [r3, #48] ; 0x30
8000a60: f003 0302 and.w r3, r3, #2
8000a64: 60bb str r3, [r7, #8]
8000a66: 68bb ldr r3, [r7, #8]
/**I2S4 GPIO Configuration
PA1 ------> I2S4_SD
PB12 ------> I2S4_WS
PB13 ------> I2S4_CK
*/
GPIO_InitStruct.Pin = DAC_DATA_Pin;
8000a68: 2302 movs r3, #2
8000a6a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a6c: 2302 movs r3, #2
8000a6e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a70: 2300 movs r3, #0
8000a72: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a74: 2300 movs r3, #0
8000a76: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;
8000a78: 2305 movs r3, #5
8000a7a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(DAC_DATA_GPIO_Port, &GPIO_InitStruct);
8000a7c: f107 032c add.w r3, r7, #44 ; 0x2c
8000a80: 4619 mov r1, r3
8000a82: 480e ldr r0, [pc, #56] ; (8000abc <HAL_I2S_MspInit+0x100>)
8000a84: f000 fe8a bl 800179c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = DAC_LRCLK_Pin|DAC_CLK_Pin;
8000a88: f44f 5340 mov.w r3, #12288 ; 0x3000
8000a8c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a8e: 2302 movs r3, #2
8000a90: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a92: 2300 movs r3, #0
8000a94: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000a96: 2300 movs r3, #0
8000a98: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF6_SPI4;
8000a9a: 2306 movs r3, #6
8000a9c: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000a9e: f107 032c add.w r3, r7, #44 ; 0x2c
8000aa2: 4619 mov r1, r3
8000aa4: 4806 ldr r0, [pc, #24] ; (8000ac0 <HAL_I2S_MspInit+0x104>)
8000aa6: f000 fe79 bl 800179c <HAL_GPIO_Init>
/* USER CODE BEGIN SPI4_MspInit 1 */
/* USER CODE END SPI4_MspInit 1 */
}
}
8000aaa: bf00 nop
8000aac: 3740 adds r7, #64 ; 0x40
8000aae: 46bd mov sp, r7
8000ab0: bd80 pop {r7, pc}
8000ab2: bf00 nop
8000ab4: 40013400 .word 0x40013400
8000ab8: 40023800 .word 0x40023800
8000abc: 40020000 .word 0x40020000
8000ac0: 40020400 .word 0x40020400
08000ac4 <HAL_SD_MspInit>:
* This function configures the hardware resources used in this example
* @param hsd: SD handle pointer
* @retval None
*/
void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
{
8000ac4: b580 push {r7, lr}
8000ac6: b08a sub sp, #40 ; 0x28
8000ac8: af00 add r7, sp, #0
8000aca: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000acc: f107 0314 add.w r3, r7, #20
8000ad0: 2200 movs r2, #0
8000ad2: 601a str r2, [r3, #0]
8000ad4: 605a str r2, [r3, #4]
8000ad6: 609a str r2, [r3, #8]
8000ad8: 60da str r2, [r3, #12]
8000ada: 611a str r2, [r3, #16]
if(hsd->Instance==SDIO)
8000adc: 687b ldr r3, [r7, #4]
8000ade: 681b ldr r3, [r3, #0]
8000ae0: 4a29 ldr r2, [pc, #164] ; (8000b88 <HAL_SD_MspInit+0xc4>)
8000ae2: 4293 cmp r3, r2
8000ae4: d14b bne.n 8000b7e <HAL_SD_MspInit+0xba>
{
/* USER CODE BEGIN SDIO_MspInit 0 */
/* USER CODE END SDIO_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SDIO_CLK_ENABLE();
8000ae6: 2300 movs r3, #0
8000ae8: 613b str r3, [r7, #16]
8000aea: 4b28 ldr r3, [pc, #160] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000aec: 6c5b ldr r3, [r3, #68] ; 0x44
8000aee: 4a27 ldr r2, [pc, #156] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000af0: f443 6300 orr.w r3, r3, #2048 ; 0x800
8000af4: 6453 str r3, [r2, #68] ; 0x44
8000af6: 4b25 ldr r3, [pc, #148] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000af8: 6c5b ldr r3, [r3, #68] ; 0x44
8000afa: f403 6300 and.w r3, r3, #2048 ; 0x800
8000afe: 613b str r3, [r7, #16]
8000b00: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000b02: 2300 movs r3, #0
8000b04: 60fb str r3, [r7, #12]
8000b06: 4b21 ldr r3, [pc, #132] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000b08: 6b1b ldr r3, [r3, #48] ; 0x30
8000b0a: 4a20 ldr r2, [pc, #128] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000b0c: f043 0301 orr.w r3, r3, #1
8000b10: 6313 str r3, [r2, #48] ; 0x30
8000b12: 4b1e ldr r3, [pc, #120] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000b14: 6b1b ldr r3, [r3, #48] ; 0x30
8000b16: f003 0301 and.w r3, r3, #1
8000b1a: 60fb str r3, [r7, #12]
8000b1c: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000b1e: 2300 movs r3, #0
8000b20: 60bb str r3, [r7, #8]
8000b22: 4b1a ldr r3, [pc, #104] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000b24: 6b1b ldr r3, [r3, #48] ; 0x30
8000b26: 4a19 ldr r2, [pc, #100] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000b28: f043 0302 orr.w r3, r3, #2
8000b2c: 6313 str r3, [r2, #48] ; 0x30
8000b2e: 4b17 ldr r3, [pc, #92] ; (8000b8c <HAL_SD_MspInit+0xc8>)
8000b30: 6b1b ldr r3, [r3, #48] ; 0x30
8000b32: f003 0302 and.w r3, r3, #2
8000b36: 60bb str r3, [r7, #8]
8000b38: 68bb ldr r3, [r7, #8]
PA8 ------> SDIO_D1
PA9 ------> SDIO_D2
PB5 ------> SDIO_D3
PB7 ------> SDIO_D0
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_9;
8000b3a: f44f 7350 mov.w r3, #832 ; 0x340
8000b3e: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b40: 2302 movs r3, #2
8000b42: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b44: 2300 movs r3, #0
8000b46: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b48: 2303 movs r3, #3
8000b4a: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;
8000b4c: 230c movs r3, #12
8000b4e: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000b50: f107 0314 add.w r3, r7, #20
8000b54: 4619 mov r1, r3
8000b56: 480e ldr r0, [pc, #56] ; (8000b90 <HAL_SD_MspInit+0xcc>)
8000b58: f000 fe20 bl 800179c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_5|GPIO_PIN_7;
8000b5c: f248 03a0 movw r3, #32928 ; 0x80a0
8000b60: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000b62: 2302 movs r3, #2
8000b64: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000b66: 2300 movs r3, #0
8000b68: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000b6a: 2303 movs r3, #3
8000b6c: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;
8000b6e: 230c movs r3, #12
8000b70: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000b72: f107 0314 add.w r3, r7, #20
8000b76: 4619 mov r1, r3
8000b78: 4806 ldr r0, [pc, #24] ; (8000b94 <HAL_SD_MspInit+0xd0>)
8000b7a: f000 fe0f bl 800179c <HAL_GPIO_Init>
/* USER CODE BEGIN SDIO_MspInit 1 */
/* USER CODE END SDIO_MspInit 1 */
}
}
8000b7e: bf00 nop
8000b80: 3728 adds r7, #40 ; 0x28
8000b82: 46bd mov sp, r7
8000b84: bd80 pop {r7, pc}
8000b86: bf00 nop
8000b88: 40012c00 .word 0x40012c00
8000b8c: 40023800 .word 0x40023800
8000b90: 40020000 .word 0x40020000
8000b94: 40020400 .word 0x40020400
08000b98 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8000b98: b580 push {r7, lr}
8000b9a: b08a sub sp, #40 ; 0x28
8000b9c: af00 add r7, sp, #0
8000b9e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000ba0: f107 0314 add.w r3, r7, #20
8000ba4: 2200 movs r2, #0
8000ba6: 601a str r2, [r3, #0]
8000ba8: 605a str r2, [r3, #4]
8000baa: 609a str r2, [r3, #8]
8000bac: 60da str r2, [r3, #12]
8000bae: 611a str r2, [r3, #16]
if(hspi->Instance==SPI1)
8000bb0: 687b ldr r3, [r7, #4]
8000bb2: 681b ldr r3, [r3, #0]
8000bb4: 4a28 ldr r2, [pc, #160] ; (8000c58 <HAL_SPI_MspInit+0xc0>)
8000bb6: 4293 cmp r3, r2
8000bb8: d149 bne.n 8000c4e <HAL_SPI_MspInit+0xb6>
{
/* USER CODE BEGIN SPI1_MspInit 0 */
/* USER CODE END SPI1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI1_CLK_ENABLE();
8000bba: 2300 movs r3, #0
8000bbc: 613b str r3, [r7, #16]
8000bbe: 4b27 ldr r3, [pc, #156] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000bc0: 6c5b ldr r3, [r3, #68] ; 0x44
8000bc2: 4a26 ldr r2, [pc, #152] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000bc4: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8000bc8: 6453 str r3, [r2, #68] ; 0x44
8000bca: 4b24 ldr r3, [pc, #144] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000bcc: 6c5b ldr r3, [r3, #68] ; 0x44
8000bce: f403 5380 and.w r3, r3, #4096 ; 0x1000
8000bd2: 613b str r3, [r7, #16]
8000bd4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000bd6: 2300 movs r3, #0
8000bd8: 60fb str r3, [r7, #12]
8000bda: 4b20 ldr r3, [pc, #128] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000bdc: 6b1b ldr r3, [r3, #48] ; 0x30
8000bde: 4a1f ldr r2, [pc, #124] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000be0: f043 0301 orr.w r3, r3, #1
8000be4: 6313 str r3, [r2, #48] ; 0x30
8000be6: 4b1d ldr r3, [pc, #116] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000be8: 6b1b ldr r3, [r3, #48] ; 0x30
8000bea: f003 0301 and.w r3, r3, #1
8000bee: 60fb str r3, [r7, #12]
8000bf0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000bf2: 2300 movs r3, #0
8000bf4: 60bb str r3, [r7, #8]
8000bf6: 4b19 ldr r3, [pc, #100] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000bf8: 6b1b ldr r3, [r3, #48] ; 0x30
8000bfa: 4a18 ldr r2, [pc, #96] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000bfc: f043 0302 orr.w r3, r3, #2
8000c00: 6313 str r3, [r2, #48] ; 0x30
8000c02: 4b16 ldr r3, [pc, #88] ; (8000c5c <HAL_SPI_MspInit+0xc4>)
8000c04: 6b1b ldr r3, [r3, #48] ; 0x30
8000c06: f003 0302 and.w r3, r3, #2
8000c0a: 60bb str r3, [r7, #8]
8000c0c: 68bb ldr r3, [r7, #8]
PA4 ------> SPI1_NSS
PA5 ------> SPI1_SCK
PA7 ------> SPI1_MOSI
PB4 ------> SPI1_MISO
*/
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_7;
8000c0e: 23b0 movs r3, #176 ; 0xb0
8000c10: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c12: 2302 movs r3, #2
8000c14: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c16: 2300 movs r3, #0
8000c18: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c1a: 2303 movs r3, #3
8000c1c: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000c1e: 2305 movs r3, #5
8000c20: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c22: f107 0314 add.w r3, r7, #20
8000c26: 4619 mov r1, r3
8000c28: 480d ldr r0, [pc, #52] ; (8000c60 <HAL_SPI_MspInit+0xc8>)
8000c2a: f000 fdb7 bl 800179c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_4;
8000c2e: 2310 movs r3, #16
8000c30: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000c32: 2302 movs r3, #2
8000c34: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c36: 2300 movs r3, #0
8000c38: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000c3a: 2303 movs r3, #3
8000c3c: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8000c3e: 2305 movs r3, #5
8000c40: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000c42: f107 0314 add.w r3, r7, #20
8000c46: 4619 mov r1, r3
8000c48: 4806 ldr r0, [pc, #24] ; (8000c64 <HAL_SPI_MspInit+0xcc>)
8000c4a: f000 fda7 bl 800179c <HAL_GPIO_Init>
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
}
8000c4e: bf00 nop
8000c50: 3728 adds r7, #40 ; 0x28
8000c52: 46bd mov sp, r7
8000c54: bd80 pop {r7, pc}
8000c56: bf00 nop
8000c58: 40013000 .word 0x40013000
8000c5c: 40023800 .word 0x40023800
8000c60: 40020000 .word 0x40020000
8000c64: 40020400 .word 0x40020400
08000c68 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000c68: b580 push {r7, lr}
8000c6a: b08a sub sp, #40 ; 0x28
8000c6c: af00 add r7, sp, #0
8000c6e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000c70: f107 0314 add.w r3, r7, #20
8000c74: 2200 movs r2, #0
8000c76: 601a str r2, [r3, #0]
8000c78: 605a str r2, [r3, #4]
8000c7a: 609a str r2, [r3, #8]
8000c7c: 60da str r2, [r3, #12]
8000c7e: 611a str r2, [r3, #16]
if(huart->Instance==USART1)
8000c80: 687b ldr r3, [r7, #4]
8000c82: 681b ldr r3, [r3, #0]
8000c84: 4a28 ldr r2, [pc, #160] ; (8000d28 <HAL_UART_MspInit+0xc0>)
8000c86: 4293 cmp r3, r2
8000c88: d14a bne.n 8000d20 <HAL_UART_MspInit+0xb8>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8000c8a: 2300 movs r3, #0
8000c8c: 613b str r3, [r7, #16]
8000c8e: 4b27 ldr r3, [pc, #156] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000c90: 6c5b ldr r3, [r3, #68] ; 0x44
8000c92: 4a26 ldr r2, [pc, #152] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000c94: f043 0310 orr.w r3, r3, #16
8000c98: 6453 str r3, [r2, #68] ; 0x44
8000c9a: 4b24 ldr r3, [pc, #144] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000c9c: 6c5b ldr r3, [r3, #68] ; 0x44
8000c9e: f003 0310 and.w r3, r3, #16
8000ca2: 613b str r3, [r7, #16]
8000ca4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000ca6: 2300 movs r3, #0
8000ca8: 60fb str r3, [r7, #12]
8000caa: 4b20 ldr r3, [pc, #128] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000cac: 6b1b ldr r3, [r3, #48] ; 0x30
8000cae: 4a1f ldr r2, [pc, #124] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000cb0: f043 0301 orr.w r3, r3, #1
8000cb4: 6313 str r3, [r2, #48] ; 0x30
8000cb6: 4b1d ldr r3, [pc, #116] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000cb8: 6b1b ldr r3, [r3, #48] ; 0x30
8000cba: f003 0301 and.w r3, r3, #1
8000cbe: 60fb str r3, [r7, #12]
8000cc0: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000cc2: 2300 movs r3, #0
8000cc4: 60bb str r3, [r7, #8]
8000cc6: 4b19 ldr r3, [pc, #100] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000cc8: 6b1b ldr r3, [r3, #48] ; 0x30
8000cca: 4a18 ldr r2, [pc, #96] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000ccc: f043 0302 orr.w r3, r3, #2
8000cd0: 6313 str r3, [r2, #48] ; 0x30
8000cd2: 4b16 ldr r3, [pc, #88] ; (8000d2c <HAL_UART_MspInit+0xc4>)
8000cd4: 6b1b ldr r3, [r3, #48] ; 0x30
8000cd6: f003 0302 and.w r3, r3, #2
8000cda: 60bb str r3, [r7, #8]
8000cdc: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PA10 ------> USART1_RX
PB6 ------> USART1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_10;
8000cde: f44f 6380 mov.w r3, #1024 ; 0x400
8000ce2: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000ce4: 2302 movs r3, #2
8000ce6: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000ce8: 2300 movs r3, #0
8000cea: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000cec: 2303 movs r3, #3
8000cee: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8000cf0: 2307 movs r3, #7
8000cf2: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000cf4: f107 0314 add.w r3, r7, #20
8000cf8: 4619 mov r1, r3
8000cfa: 480d ldr r0, [pc, #52] ; (8000d30 <HAL_UART_MspInit+0xc8>)
8000cfc: f000 fd4e bl 800179c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_6;
8000d00: 2340 movs r3, #64 ; 0x40
8000d02: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d04: 2302 movs r3, #2
8000d06: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d08: 2300 movs r3, #0
8000d0a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d0c: 2303 movs r3, #3
8000d0e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8000d10: 2307 movs r3, #7
8000d12: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000d14: f107 0314 add.w r3, r7, #20
8000d18: 4619 mov r1, r3
8000d1a: 4806 ldr r0, [pc, #24] ; (8000d34 <HAL_UART_MspInit+0xcc>)
8000d1c: f000 fd3e bl 800179c <HAL_GPIO_Init>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8000d20: bf00 nop
8000d22: 3728 adds r7, #40 ; 0x28
8000d24: 46bd mov sp, r7
8000d26: bd80 pop {r7, pc}
8000d28: 40011000 .word 0x40011000
8000d2c: 40023800 .word 0x40023800
8000d30: 40020000 .word 0x40020000
8000d34: 40020400 .word 0x40020400
08000d38 <HAL_HCD_MspInit>:
* This function configures the hardware resources used in this example
* @param hhcd: HCD handle pointer
* @retval None
*/
void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd)
{
8000d38: b580 push {r7, lr}
8000d3a: b08a sub sp, #40 ; 0x28
8000d3c: af00 add r7, sp, #0
8000d3e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000d40: f107 0314 add.w r3, r7, #20
8000d44: 2200 movs r2, #0
8000d46: 601a str r2, [r3, #0]
8000d48: 605a str r2, [r3, #4]
8000d4a: 609a str r2, [r3, #8]
8000d4c: 60da str r2, [r3, #12]
8000d4e: 611a str r2, [r3, #16]
if(hhcd->Instance==USB_OTG_FS)
8000d50: 687b ldr r3, [r7, #4]
8000d52: 681b ldr r3, [r3, #0]
8000d54: f1b3 4fa0 cmp.w r3, #1342177280 ; 0x50000000
8000d58: d132 bne.n 8000dc0 <HAL_HCD_MspInit+0x88>
{
/* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
/* USER CODE END USB_OTG_FS_MspInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000d5a: 2300 movs r3, #0
8000d5c: 613b str r3, [r7, #16]
8000d5e: 4b1a ldr r3, [pc, #104] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000d60: 6b1b ldr r3, [r3, #48] ; 0x30
8000d62: 4a19 ldr r2, [pc, #100] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000d64: f043 0301 orr.w r3, r3, #1
8000d68: 6313 str r3, [r2, #48] ; 0x30
8000d6a: 4b17 ldr r3, [pc, #92] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000d6c: 6b1b ldr r3, [r3, #48] ; 0x30
8000d6e: f003 0301 and.w r3, r3, #1
8000d72: 613b str r3, [r7, #16]
8000d74: 693b ldr r3, [r7, #16]
/**USB_OTG_FS GPIO Configuration
PA11 ------> USB_OTG_FS_DM
PA12 ------> USB_OTG_FS_DP
*/
GPIO_InitStruct.Pin = USB_DM_Pin|USB_DP_Pin;
8000d76: f44f 53c0 mov.w r3, #6144 ; 0x1800
8000d7a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000d7c: 2302 movs r3, #2
8000d7e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d80: 2300 movs r3, #0
8000d82: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d84: 2303 movs r3, #3
8000d86: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
8000d88: 230a movs r3, #10
8000d8a: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000d8c: f107 0314 add.w r3, r7, #20
8000d90: 4619 mov r1, r3
8000d92: 480e ldr r0, [pc, #56] ; (8000dcc <HAL_HCD_MspInit+0x94>)
8000d94: f000 fd02 bl 800179c <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
8000d98: 4b0b ldr r3, [pc, #44] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000d9a: 6b5b ldr r3, [r3, #52] ; 0x34
8000d9c: 4a0a ldr r2, [pc, #40] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000d9e: f043 0380 orr.w r3, r3, #128 ; 0x80
8000da2: 6353 str r3, [r2, #52] ; 0x34
8000da4: 2300 movs r3, #0
8000da6: 60fb str r3, [r7, #12]
8000da8: 4b07 ldr r3, [pc, #28] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000daa: 6c5b ldr r3, [r3, #68] ; 0x44
8000dac: 4a06 ldr r2, [pc, #24] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000dae: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000db2: 6453 str r3, [r2, #68] ; 0x44
8000db4: 4b04 ldr r3, [pc, #16] ; (8000dc8 <HAL_HCD_MspInit+0x90>)
8000db6: 6c5b ldr r3, [r3, #68] ; 0x44
8000db8: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000dbc: 60fb str r3, [r7, #12]
8000dbe: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
/* USER CODE END USB_OTG_FS_MspInit 1 */
}
}
8000dc0: bf00 nop
8000dc2: 3728 adds r7, #40 ; 0x28
8000dc4: 46bd mov sp, r7
8000dc6: bd80 pop {r7, pc}
8000dc8: 40023800 .word 0x40023800
8000dcc: 40020000 .word 0x40020000
08000dd0 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000dd0: b480 push {r7}
8000dd2: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000dd4: e7fe b.n 8000dd4 <NMI_Handler+0x4>
08000dd6 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000dd6: b480 push {r7}
8000dd8: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000dda: e7fe b.n 8000dda <HardFault_Handler+0x4>
08000ddc <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000ddc: b480 push {r7}
8000dde: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000de0: e7fe b.n 8000de0 <MemManage_Handler+0x4>
08000de2 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000de2: b480 push {r7}
8000de4: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000de6: e7fe b.n 8000de6 <BusFault_Handler+0x4>
08000de8 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000de8: b480 push {r7}
8000dea: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000dec: e7fe b.n 8000dec <UsageFault_Handler+0x4>
08000dee <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000dee: b480 push {r7}
8000df0: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8000df2: bf00 nop
8000df4: 46bd mov sp, r7
8000df6: f85d 7b04 ldr.w r7, [sp], #4
8000dfa: 4770 bx lr
08000dfc <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000dfc: b480 push {r7}
8000dfe: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000e00: bf00 nop
8000e02: 46bd mov sp, r7
8000e04: f85d 7b04 ldr.w r7, [sp], #4
8000e08: 4770 bx lr
08000e0a <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000e0a: b480 push {r7}
8000e0c: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000e0e: bf00 nop
8000e10: 46bd mov sp, r7
8000e12: f85d 7b04 ldr.w r7, [sp], #4
8000e16: 4770 bx lr
08000e18 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000e18: b580 push {r7, lr}
8000e1a: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000e1c: f000 f890 bl 8000f40 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000e20: bf00 nop
8000e22: bd80 pop {r7, pc}
08000e24 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000e24: b480 push {r7}
8000e26: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000e28: 4b06 ldr r3, [pc, #24] ; (8000e44 <SystemInit+0x20>)
8000e2a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000e2e: 4a05 ldr r2, [pc, #20] ; (8000e44 <SystemInit+0x20>)
8000e30: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000e34: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000e38: bf00 nop
8000e3a: 46bd mov sp, r7
8000e3c: f85d 7b04 ldr.w r7, [sp], #4
8000e40: 4770 bx lr
8000e42: bf00 nop
8000e44: e000ed00 .word 0xe000ed00
08000e48 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000e48: f8df d034 ldr.w sp, [pc, #52] ; 8000e80 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000e4c: 480d ldr r0, [pc, #52] ; (8000e84 <LoopFillZerobss+0x16>)
ldr r1, =_edata
8000e4e: 490e ldr r1, [pc, #56] ; (8000e88 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
8000e50: 4a0e ldr r2, [pc, #56] ; (8000e8c <LoopFillZerobss+0x1e>)
movs r3, #0
8000e52: 2300 movs r3, #0
b LoopCopyDataInit
8000e54: e002 b.n 8000e5c <LoopCopyDataInit>
08000e56 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000e56: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000e58: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000e5a: 3304 adds r3, #4
08000e5c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000e5c: 18c4 adds r4, r0, r3
cmp r4, r1
8000e5e: 428c cmp r4, r1
bcc CopyDataInit
8000e60: d3f9 bcc.n 8000e56 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000e62: 4a0b ldr r2, [pc, #44] ; (8000e90 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8000e64: 4c0b ldr r4, [pc, #44] ; (8000e94 <LoopFillZerobss+0x26>)
movs r3, #0
8000e66: 2300 movs r3, #0
b LoopFillZerobss
8000e68: e001 b.n 8000e6e <LoopFillZerobss>
08000e6a <FillZerobss>:
FillZerobss:
str r3, [r2]
8000e6a: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000e6c: 3204 adds r2, #4
08000e6e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000e6e: 42a2 cmp r2, r4
bcc FillZerobss
8000e70: d3fb bcc.n 8000e6a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8000e72: f7ff ffd7 bl 8000e24 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000e76: f004 fe15 bl 8005aa4 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000e7a: f7ff fb29 bl 80004d0 <main>
bx lr
8000e7e: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000e80: 20020000 .word 0x20020000
ldr r0, =_sdata
8000e84: 20000000 .word 0x20000000
ldr r1, =_edata
8000e88: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000e8c: 08005b50 .word 0x08005b50
ldr r2, =_sbss
8000e90: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000e94: 2000095c .word 0x2000095c
08000e98 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000e98: e7fe b.n 8000e98 <ADC_IRQHandler>
...
08000e9c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000e9c: b580 push {r7, lr}
8000e9e: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000ea0: 4b0e ldr r3, [pc, #56] ; (8000edc <HAL_Init+0x40>)
8000ea2: 681b ldr r3, [r3, #0]
8000ea4: 4a0d ldr r2, [pc, #52] ; (8000edc <HAL_Init+0x40>)
8000ea6: f443 7300 orr.w r3, r3, #512 ; 0x200
8000eaa: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000eac: 4b0b ldr r3, [pc, #44] ; (8000edc <HAL_Init+0x40>)
8000eae: 681b ldr r3, [r3, #0]
8000eb0: 4a0a ldr r2, [pc, #40] ; (8000edc <HAL_Init+0x40>)
8000eb2: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000eb6: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000eb8: 4b08 ldr r3, [pc, #32] ; (8000edc <HAL_Init+0x40>)
8000eba: 681b ldr r3, [r3, #0]
8000ebc: 4a07 ldr r2, [pc, #28] ; (8000edc <HAL_Init+0x40>)
8000ebe: f443 7380 orr.w r3, r3, #256 ; 0x100
8000ec2: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000ec4: 2003 movs r0, #3
8000ec6: f000 fba3 bl 8001610 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000eca: 200f movs r0, #15
8000ecc: f000 f808 bl 8000ee0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000ed0: f7ff fd08 bl 80008e4 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000ed4: 2300 movs r3, #0
}
8000ed6: 4618 mov r0, r3
8000ed8: bd80 pop {r7, pc}
8000eda: bf00 nop
8000edc: 40023c00 .word 0x40023c00
08000ee0 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000ee0: b580 push {r7, lr}
8000ee2: b082 sub sp, #8
8000ee4: af00 add r7, sp, #0
8000ee6: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000ee8: 4b12 ldr r3, [pc, #72] ; (8000f34 <HAL_InitTick+0x54>)
8000eea: 681a ldr r2, [r3, #0]
8000eec: 4b12 ldr r3, [pc, #72] ; (8000f38 <HAL_InitTick+0x58>)
8000eee: 781b ldrb r3, [r3, #0]
8000ef0: 4619 mov r1, r3
8000ef2: f44f 737a mov.w r3, #1000 ; 0x3e8
8000ef6: fbb3 f3f1 udiv r3, r3, r1
8000efa: fbb2 f3f3 udiv r3, r2, r3
8000efe: 4618 mov r0, r3
8000f00: f000 fbad bl 800165e <HAL_SYSTICK_Config>
8000f04: 4603 mov r3, r0
8000f06: 2b00 cmp r3, #0
8000f08: d001 beq.n 8000f0e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000f0a: 2301 movs r3, #1
8000f0c: e00e b.n 8000f2c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000f0e: 687b ldr r3, [r7, #4]
8000f10: 2b0f cmp r3, #15
8000f12: d80a bhi.n 8000f2a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000f14: 2200 movs r2, #0
8000f16: 6879 ldr r1, [r7, #4]
8000f18: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8000f1c: f000 fb83 bl 8001626 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000f20: 4a06 ldr r2, [pc, #24] ; (8000f3c <HAL_InitTick+0x5c>)
8000f22: 687b ldr r3, [r7, #4]
8000f24: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000f26: 2300 movs r3, #0
8000f28: e000 b.n 8000f2c <HAL_InitTick+0x4c>
return HAL_ERROR;
8000f2a: 2301 movs r3, #1
}
8000f2c: 4618 mov r0, r3
8000f2e: 3708 adds r7, #8
8000f30: 46bd mov sp, r7
8000f32: bd80 pop {r7, pc}
8000f34: 20000000 .word 0x20000000
8000f38: 20000008 .word 0x20000008
8000f3c: 20000004 .word 0x20000004
08000f40 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000f40: b480 push {r7}
8000f42: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000f44: 4b06 ldr r3, [pc, #24] ; (8000f60 <HAL_IncTick+0x20>)
8000f46: 781b ldrb r3, [r3, #0]
8000f48: 461a mov r2, r3
8000f4a: 4b06 ldr r3, [pc, #24] ; (8000f64 <HAL_IncTick+0x24>)
8000f4c: 681b ldr r3, [r3, #0]
8000f4e: 4413 add r3, r2
8000f50: 4a04 ldr r2, [pc, #16] ; (8000f64 <HAL_IncTick+0x24>)
8000f52: 6013 str r3, [r2, #0]
}
8000f54: bf00 nop
8000f56: 46bd mov sp, r7
8000f58: f85d 7b04 ldr.w r7, [sp], #4
8000f5c: 4770 bx lr
8000f5e: bf00 nop
8000f60: 20000008 .word 0x20000008
8000f64: 200004f0 .word 0x200004f0
08000f68 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000f68: b480 push {r7}
8000f6a: af00 add r7, sp, #0
return uwTick;
8000f6c: 4b03 ldr r3, [pc, #12] ; (8000f7c <HAL_GetTick+0x14>)
8000f6e: 681b ldr r3, [r3, #0]
}
8000f70: 4618 mov r0, r3
8000f72: 46bd mov sp, r7
8000f74: f85d 7b04 ldr.w r7, [sp], #4
8000f78: 4770 bx lr
8000f7a: bf00 nop
8000f7c: 200004f0 .word 0x200004f0
08000f80 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000f80: b580 push {r7, lr}
8000f82: b084 sub sp, #16
8000f84: af00 add r7, sp, #0
8000f86: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8000f88: f7ff ffee bl 8000f68 <HAL_GetTick>
8000f8c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000f8e: 687b ldr r3, [r7, #4]
8000f90: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000f92: 68fb ldr r3, [r7, #12]
8000f94: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
8000f98: d005 beq.n 8000fa6 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8000f9a: 4b0a ldr r3, [pc, #40] ; (8000fc4 <HAL_Delay+0x44>)
8000f9c: 781b ldrb r3, [r3, #0]
8000f9e: 461a mov r2, r3
8000fa0: 68fb ldr r3, [r7, #12]
8000fa2: 4413 add r3, r2
8000fa4: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8000fa6: bf00 nop
8000fa8: f7ff ffde bl 8000f68 <HAL_GetTick>
8000fac: 4602 mov r2, r0
8000fae: 68bb ldr r3, [r7, #8]
8000fb0: 1ad3 subs r3, r2, r3
8000fb2: 68fa ldr r2, [r7, #12]
8000fb4: 429a cmp r2, r3
8000fb6: d8f7 bhi.n 8000fa8 <HAL_Delay+0x28>
{
}
}
8000fb8: bf00 nop
8000fba: bf00 nop
8000fbc: 3710 adds r7, #16
8000fbe: 46bd mov sp, r7
8000fc0: bd80 pop {r7, pc}
8000fc2: bf00 nop
8000fc4: 20000008 .word 0x20000008
08000fc8 <HAL_ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
8000fc8: b580 push {r7, lr}
8000fca: b084 sub sp, #16
8000fcc: af00 add r7, sp, #0
8000fce: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000fd0: 2300 movs r3, #0
8000fd2: 73fb strb r3, [r7, #15]
/* Check ADC handle */
if(hadc == NULL)
8000fd4: 687b ldr r3, [r7, #4]
8000fd6: 2b00 cmp r3, #0
8000fd8: d101 bne.n 8000fde <HAL_ADC_Init+0x16>
{
return HAL_ERROR;
8000fda: 2301 movs r3, #1
8000fdc: e033 b.n 8001046 <HAL_ADC_Init+0x7e>
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if(hadc->State == HAL_ADC_STATE_RESET)
8000fde: 687b ldr r3, [r7, #4]
8000fe0: 6c1b ldr r3, [r3, #64] ; 0x40
8000fe2: 2b00 cmp r3, #0
8000fe4: d109 bne.n 8000ffa <HAL_ADC_Init+0x32>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8000fe6: 6878 ldr r0, [r7, #4]
8000fe8: f7ff fca4 bl 8000934 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8000fec: 687b ldr r3, [r7, #4]
8000fee: 2200 movs r2, #0
8000ff0: 645a str r2, [r3, #68] ; 0x44
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8000ff2: 687b ldr r3, [r7, #4]
8000ff4: 2200 movs r2, #0
8000ff6: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8000ffa: 687b ldr r3, [r7, #4]
8000ffc: 6c1b ldr r3, [r3, #64] ; 0x40
8000ffe: f003 0310 and.w r3, r3, #16
8001002: 2b00 cmp r3, #0
8001004: d118 bne.n 8001038 <HAL_ADC_Init+0x70>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001006: 687b ldr r3, [r7, #4]
8001008: 6c1b ldr r3, [r3, #64] ; 0x40
800100a: f423 5388 bic.w r3, r3, #4352 ; 0x1100
800100e: f023 0302 bic.w r3, r3, #2
8001012: f043 0202 orr.w r2, r3, #2
8001016: 687b ldr r3, [r7, #4]
8001018: 641a str r2, [r3, #64] ; 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
800101a: 6878 ldr r0, [r7, #4]
800101c: f000 f94a bl 80012b4 <ADC_Init>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001020: 687b ldr r3, [r7, #4]
8001022: 2200 movs r2, #0
8001024: 645a str r2, [r3, #68] ; 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001026: 687b ldr r3, [r7, #4]
8001028: 6c1b ldr r3, [r3, #64] ; 0x40
800102a: f023 0303 bic.w r3, r3, #3
800102e: f043 0201 orr.w r2, r3, #1
8001032: 687b ldr r3, [r7, #4]
8001034: 641a str r2, [r3, #64] ; 0x40
8001036: e001 b.n 800103c <HAL_ADC_Init+0x74>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
tmp_hal_status = HAL_ERROR;
8001038: 2301 movs r3, #1
800103a: 73fb strb r3, [r7, #15]
}
/* Release Lock */
__HAL_UNLOCK(hadc);
800103c: 687b ldr r3, [r7, #4]
800103e: 2200 movs r2, #0
8001040: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return tmp_hal_status;
8001044: 7bfb ldrb r3, [r7, #15]
}
8001046: 4618 mov r0, r3
8001048: 3710 adds r7, #16
800104a: 46bd mov sp, r7
800104c: bd80 pop {r7, pc}
...
08001050 <HAL_ADC_ConfigChannel>:
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
8001050: b480 push {r7}
8001052: b085 sub sp, #20
8001054: af00 add r7, sp, #0
8001056: 6078 str r0, [r7, #4]
8001058: 6039 str r1, [r7, #0]
__IO uint32_t counter = 0U;
800105a: 2300 movs r3, #0
800105c: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
800105e: 687b ldr r3, [r7, #4]
8001060: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8001064: 2b01 cmp r3, #1
8001066: d101 bne.n 800106c <HAL_ADC_ConfigChannel+0x1c>
8001068: 2302 movs r3, #2
800106a: e113 b.n 8001294 <HAL_ADC_ConfigChannel+0x244>
800106c: 687b ldr r3, [r7, #4]
800106e: 2201 movs r2, #1
8001070: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfig->Channel > ADC_CHANNEL_9)
8001074: 683b ldr r3, [r7, #0]
8001076: 681b ldr r3, [r3, #0]
8001078: 2b09 cmp r3, #9
800107a: d925 bls.n 80010c8 <HAL_ADC_ConfigChannel+0x78>
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
800107c: 687b ldr r3, [r7, #4]
800107e: 681b ldr r3, [r3, #0]
8001080: 68d9 ldr r1, [r3, #12]
8001082: 683b ldr r3, [r7, #0]
8001084: 681b ldr r3, [r3, #0]
8001086: b29b uxth r3, r3
8001088: 461a mov r2, r3
800108a: 4613 mov r3, r2
800108c: 005b lsls r3, r3, #1
800108e: 4413 add r3, r2
8001090: 3b1e subs r3, #30
8001092: 2207 movs r2, #7
8001094: fa02 f303 lsl.w r3, r2, r3
8001098: 43da mvns r2, r3
800109a: 687b ldr r3, [r7, #4]
800109c: 681b ldr r3, [r3, #0]
800109e: 400a ands r2, r1
80010a0: 60da str r2, [r3, #12]
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
80010a2: 687b ldr r3, [r7, #4]
80010a4: 681b ldr r3, [r3, #0]
80010a6: 68d9 ldr r1, [r3, #12]
80010a8: 683b ldr r3, [r7, #0]
80010aa: 689a ldr r2, [r3, #8]
80010ac: 683b ldr r3, [r7, #0]
80010ae: 681b ldr r3, [r3, #0]
80010b0: b29b uxth r3, r3
80010b2: 4618 mov r0, r3
80010b4: 4603 mov r3, r0
80010b6: 005b lsls r3, r3, #1
80010b8: 4403 add r3, r0
80010ba: 3b1e subs r3, #30
80010bc: 409a lsls r2, r3
80010be: 687b ldr r3, [r7, #4]
80010c0: 681b ldr r3, [r3, #0]
80010c2: 430a orrs r2, r1
80010c4: 60da str r2, [r3, #12]
80010c6: e022 b.n 800110e <HAL_ADC_ConfigChannel+0xbe>
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
80010c8: 687b ldr r3, [r7, #4]
80010ca: 681b ldr r3, [r3, #0]
80010cc: 6919 ldr r1, [r3, #16]
80010ce: 683b ldr r3, [r7, #0]
80010d0: 681b ldr r3, [r3, #0]
80010d2: b29b uxth r3, r3
80010d4: 461a mov r2, r3
80010d6: 4613 mov r3, r2
80010d8: 005b lsls r3, r3, #1
80010da: 4413 add r3, r2
80010dc: 2207 movs r2, #7
80010de: fa02 f303 lsl.w r3, r2, r3
80010e2: 43da mvns r2, r3
80010e4: 687b ldr r3, [r7, #4]
80010e6: 681b ldr r3, [r3, #0]
80010e8: 400a ands r2, r1
80010ea: 611a str r2, [r3, #16]
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
80010ec: 687b ldr r3, [r7, #4]
80010ee: 681b ldr r3, [r3, #0]
80010f0: 6919 ldr r1, [r3, #16]
80010f2: 683b ldr r3, [r7, #0]
80010f4: 689a ldr r2, [r3, #8]
80010f6: 683b ldr r3, [r7, #0]
80010f8: 681b ldr r3, [r3, #0]
80010fa: b29b uxth r3, r3
80010fc: 4618 mov r0, r3
80010fe: 4603 mov r3, r0
8001100: 005b lsls r3, r3, #1
8001102: 4403 add r3, r0
8001104: 409a lsls r2, r3
8001106: 687b ldr r3, [r7, #4]
8001108: 681b ldr r3, [r3, #0]
800110a: 430a orrs r2, r1
800110c: 611a str r2, [r3, #16]
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
800110e: 683b ldr r3, [r7, #0]
8001110: 685b ldr r3, [r3, #4]
8001112: 2b06 cmp r3, #6
8001114: d824 bhi.n 8001160 <HAL_ADC_ConfigChannel+0x110>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
8001116: 687b ldr r3, [r7, #4]
8001118: 681b ldr r3, [r3, #0]
800111a: 6b59 ldr r1, [r3, #52] ; 0x34
800111c: 683b ldr r3, [r7, #0]
800111e: 685a ldr r2, [r3, #4]
8001120: 4613 mov r3, r2
8001122: 009b lsls r3, r3, #2
8001124: 4413 add r3, r2
8001126: 3b05 subs r3, #5
8001128: 221f movs r2, #31
800112a: fa02 f303 lsl.w r3, r2, r3
800112e: 43da mvns r2, r3
8001130: 687b ldr r3, [r7, #4]
8001132: 681b ldr r3, [r3, #0]
8001134: 400a ands r2, r1
8001136: 635a str r2, [r3, #52] ; 0x34
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
8001138: 687b ldr r3, [r7, #4]
800113a: 681b ldr r3, [r3, #0]
800113c: 6b59 ldr r1, [r3, #52] ; 0x34
800113e: 683b ldr r3, [r7, #0]
8001140: 681b ldr r3, [r3, #0]
8001142: b29b uxth r3, r3
8001144: 4618 mov r0, r3
8001146: 683b ldr r3, [r7, #0]
8001148: 685a ldr r2, [r3, #4]
800114a: 4613 mov r3, r2
800114c: 009b lsls r3, r3, #2
800114e: 4413 add r3, r2
8001150: 3b05 subs r3, #5
8001152: fa00 f203 lsl.w r2, r0, r3
8001156: 687b ldr r3, [r7, #4]
8001158: 681b ldr r3, [r3, #0]
800115a: 430a orrs r2, r1
800115c: 635a str r2, [r3, #52] ; 0x34
800115e: e04c b.n 80011fa <HAL_ADC_ConfigChannel+0x1aa>
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
8001160: 683b ldr r3, [r7, #0]
8001162: 685b ldr r3, [r3, #4]
8001164: 2b0c cmp r3, #12
8001166: d824 bhi.n 80011b2 <HAL_ADC_ConfigChannel+0x162>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
8001168: 687b ldr r3, [r7, #4]
800116a: 681b ldr r3, [r3, #0]
800116c: 6b19 ldr r1, [r3, #48] ; 0x30
800116e: 683b ldr r3, [r7, #0]
8001170: 685a ldr r2, [r3, #4]
8001172: 4613 mov r3, r2
8001174: 009b lsls r3, r3, #2
8001176: 4413 add r3, r2
8001178: 3b23 subs r3, #35 ; 0x23
800117a: 221f movs r2, #31
800117c: fa02 f303 lsl.w r3, r2, r3
8001180: 43da mvns r2, r3
8001182: 687b ldr r3, [r7, #4]
8001184: 681b ldr r3, [r3, #0]
8001186: 400a ands r2, r1
8001188: 631a str r2, [r3, #48] ; 0x30
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
800118a: 687b ldr r3, [r7, #4]
800118c: 681b ldr r3, [r3, #0]
800118e: 6b19 ldr r1, [r3, #48] ; 0x30
8001190: 683b ldr r3, [r7, #0]
8001192: 681b ldr r3, [r3, #0]
8001194: b29b uxth r3, r3
8001196: 4618 mov r0, r3
8001198: 683b ldr r3, [r7, #0]
800119a: 685a ldr r2, [r3, #4]
800119c: 4613 mov r3, r2
800119e: 009b lsls r3, r3, #2
80011a0: 4413 add r3, r2
80011a2: 3b23 subs r3, #35 ; 0x23
80011a4: fa00 f203 lsl.w r2, r0, r3
80011a8: 687b ldr r3, [r7, #4]
80011aa: 681b ldr r3, [r3, #0]
80011ac: 430a orrs r2, r1
80011ae: 631a str r2, [r3, #48] ; 0x30
80011b0: e023 b.n 80011fa <HAL_ADC_ConfigChannel+0x1aa>
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
80011b2: 687b ldr r3, [r7, #4]
80011b4: 681b ldr r3, [r3, #0]
80011b6: 6ad9 ldr r1, [r3, #44] ; 0x2c
80011b8: 683b ldr r3, [r7, #0]
80011ba: 685a ldr r2, [r3, #4]
80011bc: 4613 mov r3, r2
80011be: 009b lsls r3, r3, #2
80011c0: 4413 add r3, r2
80011c2: 3b41 subs r3, #65 ; 0x41
80011c4: 221f movs r2, #31
80011c6: fa02 f303 lsl.w r3, r2, r3
80011ca: 43da mvns r2, r3
80011cc: 687b ldr r3, [r7, #4]
80011ce: 681b ldr r3, [r3, #0]
80011d0: 400a ands r2, r1
80011d2: 62da str r2, [r3, #44] ; 0x2c
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
80011d4: 687b ldr r3, [r7, #4]
80011d6: 681b ldr r3, [r3, #0]
80011d8: 6ad9 ldr r1, [r3, #44] ; 0x2c
80011da: 683b ldr r3, [r7, #0]
80011dc: 681b ldr r3, [r3, #0]
80011de: b29b uxth r3, r3
80011e0: 4618 mov r0, r3
80011e2: 683b ldr r3, [r7, #0]
80011e4: 685a ldr r2, [r3, #4]
80011e6: 4613 mov r3, r2
80011e8: 009b lsls r3, r3, #2
80011ea: 4413 add r3, r2
80011ec: 3b41 subs r3, #65 ; 0x41
80011ee: fa00 f203 lsl.w r2, r0, r3
80011f2: 687b ldr r3, [r7, #4]
80011f4: 681b ldr r3, [r3, #0]
80011f6: 430a orrs r2, r1
80011f8: 62da str r2, [r3, #44] ; 0x2c
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
80011fa: 4b29 ldr r3, [pc, #164] ; (80012a0 <HAL_ADC_ConfigChannel+0x250>)
80011fc: 60fb str r3, [r7, #12]
/* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
80011fe: 687b ldr r3, [r7, #4]
8001200: 681b ldr r3, [r3, #0]
8001202: 4a28 ldr r2, [pc, #160] ; (80012a4 <HAL_ADC_ConfigChannel+0x254>)
8001204: 4293 cmp r3, r2
8001206: d10f bne.n 8001228 <HAL_ADC_ConfigChannel+0x1d8>
8001208: 683b ldr r3, [r7, #0]
800120a: 681b ldr r3, [r3, #0]
800120c: 2b12 cmp r3, #18
800120e: d10b bne.n 8001228 <HAL_ADC_ConfigChannel+0x1d8>
{
/* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
{
tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
8001210: 68fb ldr r3, [r7, #12]
8001212: 685b ldr r3, [r3, #4]
8001214: f423 0200 bic.w r2, r3, #8388608 ; 0x800000
8001218: 68fb ldr r3, [r7, #12]
800121a: 605a str r2, [r3, #4]
}
/* Enable the VBAT channel*/
tmpADC_Common->CCR |= ADC_CCR_VBATE;
800121c: 68fb ldr r3, [r7, #12]
800121e: 685b ldr r3, [r3, #4]
8001220: f443 0280 orr.w r2, r3, #4194304 ; 0x400000
8001224: 68fb ldr r3, [r7, #12]
8001226: 605a str r2, [r3, #4]
}
/* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
Channel_17 is selected for VREFINT enable TSVREFE */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
8001228: 687b ldr r3, [r7, #4]
800122a: 681b ldr r3, [r3, #0]
800122c: 4a1d ldr r2, [pc, #116] ; (80012a4 <HAL_ADC_ConfigChannel+0x254>)
800122e: 4293 cmp r3, r2
8001230: d12b bne.n 800128a <HAL_ADC_ConfigChannel+0x23a>
8001232: 683b ldr r3, [r7, #0]
8001234: 681b ldr r3, [r3, #0]
8001236: 4a1c ldr r2, [pc, #112] ; (80012a8 <HAL_ADC_ConfigChannel+0x258>)
8001238: 4293 cmp r3, r2
800123a: d003 beq.n 8001244 <HAL_ADC_ConfigChannel+0x1f4>
800123c: 683b ldr r3, [r7, #0]
800123e: 681b ldr r3, [r3, #0]
8001240: 2b11 cmp r3, #17
8001242: d122 bne.n 800128a <HAL_ADC_ConfigChannel+0x23a>
{
/* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
{
tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
8001244: 68fb ldr r3, [r7, #12]
8001246: 685b ldr r3, [r3, #4]
8001248: f423 0280 bic.w r2, r3, #4194304 ; 0x400000
800124c: 68fb ldr r3, [r7, #12]
800124e: 605a str r2, [r3, #4]
}
/* Enable the Temperature sensor and VREFINT channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
8001250: 68fb ldr r3, [r7, #12]
8001252: 685b ldr r3, [r3, #4]
8001254: f443 0200 orr.w r2, r3, #8388608 ; 0x800000
8001258: 68fb ldr r3, [r7, #12]
800125a: 605a str r2, [r3, #4]
if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
800125c: 683b ldr r3, [r7, #0]
800125e: 681b ldr r3, [r3, #0]
8001260: 4a11 ldr r2, [pc, #68] ; (80012a8 <HAL_ADC_ConfigChannel+0x258>)
8001262: 4293 cmp r3, r2
8001264: d111 bne.n 800128a <HAL_ADC_ConfigChannel+0x23a>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
8001266: 4b11 ldr r3, [pc, #68] ; (80012ac <HAL_ADC_ConfigChannel+0x25c>)
8001268: 681b ldr r3, [r3, #0]
800126a: 4a11 ldr r2, [pc, #68] ; (80012b0 <HAL_ADC_ConfigChannel+0x260>)
800126c: fba2 2303 umull r2, r3, r2, r3
8001270: 0c9a lsrs r2, r3, #18
8001272: 4613 mov r3, r2
8001274: 009b lsls r3, r3, #2
8001276: 4413 add r3, r2
8001278: 005b lsls r3, r3, #1
800127a: 60bb str r3, [r7, #8]
while(counter != 0U)
800127c: e002 b.n 8001284 <HAL_ADC_ConfigChannel+0x234>
{
counter--;
800127e: 68bb ldr r3, [r7, #8]
8001280: 3b01 subs r3, #1
8001282: 60bb str r3, [r7, #8]
while(counter != 0U)
8001284: 68bb ldr r3, [r7, #8]
8001286: 2b00 cmp r3, #0
8001288: d1f9 bne.n 800127e <HAL_ADC_ConfigChannel+0x22e>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
800128a: 687b ldr r3, [r7, #4]
800128c: 2200 movs r2, #0
800128e: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Return function status */
return HAL_OK;
8001292: 2300 movs r3, #0
}
8001294: 4618 mov r0, r3
8001296: 3714 adds r7, #20
8001298: 46bd mov sp, r7
800129a: f85d 7b04 ldr.w r7, [sp], #4
800129e: 4770 bx lr
80012a0: 40012300 .word 0x40012300
80012a4: 40012000 .word 0x40012000
80012a8: 10000012 .word 0x10000012
80012ac: 20000000 .word 0x20000000
80012b0: 431bde83 .word 0x431bde83
080012b4 <ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
80012b4: b480 push {r7}
80012b6: b085 sub sp, #20
80012b8: af00 add r7, sp, #0
80012ba: 6078 str r0, [r7, #4]
/* Set ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
80012bc: 4b79 ldr r3, [pc, #484] ; (80014a4 <ADC_Init+0x1f0>)
80012be: 60fb str r3, [r7, #12]
/* Set the ADC clock prescaler */
tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
80012c0: 68fb ldr r3, [r7, #12]
80012c2: 685b ldr r3, [r3, #4]
80012c4: f423 3240 bic.w r2, r3, #196608 ; 0x30000
80012c8: 68fb ldr r3, [r7, #12]
80012ca: 605a str r2, [r3, #4]
tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
80012cc: 68fb ldr r3, [r7, #12]
80012ce: 685a ldr r2, [r3, #4]
80012d0: 687b ldr r3, [r7, #4]
80012d2: 685b ldr r3, [r3, #4]
80012d4: 431a orrs r2, r3
80012d6: 68fb ldr r3, [r7, #12]
80012d8: 605a str r2, [r3, #4]
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
80012da: 687b ldr r3, [r7, #4]
80012dc: 681b ldr r3, [r3, #0]
80012de: 685a ldr r2, [r3, #4]
80012e0: 687b ldr r3, [r7, #4]
80012e2: 681b ldr r3, [r3, #0]
80012e4: f422 7280 bic.w r2, r2, #256 ; 0x100
80012e8: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
80012ea: 687b ldr r3, [r7, #4]
80012ec: 681b ldr r3, [r3, #0]
80012ee: 6859 ldr r1, [r3, #4]
80012f0: 687b ldr r3, [r7, #4]
80012f2: 691b ldr r3, [r3, #16]
80012f4: 021a lsls r2, r3, #8
80012f6: 687b ldr r3, [r7, #4]
80012f8: 681b ldr r3, [r3, #0]
80012fa: 430a orrs r2, r1
80012fc: 605a str r2, [r3, #4]
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
80012fe: 687b ldr r3, [r7, #4]
8001300: 681b ldr r3, [r3, #0]
8001302: 685a ldr r2, [r3, #4]
8001304: 687b ldr r3, [r7, #4]
8001306: 681b ldr r3, [r3, #0]
8001308: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000
800130c: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= hadc->Init.Resolution;
800130e: 687b ldr r3, [r7, #4]
8001310: 681b ldr r3, [r3, #0]
8001312: 6859 ldr r1, [r3, #4]
8001314: 687b ldr r3, [r7, #4]
8001316: 689a ldr r2, [r3, #8]
8001318: 687b ldr r3, [r7, #4]
800131a: 681b ldr r3, [r3, #0]
800131c: 430a orrs r2, r1
800131e: 605a str r2, [r3, #4]
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
8001320: 687b ldr r3, [r7, #4]
8001322: 681b ldr r3, [r3, #0]
8001324: 689a ldr r2, [r3, #8]
8001326: 687b ldr r3, [r7, #4]
8001328: 681b ldr r3, [r3, #0]
800132a: f422 6200 bic.w r2, r2, #2048 ; 0x800
800132e: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.DataAlign;
8001330: 687b ldr r3, [r7, #4]
8001332: 681b ldr r3, [r3, #0]
8001334: 6899 ldr r1, [r3, #8]
8001336: 687b ldr r3, [r7, #4]
8001338: 68da ldr r2, [r3, #12]
800133a: 687b ldr r3, [r7, #4]
800133c: 681b ldr r3, [r3, #0]
800133e: 430a orrs r2, r1
8001340: 609a str r2, [r3, #8]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8001342: 687b ldr r3, [r7, #4]
8001344: 6a9b ldr r3, [r3, #40] ; 0x28
8001346: 4a58 ldr r2, [pc, #352] ; (80014a8 <ADC_Init+0x1f4>)
8001348: 4293 cmp r3, r2
800134a: d022 beq.n 8001392 <ADC_Init+0xde>
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
800134c: 687b ldr r3, [r7, #4]
800134e: 681b ldr r3, [r3, #0]
8001350: 689a ldr r2, [r3, #8]
8001352: 687b ldr r3, [r7, #4]
8001354: 681b ldr r3, [r3, #0]
8001356: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
800135a: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
800135c: 687b ldr r3, [r7, #4]
800135e: 681b ldr r3, [r3, #0]
8001360: 6899 ldr r1, [r3, #8]
8001362: 687b ldr r3, [r7, #4]
8001364: 6a9a ldr r2, [r3, #40] ; 0x28
8001366: 687b ldr r3, [r7, #4]
8001368: 681b ldr r3, [r3, #0]
800136a: 430a orrs r2, r1
800136c: 609a str r2, [r3, #8]
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
800136e: 687b ldr r3, [r7, #4]
8001370: 681b ldr r3, [r3, #0]
8001372: 689a ldr r2, [r3, #8]
8001374: 687b ldr r3, [r7, #4]
8001376: 681b ldr r3, [r3, #0]
8001378: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
800137c: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
800137e: 687b ldr r3, [r7, #4]
8001380: 681b ldr r3, [r3, #0]
8001382: 6899 ldr r1, [r3, #8]
8001384: 687b ldr r3, [r7, #4]
8001386: 6ada ldr r2, [r3, #44] ; 0x2c
8001388: 687b ldr r3, [r7, #4]
800138a: 681b ldr r3, [r3, #0]
800138c: 430a orrs r2, r1
800138e: 609a str r2, [r3, #8]
8001390: e00f b.n 80013b2 <ADC_Init+0xfe>
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
8001392: 687b ldr r3, [r7, #4]
8001394: 681b ldr r3, [r3, #0]
8001396: 689a ldr r2, [r3, #8]
8001398: 687b ldr r3, [r7, #4]
800139a: 681b ldr r3, [r3, #0]
800139c: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000
80013a0: 609a str r2, [r3, #8]
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
80013a2: 687b ldr r3, [r7, #4]
80013a4: 681b ldr r3, [r3, #0]
80013a6: 689a ldr r2, [r3, #8]
80013a8: 687b ldr r3, [r7, #4]
80013aa: 681b ldr r3, [r3, #0]
80013ac: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000
80013b0: 609a str r2, [r3, #8]
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
80013b2: 687b ldr r3, [r7, #4]
80013b4: 681b ldr r3, [r3, #0]
80013b6: 689a ldr r2, [r3, #8]
80013b8: 687b ldr r3, [r7, #4]
80013ba: 681b ldr r3, [r3, #0]
80013bc: f022 0202 bic.w r2, r2, #2
80013c0: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
80013c2: 687b ldr r3, [r7, #4]
80013c4: 681b ldr r3, [r3, #0]
80013c6: 6899 ldr r1, [r3, #8]
80013c8: 687b ldr r3, [r7, #4]
80013ca: 7e1b ldrb r3, [r3, #24]
80013cc: 005a lsls r2, r3, #1
80013ce: 687b ldr r3, [r7, #4]
80013d0: 681b ldr r3, [r3, #0]
80013d2: 430a orrs r2, r1
80013d4: 609a str r2, [r3, #8]
if(hadc->Init.DiscontinuousConvMode != DISABLE)
80013d6: 687b ldr r3, [r7, #4]
80013d8: f893 3020 ldrb.w r3, [r3, #32]
80013dc: 2b00 cmp r3, #0
80013de: d01b beq.n 8001418 <ADC_Init+0x164>
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
80013e0: 687b ldr r3, [r7, #4]
80013e2: 681b ldr r3, [r3, #0]
80013e4: 685a ldr r2, [r3, #4]
80013e6: 687b ldr r3, [r7, #4]
80013e8: 681b ldr r3, [r3, #0]
80013ea: f442 6200 orr.w r2, r2, #2048 ; 0x800
80013ee: 605a str r2, [r3, #4]
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
80013f0: 687b ldr r3, [r7, #4]
80013f2: 681b ldr r3, [r3, #0]
80013f4: 685a ldr r2, [r3, #4]
80013f6: 687b ldr r3, [r7, #4]
80013f8: 681b ldr r3, [r3, #0]
80013fa: f422 4260 bic.w r2, r2, #57344 ; 0xe000
80013fe: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
8001400: 687b ldr r3, [r7, #4]
8001402: 681b ldr r3, [r3, #0]
8001404: 6859 ldr r1, [r3, #4]
8001406: 687b ldr r3, [r7, #4]
8001408: 6a5b ldr r3, [r3, #36] ; 0x24
800140a: 3b01 subs r3, #1
800140c: 035a lsls r2, r3, #13
800140e: 687b ldr r3, [r7, #4]
8001410: 681b ldr r3, [r3, #0]
8001412: 430a orrs r2, r1
8001414: 605a str r2, [r3, #4]
8001416: e007 b.n 8001428 <ADC_Init+0x174>
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
8001418: 687b ldr r3, [r7, #4]
800141a: 681b ldr r3, [r3, #0]
800141c: 685a ldr r2, [r3, #4]
800141e: 687b ldr r3, [r7, #4]
8001420: 681b ldr r3, [r3, #0]
8001422: f422 6200 bic.w r2, r2, #2048 ; 0x800
8001426: 605a str r2, [r3, #4]
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
8001428: 687b ldr r3, [r7, #4]
800142a: 681b ldr r3, [r3, #0]
800142c: 6ada ldr r2, [r3, #44] ; 0x2c
800142e: 687b ldr r3, [r7, #4]
8001430: 681b ldr r3, [r3, #0]
8001432: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000
8001436: 62da str r2, [r3, #44] ; 0x2c
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
8001438: 687b ldr r3, [r7, #4]
800143a: 681b ldr r3, [r3, #0]
800143c: 6ad9 ldr r1, [r3, #44] ; 0x2c
800143e: 687b ldr r3, [r7, #4]
8001440: 69db ldr r3, [r3, #28]
8001442: 3b01 subs r3, #1
8001444: 051a lsls r2, r3, #20
8001446: 687b ldr r3, [r7, #4]
8001448: 681b ldr r3, [r3, #0]
800144a: 430a orrs r2, r1
800144c: 62da str r2, [r3, #44] ; 0x2c
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
800144e: 687b ldr r3, [r7, #4]
8001450: 681b ldr r3, [r3, #0]
8001452: 689a ldr r2, [r3, #8]
8001454: 687b ldr r3, [r7, #4]
8001456: 681b ldr r3, [r3, #0]
8001458: f422 7200 bic.w r2, r2, #512 ; 0x200
800145c: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
800145e: 687b ldr r3, [r7, #4]
8001460: 681b ldr r3, [r3, #0]
8001462: 6899 ldr r1, [r3, #8]
8001464: 687b ldr r3, [r7, #4]
8001466: f893 3030 ldrb.w r3, [r3, #48] ; 0x30
800146a: 025a lsls r2, r3, #9
800146c: 687b ldr r3, [r7, #4]
800146e: 681b ldr r3, [r3, #0]
8001470: 430a orrs r2, r1
8001472: 609a str r2, [r3, #8]
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
8001474: 687b ldr r3, [r7, #4]
8001476: 681b ldr r3, [r3, #0]
8001478: 689a ldr r2, [r3, #8]
800147a: 687b ldr r3, [r7, #4]
800147c: 681b ldr r3, [r3, #0]
800147e: f422 6280 bic.w r2, r2, #1024 ; 0x400
8001482: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
8001484: 687b ldr r3, [r7, #4]
8001486: 681b ldr r3, [r3, #0]
8001488: 6899 ldr r1, [r3, #8]
800148a: 687b ldr r3, [r7, #4]
800148c: 695b ldr r3, [r3, #20]
800148e: 029a lsls r2, r3, #10
8001490: 687b ldr r3, [r7, #4]
8001492: 681b ldr r3, [r3, #0]
8001494: 430a orrs r2, r1
8001496: 609a str r2, [r3, #8]
}
8001498: bf00 nop
800149a: 3714 adds r7, #20
800149c: 46bd mov sp, r7
800149e: f85d 7b04 ldr.w r7, [sp], #4
80014a2: 4770 bx lr
80014a4: 40012300 .word 0x40012300
80014a8: 0f000001 .word 0x0f000001
080014ac <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80014ac: b480 push {r7}
80014ae: b085 sub sp, #20
80014b0: af00 add r7, sp, #0
80014b2: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80014b4: 687b ldr r3, [r7, #4]
80014b6: f003 0307 and.w r3, r3, #7
80014ba: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80014bc: 4b0c ldr r3, [pc, #48] ; (80014f0 <__NVIC_SetPriorityGrouping+0x44>)
80014be: 68db ldr r3, [r3, #12]
80014c0: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80014c2: 68ba ldr r2, [r7, #8]
80014c4: f64f 03ff movw r3, #63743 ; 0xf8ff
80014c8: 4013 ands r3, r2
80014ca: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80014cc: 68fb ldr r3, [r7, #12]
80014ce: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80014d0: 68bb ldr r3, [r7, #8]
80014d2: 4313 orrs r3, r2
reg_value = (reg_value |
80014d4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
80014d8: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80014dc: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80014de: 4a04 ldr r2, [pc, #16] ; (80014f0 <__NVIC_SetPriorityGrouping+0x44>)
80014e0: 68bb ldr r3, [r7, #8]
80014e2: 60d3 str r3, [r2, #12]
}
80014e4: bf00 nop
80014e6: 3714 adds r7, #20
80014e8: 46bd mov sp, r7
80014ea: f85d 7b04 ldr.w r7, [sp], #4
80014ee: 4770 bx lr
80014f0: e000ed00 .word 0xe000ed00
080014f4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80014f4: b480 push {r7}
80014f6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80014f8: 4b04 ldr r3, [pc, #16] ; (800150c <__NVIC_GetPriorityGrouping+0x18>)
80014fa: 68db ldr r3, [r3, #12]
80014fc: 0a1b lsrs r3, r3, #8
80014fe: f003 0307 and.w r3, r3, #7
}
8001502: 4618 mov r0, r3
8001504: 46bd mov sp, r7
8001506: f85d 7b04 ldr.w r7, [sp], #4
800150a: 4770 bx lr
800150c: e000ed00 .word 0xe000ed00
08001510 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001510: b480 push {r7}
8001512: b083 sub sp, #12
8001514: af00 add r7, sp, #0
8001516: 4603 mov r3, r0
8001518: 6039 str r1, [r7, #0]
800151a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800151c: f997 3007 ldrsb.w r3, [r7, #7]
8001520: 2b00 cmp r3, #0
8001522: db0a blt.n 800153a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001524: 683b ldr r3, [r7, #0]
8001526: b2da uxtb r2, r3
8001528: 490c ldr r1, [pc, #48] ; (800155c <__NVIC_SetPriority+0x4c>)
800152a: f997 3007 ldrsb.w r3, [r7, #7]
800152e: 0112 lsls r2, r2, #4
8001530: b2d2 uxtb r2, r2
8001532: 440b add r3, r1
8001534: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001538: e00a b.n 8001550 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800153a: 683b ldr r3, [r7, #0]
800153c: b2da uxtb r2, r3
800153e: 4908 ldr r1, [pc, #32] ; (8001560 <__NVIC_SetPriority+0x50>)
8001540: 79fb ldrb r3, [r7, #7]
8001542: f003 030f and.w r3, r3, #15
8001546: 3b04 subs r3, #4
8001548: 0112 lsls r2, r2, #4
800154a: b2d2 uxtb r2, r2
800154c: 440b add r3, r1
800154e: 761a strb r2, [r3, #24]
}
8001550: bf00 nop
8001552: 370c adds r7, #12
8001554: 46bd mov sp, r7
8001556: f85d 7b04 ldr.w r7, [sp], #4
800155a: 4770 bx lr
800155c: e000e100 .word 0xe000e100
8001560: e000ed00 .word 0xe000ed00
08001564 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001564: b480 push {r7}
8001566: b089 sub sp, #36 ; 0x24
8001568: af00 add r7, sp, #0
800156a: 60f8 str r0, [r7, #12]
800156c: 60b9 str r1, [r7, #8]
800156e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001570: 68fb ldr r3, [r7, #12]
8001572: f003 0307 and.w r3, r3, #7
8001576: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001578: 69fb ldr r3, [r7, #28]
800157a: f1c3 0307 rsb r3, r3, #7
800157e: 2b04 cmp r3, #4
8001580: bf28 it cs
8001582: 2304 movcs r3, #4
8001584: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001586: 69fb ldr r3, [r7, #28]
8001588: 3304 adds r3, #4
800158a: 2b06 cmp r3, #6
800158c: d902 bls.n 8001594 <NVIC_EncodePriority+0x30>
800158e: 69fb ldr r3, [r7, #28]
8001590: 3b03 subs r3, #3
8001592: e000 b.n 8001596 <NVIC_EncodePriority+0x32>
8001594: 2300 movs r3, #0
8001596: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001598: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800159c: 69bb ldr r3, [r7, #24]
800159e: fa02 f303 lsl.w r3, r2, r3
80015a2: 43da mvns r2, r3
80015a4: 68bb ldr r3, [r7, #8]
80015a6: 401a ands r2, r3
80015a8: 697b ldr r3, [r7, #20]
80015aa: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80015ac: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
80015b0: 697b ldr r3, [r7, #20]
80015b2: fa01 f303 lsl.w r3, r1, r3
80015b6: 43d9 mvns r1, r3
80015b8: 687b ldr r3, [r7, #4]
80015ba: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80015bc: 4313 orrs r3, r2
);
}
80015be: 4618 mov r0, r3
80015c0: 3724 adds r7, #36 ; 0x24
80015c2: 46bd mov sp, r7
80015c4: f85d 7b04 ldr.w r7, [sp], #4
80015c8: 4770 bx lr
...
080015cc <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80015cc: b580 push {r7, lr}
80015ce: b082 sub sp, #8
80015d0: af00 add r7, sp, #0
80015d2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80015d4: 687b ldr r3, [r7, #4]
80015d6: 3b01 subs r3, #1
80015d8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
80015dc: d301 bcc.n 80015e2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80015de: 2301 movs r3, #1
80015e0: e00f b.n 8001602 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80015e2: 4a0a ldr r2, [pc, #40] ; (800160c <SysTick_Config+0x40>)
80015e4: 687b ldr r3, [r7, #4]
80015e6: 3b01 subs r3, #1
80015e8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80015ea: 210f movs r1, #15
80015ec: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
80015f0: f7ff ff8e bl 8001510 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80015f4: 4b05 ldr r3, [pc, #20] ; (800160c <SysTick_Config+0x40>)
80015f6: 2200 movs r2, #0
80015f8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80015fa: 4b04 ldr r3, [pc, #16] ; (800160c <SysTick_Config+0x40>)
80015fc: 2207 movs r2, #7
80015fe: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001600: 2300 movs r3, #0
}
8001602: 4618 mov r0, r3
8001604: 3708 adds r7, #8
8001606: 46bd mov sp, r7
8001608: bd80 pop {r7, pc}
800160a: bf00 nop
800160c: e000e010 .word 0xe000e010
08001610 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001610: b580 push {r7, lr}
8001612: b082 sub sp, #8
8001614: af00 add r7, sp, #0
8001616: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001618: 6878 ldr r0, [r7, #4]
800161a: f7ff ff47 bl 80014ac <__NVIC_SetPriorityGrouping>
}
800161e: bf00 nop
8001620: 3708 adds r7, #8
8001622: 46bd mov sp, r7
8001624: bd80 pop {r7, pc}
08001626 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001626: b580 push {r7, lr}
8001628: b086 sub sp, #24
800162a: af00 add r7, sp, #0
800162c: 4603 mov r3, r0
800162e: 60b9 str r1, [r7, #8]
8001630: 607a str r2, [r7, #4]
8001632: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001634: 2300 movs r3, #0
8001636: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001638: f7ff ff5c bl 80014f4 <__NVIC_GetPriorityGrouping>
800163c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800163e: 687a ldr r2, [r7, #4]
8001640: 68b9 ldr r1, [r7, #8]
8001642: 6978 ldr r0, [r7, #20]
8001644: f7ff ff8e bl 8001564 <NVIC_EncodePriority>
8001648: 4602 mov r2, r0
800164a: f997 300f ldrsb.w r3, [r7, #15]
800164e: 4611 mov r1, r2
8001650: 4618 mov r0, r3
8001652: f7ff ff5d bl 8001510 <__NVIC_SetPriority>
}
8001656: bf00 nop
8001658: 3718 adds r7, #24
800165a: 46bd mov sp, r7
800165c: bd80 pop {r7, pc}
0800165e <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800165e: b580 push {r7, lr}
8001660: b082 sub sp, #8
8001662: af00 add r7, sp, #0
8001664: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001666: 6878 ldr r0, [r7, #4]
8001668: f7ff ffb0 bl 80015cc <SysTick_Config>
800166c: 4603 mov r3, r0
}
800166e: 4618 mov r0, r3
8001670: 3708 adds r7, #8
8001672: 46bd mov sp, r7
8001674: bd80 pop {r7, pc}
08001676 <HAL_DMA_Start_IT>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8001676: b580 push {r7, lr}
8001678: b086 sub sp, #24
800167a: af00 add r7, sp, #0
800167c: 60f8 str r0, [r7, #12]
800167e: 60b9 str r1, [r7, #8]
8001680: 607a str r2, [r7, #4]
8001682: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8001684: 2300 movs r3, #0
8001686: 75fb strb r3, [r7, #23]
/* calculate DMA base and stream number */
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
8001688: 68fb ldr r3, [r7, #12]
800168a: 6d9b ldr r3, [r3, #88] ; 0x58
800168c: 613b str r3, [r7, #16]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
800168e: 68fb ldr r3, [r7, #12]
8001690: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
8001694: 2b01 cmp r3, #1
8001696: d101 bne.n 800169c <HAL_DMA_Start_IT+0x26>
8001698: 2302 movs r3, #2
800169a: e040 b.n 800171e <HAL_DMA_Start_IT+0xa8>
800169c: 68fb ldr r3, [r7, #12]
800169e: 2201 movs r2, #1
80016a0: f883 2034 strb.w r2, [r3, #52] ; 0x34
if(HAL_DMA_STATE_READY == hdma->State)
80016a4: 68fb ldr r3, [r7, #12]
80016a6: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
80016aa: b2db uxtb r3, r3
80016ac: 2b01 cmp r3, #1
80016ae: d12f bne.n 8001710 <HAL_DMA_Start_IT+0x9a>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
80016b0: 68fb ldr r3, [r7, #12]
80016b2: 2202 movs r2, #2
80016b4: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80016b8: 68fb ldr r3, [r7, #12]
80016ba: 2200 movs r2, #0
80016bc: 655a str r2, [r3, #84] ; 0x54
/* Configure the source, destination address and the data length */
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
80016be: 683b ldr r3, [r7, #0]
80016c0: 687a ldr r2, [r7, #4]
80016c2: 68b9 ldr r1, [r7, #8]
80016c4: 68f8 ldr r0, [r7, #12]
80016c6: f000 f83a bl 800173e <DMA_SetConfig>
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
80016ca: 68fb ldr r3, [r7, #12]
80016cc: 6ddb ldr r3, [r3, #92] ; 0x5c
80016ce: 223f movs r2, #63 ; 0x3f
80016d0: 409a lsls r2, r3
80016d2: 693b ldr r3, [r7, #16]
80016d4: 609a str r2, [r3, #8]
/* Enable Common interrupts*/
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
80016d6: 68fb ldr r3, [r7, #12]
80016d8: 681b ldr r3, [r3, #0]
80016da: 681a ldr r2, [r3, #0]
80016dc: 68fb ldr r3, [r7, #12]
80016de: 681b ldr r3, [r3, #0]
80016e0: f042 0216 orr.w r2, r2, #22
80016e4: 601a str r2, [r3, #0]
if(hdma->XferHalfCpltCallback != NULL)
80016e6: 68fb ldr r3, [r7, #12]
80016e8: 6c1b ldr r3, [r3, #64] ; 0x40
80016ea: 2b00 cmp r3, #0
80016ec: d007 beq.n 80016fe <HAL_DMA_Start_IT+0x88>
{
hdma->Instance->CR |= DMA_IT_HT;
80016ee: 68fb ldr r3, [r7, #12]
80016f0: 681b ldr r3, [r3, #0]
80016f2: 681a ldr r2, [r3, #0]
80016f4: 68fb ldr r3, [r7, #12]
80016f6: 681b ldr r3, [r3, #0]
80016f8: f042 0208 orr.w r2, r2, #8
80016fc: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
80016fe: 68fb ldr r3, [r7, #12]
8001700: 681b ldr r3, [r3, #0]
8001702: 681a ldr r2, [r3, #0]
8001704: 68fb ldr r3, [r7, #12]
8001706: 681b ldr r3, [r3, #0]
8001708: f042 0201 orr.w r2, r2, #1
800170c: 601a str r2, [r3, #0]
800170e: e005 b.n 800171c <HAL_DMA_Start_IT+0xa6>
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdma);
8001710: 68fb ldr r3, [r7, #12]
8001712: 2200 movs r2, #0
8001714: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Return error status */
status = HAL_BUSY;
8001718: 2302 movs r3, #2
800171a: 75fb strb r3, [r7, #23]
}
return status;
800171c: 7dfb ldrb r3, [r7, #23]
}
800171e: 4618 mov r0, r3
8001720: 3718 adds r7, #24
8001722: 46bd mov sp, r7
8001724: bd80 pop {r7, pc}
08001726 <HAL_DMA_GetError>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval DMA Error Code
*/
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
{
8001726: b480 push {r7}
8001728: b083 sub sp, #12
800172a: af00 add r7, sp, #0
800172c: 6078 str r0, [r7, #4]
return hdma->ErrorCode;
800172e: 687b ldr r3, [r7, #4]
8001730: 6d5b ldr r3, [r3, #84] ; 0x54
}
8001732: 4618 mov r0, r3
8001734: 370c adds r7, #12
8001736: 46bd mov sp, r7
8001738: f85d 7b04 ldr.w r7, [sp], #4
800173c: 4770 bx lr
0800173e <DMA_SetConfig>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
800173e: b480 push {r7}
8001740: b085 sub sp, #20
8001742: af00 add r7, sp, #0
8001744: 60f8 str r0, [r7, #12]
8001746: 60b9 str r1, [r7, #8]
8001748: 607a str r2, [r7, #4]
800174a: 603b str r3, [r7, #0]
/* Clear DBM bit */
hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
800174c: 68fb ldr r3, [r7, #12]
800174e: 681b ldr r3, [r3, #0]
8001750: 681a ldr r2, [r3, #0]
8001752: 68fb ldr r3, [r7, #12]
8001754: 681b ldr r3, [r3, #0]
8001756: f422 2280 bic.w r2, r2, #262144 ; 0x40000
800175a: 601a str r2, [r3, #0]
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
800175c: 68fb ldr r3, [r7, #12]
800175e: 681b ldr r3, [r3, #0]
8001760: 683a ldr r2, [r7, #0]
8001762: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8001764: 68fb ldr r3, [r7, #12]
8001766: 689b ldr r3, [r3, #8]
8001768: 2b40 cmp r3, #64 ; 0x40
800176a: d108 bne.n 800177e <DMA_SetConfig+0x40>
{
/* Configure DMA Stream destination address */
hdma->Instance->PAR = DstAddress;
800176c: 68fb ldr r3, [r7, #12]
800176e: 681b ldr r3, [r3, #0]
8001770: 687a ldr r2, [r7, #4]
8001772: 609a str r2, [r3, #8]
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
8001774: 68fb ldr r3, [r7, #12]
8001776: 681b ldr r3, [r3, #0]
8001778: 68ba ldr r2, [r7, #8]
800177a: 60da str r2, [r3, #12]
hdma->Instance->PAR = SrcAddress;
/* Configure DMA Stream destination address */
hdma->Instance->M0AR = DstAddress;
}
}
800177c: e007 b.n 800178e <DMA_SetConfig+0x50>
hdma->Instance->PAR = SrcAddress;
800177e: 68fb ldr r3, [r7, #12]
8001780: 681b ldr r3, [r3, #0]
8001782: 68ba ldr r2, [r7, #8]
8001784: 609a str r2, [r3, #8]
hdma->Instance->M0AR = DstAddress;
8001786: 68fb ldr r3, [r7, #12]
8001788: 681b ldr r3, [r3, #0]
800178a: 687a ldr r2, [r7, #4]
800178c: 60da str r2, [r3, #12]
}
800178e: bf00 nop
8001790: 3714 adds r7, #20
8001792: 46bd mov sp, r7
8001794: f85d 7b04 ldr.w r7, [sp], #4
8001798: 4770 bx lr
...
0800179c <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
800179c: b480 push {r7}
800179e: b089 sub sp, #36 ; 0x24
80017a0: af00 add r7, sp, #0
80017a2: 6078 str r0, [r7, #4]
80017a4: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
80017a6: 2300 movs r3, #0
80017a8: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
80017aa: 2300 movs r3, #0
80017ac: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
80017ae: 2300 movs r3, #0
80017b0: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
80017b2: 2300 movs r3, #0
80017b4: 61fb str r3, [r7, #28]
80017b6: e159 b.n 8001a6c <HAL_GPIO_Init+0x2d0>
{
/* Get the IO position */
ioposition = 0x01U << position;
80017b8: 2201 movs r2, #1
80017ba: 69fb ldr r3, [r7, #28]
80017bc: fa02 f303 lsl.w r3, r2, r3
80017c0: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80017c2: 683b ldr r3, [r7, #0]
80017c4: 681b ldr r3, [r3, #0]
80017c6: 697a ldr r2, [r7, #20]
80017c8: 4013 ands r3, r2
80017ca: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
80017cc: 693a ldr r2, [r7, #16]
80017ce: 697b ldr r3, [r7, #20]
80017d0: 429a cmp r2, r3
80017d2: f040 8148 bne.w 8001a66 <HAL_GPIO_Init+0x2ca>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
80017d6: 683b ldr r3, [r7, #0]
80017d8: 685b ldr r3, [r3, #4]
80017da: f003 0303 and.w r3, r3, #3
80017de: 2b01 cmp r3, #1
80017e0: d005 beq.n 80017ee <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80017e2: 683b ldr r3, [r7, #0]
80017e4: 685b ldr r3, [r3, #4]
80017e6: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
80017ea: 2b02 cmp r3, #2
80017ec: d130 bne.n 8001850 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80017ee: 687b ldr r3, [r7, #4]
80017f0: 689b ldr r3, [r3, #8]
80017f2: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
80017f4: 69fb ldr r3, [r7, #28]
80017f6: 005b lsls r3, r3, #1
80017f8: 2203 movs r2, #3
80017fa: fa02 f303 lsl.w r3, r2, r3
80017fe: 43db mvns r3, r3
8001800: 69ba ldr r2, [r7, #24]
8001802: 4013 ands r3, r2
8001804: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8001806: 683b ldr r3, [r7, #0]
8001808: 68da ldr r2, [r3, #12]
800180a: 69fb ldr r3, [r7, #28]
800180c: 005b lsls r3, r3, #1
800180e: fa02 f303 lsl.w r3, r2, r3
8001812: 69ba ldr r2, [r7, #24]
8001814: 4313 orrs r3, r2
8001816: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001818: 687b ldr r3, [r7, #4]
800181a: 69ba ldr r2, [r7, #24]
800181c: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
800181e: 687b ldr r3, [r7, #4]
8001820: 685b ldr r3, [r3, #4]
8001822: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001824: 2201 movs r2, #1
8001826: 69fb ldr r3, [r7, #28]
8001828: fa02 f303 lsl.w r3, r2, r3
800182c: 43db mvns r3, r3
800182e: 69ba ldr r2, [r7, #24]
8001830: 4013 ands r3, r2
8001832: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
8001834: 683b ldr r3, [r7, #0]
8001836: 685b ldr r3, [r3, #4]
8001838: 091b lsrs r3, r3, #4
800183a: f003 0201 and.w r2, r3, #1
800183e: 69fb ldr r3, [r7, #28]
8001840: fa02 f303 lsl.w r3, r2, r3
8001844: 69ba ldr r2, [r7, #24]
8001846: 4313 orrs r3, r2
8001848: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
800184a: 687b ldr r3, [r7, #4]
800184c: 69ba ldr r2, [r7, #24]
800184e: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001850: 683b ldr r3, [r7, #0]
8001852: 685b ldr r3, [r3, #4]
8001854: f003 0303 and.w r3, r3, #3
8001858: 2b03 cmp r3, #3
800185a: d017 beq.n 800188c <HAL_GPIO_Init+0xf0>
{
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
800185c: 687b ldr r3, [r7, #4]
800185e: 68db ldr r3, [r3, #12]
8001860: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8001862: 69fb ldr r3, [r7, #28]
8001864: 005b lsls r3, r3, #1
8001866: 2203 movs r2, #3
8001868: fa02 f303 lsl.w r3, r2, r3
800186c: 43db mvns r3, r3
800186e: 69ba ldr r2, [r7, #24]
8001870: 4013 ands r3, r2
8001872: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8001874: 683b ldr r3, [r7, #0]
8001876: 689a ldr r2, [r3, #8]
8001878: 69fb ldr r3, [r7, #28]
800187a: 005b lsls r3, r3, #1
800187c: fa02 f303 lsl.w r3, r2, r3
8001880: 69ba ldr r2, [r7, #24]
8001882: 4313 orrs r3, r2
8001884: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8001886: 687b ldr r3, [r7, #4]
8001888: 69ba ldr r2, [r7, #24]
800188a: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
800188c: 683b ldr r3, [r7, #0]
800188e: 685b ldr r3, [r3, #4]
8001890: f003 0303 and.w r3, r3, #3
8001894: 2b02 cmp r3, #2
8001896: d123 bne.n 80018e0 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8001898: 69fb ldr r3, [r7, #28]
800189a: 08da lsrs r2, r3, #3
800189c: 687b ldr r3, [r7, #4]
800189e: 3208 adds r2, #8
80018a0: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80018a4: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
80018a6: 69fb ldr r3, [r7, #28]
80018a8: f003 0307 and.w r3, r3, #7
80018ac: 009b lsls r3, r3, #2
80018ae: 220f movs r2, #15
80018b0: fa02 f303 lsl.w r3, r2, r3
80018b4: 43db mvns r3, r3
80018b6: 69ba ldr r2, [r7, #24]
80018b8: 4013 ands r3, r2
80018ba: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
80018bc: 683b ldr r3, [r7, #0]
80018be: 691a ldr r2, [r3, #16]
80018c0: 69fb ldr r3, [r7, #28]
80018c2: f003 0307 and.w r3, r3, #7
80018c6: 009b lsls r3, r3, #2
80018c8: fa02 f303 lsl.w r3, r2, r3
80018cc: 69ba ldr r2, [r7, #24]
80018ce: 4313 orrs r3, r2
80018d0: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
80018d2: 69fb ldr r3, [r7, #28]
80018d4: 08da lsrs r2, r3, #3
80018d6: 687b ldr r3, [r7, #4]
80018d8: 3208 adds r2, #8
80018da: 69b9 ldr r1, [r7, #24]
80018dc: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80018e0: 687b ldr r3, [r7, #4]
80018e2: 681b ldr r3, [r3, #0]
80018e4: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
80018e6: 69fb ldr r3, [r7, #28]
80018e8: 005b lsls r3, r3, #1
80018ea: 2203 movs r2, #3
80018ec: fa02 f303 lsl.w r3, r2, r3
80018f0: 43db mvns r3, r3
80018f2: 69ba ldr r2, [r7, #24]
80018f4: 4013 ands r3, r2
80018f6: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
80018f8: 683b ldr r3, [r7, #0]
80018fa: 685b ldr r3, [r3, #4]
80018fc: f003 0203 and.w r2, r3, #3
8001900: 69fb ldr r3, [r7, #28]
8001902: 005b lsls r3, r3, #1
8001904: fa02 f303 lsl.w r3, r2, r3
8001908: 69ba ldr r2, [r7, #24]
800190a: 4313 orrs r3, r2
800190c: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
800190e: 687b ldr r3, [r7, #4]
8001910: 69ba ldr r2, [r7, #24]
8001912: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8001914: 683b ldr r3, [r7, #0]
8001916: 685b ldr r3, [r3, #4]
8001918: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800191c: 2b00 cmp r3, #0
800191e: f000 80a2 beq.w 8001a66 <HAL_GPIO_Init+0x2ca>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001922: 2300 movs r3, #0
8001924: 60fb str r3, [r7, #12]
8001926: 4b57 ldr r3, [pc, #348] ; (8001a84 <HAL_GPIO_Init+0x2e8>)
8001928: 6c5b ldr r3, [r3, #68] ; 0x44
800192a: 4a56 ldr r2, [pc, #344] ; (8001a84 <HAL_GPIO_Init+0x2e8>)
800192c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001930: 6453 str r3, [r2, #68] ; 0x44
8001932: 4b54 ldr r3, [pc, #336] ; (8001a84 <HAL_GPIO_Init+0x2e8>)
8001934: 6c5b ldr r3, [r3, #68] ; 0x44
8001936: f403 4380 and.w r3, r3, #16384 ; 0x4000
800193a: 60fb str r3, [r7, #12]
800193c: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
800193e: 4a52 ldr r2, [pc, #328] ; (8001a88 <HAL_GPIO_Init+0x2ec>)
8001940: 69fb ldr r3, [r7, #28]
8001942: 089b lsrs r3, r3, #2
8001944: 3302 adds r3, #2
8001946: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800194a: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
800194c: 69fb ldr r3, [r7, #28]
800194e: f003 0303 and.w r3, r3, #3
8001952: 009b lsls r3, r3, #2
8001954: 220f movs r2, #15
8001956: fa02 f303 lsl.w r3, r2, r3
800195a: 43db mvns r3, r3
800195c: 69ba ldr r2, [r7, #24]
800195e: 4013 ands r3, r2
8001960: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8001962: 687b ldr r3, [r7, #4]
8001964: 4a49 ldr r2, [pc, #292] ; (8001a8c <HAL_GPIO_Init+0x2f0>)
8001966: 4293 cmp r3, r2
8001968: d019 beq.n 800199e <HAL_GPIO_Init+0x202>
800196a: 687b ldr r3, [r7, #4]
800196c: 4a48 ldr r2, [pc, #288] ; (8001a90 <HAL_GPIO_Init+0x2f4>)
800196e: 4293 cmp r3, r2
8001970: d013 beq.n 800199a <HAL_GPIO_Init+0x1fe>
8001972: 687b ldr r3, [r7, #4]
8001974: 4a47 ldr r2, [pc, #284] ; (8001a94 <HAL_GPIO_Init+0x2f8>)
8001976: 4293 cmp r3, r2
8001978: d00d beq.n 8001996 <HAL_GPIO_Init+0x1fa>
800197a: 687b ldr r3, [r7, #4]
800197c: 4a46 ldr r2, [pc, #280] ; (8001a98 <HAL_GPIO_Init+0x2fc>)
800197e: 4293 cmp r3, r2
8001980: d007 beq.n 8001992 <HAL_GPIO_Init+0x1f6>
8001982: 687b ldr r3, [r7, #4]
8001984: 4a45 ldr r2, [pc, #276] ; (8001a9c <HAL_GPIO_Init+0x300>)
8001986: 4293 cmp r3, r2
8001988: d101 bne.n 800198e <HAL_GPIO_Init+0x1f2>
800198a: 2304 movs r3, #4
800198c: e008 b.n 80019a0 <HAL_GPIO_Init+0x204>
800198e: 2307 movs r3, #7
8001990: e006 b.n 80019a0 <HAL_GPIO_Init+0x204>
8001992: 2303 movs r3, #3
8001994: e004 b.n 80019a0 <HAL_GPIO_Init+0x204>
8001996: 2302 movs r3, #2
8001998: e002 b.n 80019a0 <HAL_GPIO_Init+0x204>
800199a: 2301 movs r3, #1
800199c: e000 b.n 80019a0 <HAL_GPIO_Init+0x204>
800199e: 2300 movs r3, #0
80019a0: 69fa ldr r2, [r7, #28]
80019a2: f002 0203 and.w r2, r2, #3
80019a6: 0092 lsls r2, r2, #2
80019a8: 4093 lsls r3, r2
80019aa: 69ba ldr r2, [r7, #24]
80019ac: 4313 orrs r3, r2
80019ae: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
80019b0: 4935 ldr r1, [pc, #212] ; (8001a88 <HAL_GPIO_Init+0x2ec>)
80019b2: 69fb ldr r3, [r7, #28]
80019b4: 089b lsrs r3, r3, #2
80019b6: 3302 adds r3, #2
80019b8: 69ba ldr r2, [r7, #24]
80019ba: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80019be: 4b38 ldr r3, [pc, #224] ; (8001aa0 <HAL_GPIO_Init+0x304>)
80019c0: 681b ldr r3, [r3, #0]
80019c2: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80019c4: 693b ldr r3, [r7, #16]
80019c6: 43db mvns r3, r3
80019c8: 69ba ldr r2, [r7, #24]
80019ca: 4013 ands r3, r2
80019cc: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
80019ce: 683b ldr r3, [r7, #0]
80019d0: 685b ldr r3, [r3, #4]
80019d2: f403 3380 and.w r3, r3, #65536 ; 0x10000
80019d6: 2b00 cmp r3, #0
80019d8: d003 beq.n 80019e2 <HAL_GPIO_Init+0x246>
{
temp |= iocurrent;
80019da: 69ba ldr r2, [r7, #24]
80019dc: 693b ldr r3, [r7, #16]
80019de: 4313 orrs r3, r2
80019e0: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
80019e2: 4a2f ldr r2, [pc, #188] ; (8001aa0 <HAL_GPIO_Init+0x304>)
80019e4: 69bb ldr r3, [r7, #24]
80019e6: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
80019e8: 4b2d ldr r3, [pc, #180] ; (8001aa0 <HAL_GPIO_Init+0x304>)
80019ea: 685b ldr r3, [r3, #4]
80019ec: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80019ee: 693b ldr r3, [r7, #16]
80019f0: 43db mvns r3, r3
80019f2: 69ba ldr r2, [r7, #24]
80019f4: 4013 ands r3, r2
80019f6: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
80019f8: 683b ldr r3, [r7, #0]
80019fa: 685b ldr r3, [r3, #4]
80019fc: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001a00: 2b00 cmp r3, #0
8001a02: d003 beq.n 8001a0c <HAL_GPIO_Init+0x270>
{
temp |= iocurrent;
8001a04: 69ba ldr r2, [r7, #24]
8001a06: 693b ldr r3, [r7, #16]
8001a08: 4313 orrs r3, r2
8001a0a: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8001a0c: 4a24 ldr r2, [pc, #144] ; (8001aa0 <HAL_GPIO_Init+0x304>)
8001a0e: 69bb ldr r3, [r7, #24]
8001a10: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001a12: 4b23 ldr r3, [pc, #140] ; (8001aa0 <HAL_GPIO_Init+0x304>)
8001a14: 689b ldr r3, [r3, #8]
8001a16: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001a18: 693b ldr r3, [r7, #16]
8001a1a: 43db mvns r3, r3
8001a1c: 69ba ldr r2, [r7, #24]
8001a1e: 4013 ands r3, r2
8001a20: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
8001a22: 683b ldr r3, [r7, #0]
8001a24: 685b ldr r3, [r3, #4]
8001a26: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8001a2a: 2b00 cmp r3, #0
8001a2c: d003 beq.n 8001a36 <HAL_GPIO_Init+0x29a>
{
temp |= iocurrent;
8001a2e: 69ba ldr r2, [r7, #24]
8001a30: 693b ldr r3, [r7, #16]
8001a32: 4313 orrs r3, r2
8001a34: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001a36: 4a1a ldr r2, [pc, #104] ; (8001aa0 <HAL_GPIO_Init+0x304>)
8001a38: 69bb ldr r3, [r7, #24]
8001a3a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001a3c: 4b18 ldr r3, [pc, #96] ; (8001aa0 <HAL_GPIO_Init+0x304>)
8001a3e: 68db ldr r3, [r3, #12]
8001a40: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001a42: 693b ldr r3, [r7, #16]
8001a44: 43db mvns r3, r3
8001a46: 69ba ldr r2, [r7, #24]
8001a48: 4013 ands r3, r2
8001a4a: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
8001a4c: 683b ldr r3, [r7, #0]
8001a4e: 685b ldr r3, [r3, #4]
8001a50: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001a54: 2b00 cmp r3, #0
8001a56: d003 beq.n 8001a60 <HAL_GPIO_Init+0x2c4>
{
temp |= iocurrent;
8001a58: 69ba ldr r2, [r7, #24]
8001a5a: 693b ldr r3, [r7, #16]
8001a5c: 4313 orrs r3, r2
8001a5e: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001a60: 4a0f ldr r2, [pc, #60] ; (8001aa0 <HAL_GPIO_Init+0x304>)
8001a62: 69bb ldr r3, [r7, #24]
8001a64: 60d3 str r3, [r2, #12]
for(position = 0U; position < GPIO_NUMBER; position++)
8001a66: 69fb ldr r3, [r7, #28]
8001a68: 3301 adds r3, #1
8001a6a: 61fb str r3, [r7, #28]
8001a6c: 69fb ldr r3, [r7, #28]
8001a6e: 2b0f cmp r3, #15
8001a70: f67f aea2 bls.w 80017b8 <HAL_GPIO_Init+0x1c>
}
}
}
}
8001a74: bf00 nop
8001a76: bf00 nop
8001a78: 3724 adds r7, #36 ; 0x24
8001a7a: 46bd mov sp, r7
8001a7c: f85d 7b04 ldr.w r7, [sp], #4
8001a80: 4770 bx lr
8001a82: bf00 nop
8001a84: 40023800 .word 0x40023800
8001a88: 40013800 .word 0x40013800
8001a8c: 40020000 .word 0x40020000
8001a90: 40020400 .word 0x40020400
8001a94: 40020800 .word 0x40020800
8001a98: 40020c00 .word 0x40020c00
8001a9c: 40021000 .word 0x40021000
8001aa0: 40013c00 .word 0x40013c00
08001aa4 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001aa4: b480 push {r7}
8001aa6: b085 sub sp, #20
8001aa8: af00 add r7, sp, #0
8001aaa: 6078 str r0, [r7, #4]
8001aac: 460b mov r3, r1
8001aae: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001ab0: 687b ldr r3, [r7, #4]
8001ab2: 691a ldr r2, [r3, #16]
8001ab4: 887b ldrh r3, [r7, #2]
8001ab6: 4013 ands r3, r2
8001ab8: 2b00 cmp r3, #0
8001aba: d002 beq.n 8001ac2 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001abc: 2301 movs r3, #1
8001abe: 73fb strb r3, [r7, #15]
8001ac0: e001 b.n 8001ac6 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8001ac2: 2300 movs r3, #0
8001ac4: 73fb strb r3, [r7, #15]
}
return bitstatus;
8001ac6: 7bfb ldrb r3, [r7, #15]
}
8001ac8: 4618 mov r0, r3
8001aca: 3714 adds r7, #20
8001acc: 46bd mov sp, r7
8001ace: f85d 7b04 ldr.w r7, [sp], #4
8001ad2: 4770 bx lr
08001ad4 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001ad4: b480 push {r7}
8001ad6: b083 sub sp, #12
8001ad8: af00 add r7, sp, #0
8001ada: 6078 str r0, [r7, #4]
8001adc: 460b mov r3, r1
8001ade: 807b strh r3, [r7, #2]
8001ae0: 4613 mov r3, r2
8001ae2: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001ae4: 787b ldrb r3, [r7, #1]
8001ae6: 2b00 cmp r3, #0
8001ae8: d003 beq.n 8001af2 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001aea: 887a ldrh r2, [r7, #2]
8001aec: 687b ldr r3, [r7, #4]
8001aee: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8001af0: e003 b.n 8001afa <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8001af2: 887b ldrh r3, [r7, #2]
8001af4: 041a lsls r2, r3, #16
8001af6: 687b ldr r3, [r7, #4]
8001af8: 619a str r2, [r3, #24]
}
8001afa: bf00 nop
8001afc: 370c adds r7, #12
8001afe: 46bd mov sp, r7
8001b00: f85d 7b04 ldr.w r7, [sp], #4
8001b04: 4770 bx lr
08001b06 <HAL_HCD_Init>:
* @brief Initialize the host driver.
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
8001b06: b5f0 push {r4, r5, r6, r7, lr}
8001b08: b08f sub sp, #60 ; 0x3c
8001b0a: af0a add r7, sp, #40 ; 0x28
8001b0c: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx;
/* Check the HCD handle allocation */
if (hhcd == NULL)
8001b0e: 687b ldr r3, [r7, #4]
8001b10: 2b00 cmp r3, #0
8001b12: d101 bne.n 8001b18 <HAL_HCD_Init+0x12>
{
return HAL_ERROR;
8001b14: 2301 movs r3, #1
8001b16: e054 b.n 8001bc2 <HAL_HCD_Init+0xbc>
}
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
USBx = hhcd->Instance;
8001b18: 687b ldr r3, [r7, #4]
8001b1a: 681b ldr r3, [r3, #0]
8001b1c: 60fb str r3, [r7, #12]
if (hhcd->State == HAL_HCD_STATE_RESET)
8001b1e: 687b ldr r3, [r7, #4]
8001b20: f893 32f9 ldrb.w r3, [r3, #761] ; 0x2f9
8001b24: b2db uxtb r3, r3
8001b26: 2b00 cmp r3, #0
8001b28: d106 bne.n 8001b38 <HAL_HCD_Init+0x32>
{
/* Allocate lock resource and initialize it */
hhcd->Lock = HAL_UNLOCKED;
8001b2a: 687b ldr r3, [r7, #4]
8001b2c: 2200 movs r2, #0
8001b2e: f883 22f8 strb.w r2, [r3, #760] ; 0x2f8
/* Init the low level hardware */
hhcd->MspInitCallback(hhcd);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd);
8001b32: 6878 ldr r0, [r7, #4]
8001b34: f7ff f900 bl 8000d38 <HAL_HCD_MspInit>
#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
}
hhcd->State = HAL_HCD_STATE_BUSY;
8001b38: 687b ldr r3, [r7, #4]
8001b3a: 2203 movs r2, #3
8001b3c: f883 22f9 strb.w r2, [r3, #761] ; 0x2f9
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
8001b40: 68fb ldr r3, [r7, #12]
8001b42: 6bdb ldr r3, [r3, #60] ; 0x3c
8001b44: f403 7380 and.w r3, r3, #256 ; 0x100
8001b48: 2b00 cmp r3, #0
8001b4a: d102 bne.n 8001b52 <HAL_HCD_Init+0x4c>
{
hhcd->Init.dma_enable = 0U;
8001b4c: 687b ldr r3, [r7, #4]
8001b4e: 2200 movs r2, #0
8001b50: 611a str r2, [r3, #16]
}
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
8001b52: 687b ldr r3, [r7, #4]
8001b54: 681b ldr r3, [r3, #0]
8001b56: 4618 mov r0, r3
8001b58: f003 fb69 bl 800522e <USB_DisableGlobalInt>
/* Init the Core (common init.) */
(void)USB_CoreInit(hhcd->Instance, hhcd->Init);
8001b5c: 687b ldr r3, [r7, #4]
8001b5e: 681b ldr r3, [r3, #0]
8001b60: 603b str r3, [r7, #0]
8001b62: 687e ldr r6, [r7, #4]
8001b64: 466d mov r5, sp
8001b66: f106 0410 add.w r4, r6, #16
8001b6a: cc0f ldmia r4!, {r0, r1, r2, r3}
8001b6c: c50f stmia r5!, {r0, r1, r2, r3}
8001b6e: cc0f ldmia r4!, {r0, r1, r2, r3}
8001b70: c50f stmia r5!, {r0, r1, r2, r3}
8001b72: e894 0003 ldmia.w r4, {r0, r1}
8001b76: e885 0003 stmia.w r5, {r0, r1}
8001b7a: 1d33 adds r3, r6, #4
8001b7c: cb0e ldmia r3, {r1, r2, r3}
8001b7e: 6838 ldr r0, [r7, #0]
8001b80: f003 faf4 bl 800516c <USB_CoreInit>
/* Force Host Mode*/
(void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
8001b84: 687b ldr r3, [r7, #4]
8001b86: 681b ldr r3, [r3, #0]
8001b88: 2101 movs r1, #1
8001b8a: 4618 mov r0, r3
8001b8c: f003 fb60 bl 8005250 <USB_SetCurrentMode>
/* Init Host */
(void)USB_HostInit(hhcd->Instance, hhcd->Init);
8001b90: 687b ldr r3, [r7, #4]
8001b92: 681b ldr r3, [r3, #0]
8001b94: 603b str r3, [r7, #0]
8001b96: 687e ldr r6, [r7, #4]
8001b98: 466d mov r5, sp
8001b9a: f106 0410 add.w r4, r6, #16
8001b9e: cc0f ldmia r4!, {r0, r1, r2, r3}
8001ba0: c50f stmia r5!, {r0, r1, r2, r3}
8001ba2: cc0f ldmia r4!, {r0, r1, r2, r3}
8001ba4: c50f stmia r5!, {r0, r1, r2, r3}
8001ba6: e894 0003 ldmia.w r4, {r0, r1}
8001baa: e885 0003 stmia.w r5, {r0, r1}
8001bae: 1d33 adds r3, r6, #4
8001bb0: cb0e ldmia r3, {r1, r2, r3}
8001bb2: 6838 ldr r0, [r7, #0]
8001bb4: f003 fbf2 bl 800539c <USB_HostInit>
hhcd->State = HAL_HCD_STATE_READY;
8001bb8: 687b ldr r3, [r7, #4]
8001bba: 2201 movs r2, #1
8001bbc: f883 22f9 strb.w r2, [r3, #761] ; 0x2f9
return HAL_OK;
8001bc0: 2300 movs r3, #0
}
8001bc2: 4618 mov r0, r3
8001bc4: 3714 adds r7, #20
8001bc6: 46bd mov sp, r7
8001bc8: bdf0 pop {r4, r5, r6, r7, pc}
...
08001bcc <HAL_I2S_Init>:
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
8001bcc: b580 push {r7, lr}
8001bce: b088 sub sp, #32
8001bd0: af00 add r7, sp, #0
8001bd2: 6078 str r0, [r7, #4]
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
uint16_t tmpreg;
#endif
/* Check the I2S handle allocation */
if (hi2s == NULL)
8001bd4: 687b ldr r3, [r7, #4]
8001bd6: 2b00 cmp r3, #0
8001bd8: d101 bne.n 8001bde <HAL_I2S_Init+0x12>
{
return HAL_ERROR;
8001bda: 2301 movs r3, #1
8001bdc: e128 b.n 8001e30 <HAL_I2S_Init+0x264>
assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
if (hi2s->State == HAL_I2S_STATE_RESET)
8001bde: 687b ldr r3, [r7, #4]
8001be0: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8001be4: b2db uxtb r3, r3
8001be6: 2b00 cmp r3, #0
8001be8: d109 bne.n 8001bfe <HAL_I2S_Init+0x32>
{
/* Allocate lock resource and initialize it */
hi2s->Lock = HAL_UNLOCKED;
8001bea: 687b ldr r3, [r7, #4]
8001bec: 2200 movs r2, #0
8001bee: f883 2040 strb.w r2, [r3, #64] ; 0x40
/* Initialize Default I2S IrqHandler ISR */
hi2s->IrqHandlerISR = I2S_IRQHandler;
8001bf2: 687b ldr r3, [r7, #4]
8001bf4: 4a90 ldr r2, [pc, #576] ; (8001e38 <HAL_I2S_Init+0x26c>)
8001bf6: 635a str r2, [r3, #52] ; 0x34
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hi2s->MspInitCallback(hi2s);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
8001bf8: 6878 ldr r0, [r7, #4]
8001bfa: f7fe fedf bl 80009bc <HAL_I2S_MspInit>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
hi2s->State = HAL_I2S_STATE_BUSY;
8001bfe: 687b ldr r3, [r7, #4]
8001c00: 2202 movs r2, #2
8001c02: f883 2041 strb.w r2, [r3, #65] ; 0x41
/*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
8001c06: 687b ldr r3, [r7, #4]
8001c08: 681b ldr r3, [r3, #0]
8001c0a: 69db ldr r3, [r3, #28]
8001c0c: 687a ldr r2, [r7, #4]
8001c0e: 6812 ldr r2, [r2, #0]
8001c10: f423 637b bic.w r3, r3, #4016 ; 0xfb0
8001c14: f023 030f bic.w r3, r3, #15
8001c18: 61d3 str r3, [r2, #28]
SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
hi2s->Instance->I2SPR = 0x0002U;
8001c1a: 687b ldr r3, [r7, #4]
8001c1c: 681b ldr r3, [r3, #0]
8001c1e: 2202 movs r2, #2
8001c20: 621a str r2, [r3, #32]
/*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
/* If the requested audio frequency is not the default, compute the prescaler */
if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
8001c22: 687b ldr r3, [r7, #4]
8001c24: 695b ldr r3, [r3, #20]
8001c26: 2b02 cmp r3, #2
8001c28: d060 beq.n 8001cec <HAL_I2S_Init+0x120>
{
/* Check the frame length (For the Prescaler computing) ********************/
if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
8001c2a: 687b ldr r3, [r7, #4]
8001c2c: 68db ldr r3, [r3, #12]
8001c2e: 2b00 cmp r3, #0
8001c30: d102 bne.n 8001c38 <HAL_I2S_Init+0x6c>
{
/* Packet length is 16 bits */
packetlength = 16U;
8001c32: 2310 movs r3, #16
8001c34: 617b str r3, [r7, #20]
8001c36: e001 b.n 8001c3c <HAL_I2S_Init+0x70>
}
else
{
/* Packet length is 32 bits */
packetlength = 32U;
8001c38: 2320 movs r3, #32
8001c3a: 617b str r3, [r7, #20]
}
/* I2S standard */
if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
8001c3c: 687b ldr r3, [r7, #4]
8001c3e: 689b ldr r3, [r3, #8]
8001c40: 2b20 cmp r3, #32
8001c42: d802 bhi.n 8001c4a <HAL_I2S_Init+0x7e>
{
/* In I2S standard packet length is multiplied by 2 */
packetlength = packetlength * 2U;
8001c44: 697b ldr r3, [r7, #20]
8001c46: 005b lsls r3, r3, #1
8001c48: 617b str r3, [r7, #20]
else
{
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2);
}
#else
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
8001c4a: 2001 movs r0, #1
8001c4c: f001 f996 bl 8002f7c <HAL_RCCEx_GetPeriphCLKFreq>
8001c50: 60f8 str r0, [r7, #12]
#endif
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
8001c52: 687b ldr r3, [r7, #4]
8001c54: 691b ldr r3, [r3, #16]
8001c56: f5b3 7f00 cmp.w r3, #512 ; 0x200
8001c5a: d125 bne.n 8001ca8 <HAL_I2S_Init+0xdc>
{
/* MCLK output is enabled */
if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
8001c5c: 687b ldr r3, [r7, #4]
8001c5e: 68db ldr r3, [r3, #12]
8001c60: 2b00 cmp r3, #0
8001c62: d010 beq.n 8001c86 <HAL_I2S_Init+0xba>
{
tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
8001c64: 697b ldr r3, [r7, #20]
8001c66: 009b lsls r3, r3, #2
8001c68: 68fa ldr r2, [r7, #12]
8001c6a: fbb2 f2f3 udiv r2, r2, r3
8001c6e: 4613 mov r3, r2
8001c70: 009b lsls r3, r3, #2
8001c72: 4413 add r3, r2
8001c74: 005b lsls r3, r3, #1
8001c76: 461a mov r2, r3
8001c78: 687b ldr r3, [r7, #4]
8001c7a: 695b ldr r3, [r3, #20]
8001c7c: fbb2 f3f3 udiv r3, r2, r3
8001c80: 3305 adds r3, #5
8001c82: 613b str r3, [r7, #16]
8001c84: e01f b.n 8001cc6 <HAL_I2S_Init+0xfa>
}
else
{
tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
8001c86: 697b ldr r3, [r7, #20]
8001c88: 00db lsls r3, r3, #3
8001c8a: 68fa ldr r2, [r7, #12]
8001c8c: fbb2 f2f3 udiv r2, r2, r3
8001c90: 4613 mov r3, r2
8001c92: 009b lsls r3, r3, #2
8001c94: 4413 add r3, r2
8001c96: 005b lsls r3, r3, #1
8001c98: 461a mov r2, r3
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 695b ldr r3, [r3, #20]
8001c9e: fbb2 f3f3 udiv r3, r2, r3
8001ca2: 3305 adds r3, #5
8001ca4: 613b str r3, [r7, #16]
8001ca6: e00e b.n 8001cc6 <HAL_I2S_Init+0xfa>
}
}
else
{
/* MCLK output is disabled */
tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
8001ca8: 68fa ldr r2, [r7, #12]
8001caa: 697b ldr r3, [r7, #20]
8001cac: fbb2 f2f3 udiv r2, r2, r3
8001cb0: 4613 mov r3, r2
8001cb2: 009b lsls r3, r3, #2
8001cb4: 4413 add r3, r2
8001cb6: 005b lsls r3, r3, #1
8001cb8: 461a mov r2, r3
8001cba: 687b ldr r3, [r7, #4]
8001cbc: 695b ldr r3, [r3, #20]
8001cbe: fbb2 f3f3 udiv r3, r2, r3
8001cc2: 3305 adds r3, #5
8001cc4: 613b str r3, [r7, #16]
}
/* Remove the flatting point */
tmp = tmp / 10U;
8001cc6: 693b ldr r3, [r7, #16]
8001cc8: 4a5c ldr r2, [pc, #368] ; (8001e3c <HAL_I2S_Init+0x270>)
8001cca: fba2 2303 umull r2, r3, r2, r3
8001cce: 08db lsrs r3, r3, #3
8001cd0: 613b str r3, [r7, #16]
/* Check the parity of the divider */
i2sodd = (uint32_t)(tmp & (uint32_t)1U);
8001cd2: 693b ldr r3, [r7, #16]
8001cd4: f003 0301 and.w r3, r3, #1
8001cd8: 61bb str r3, [r7, #24]
/* Compute the i2sdiv prescaler */
i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
8001cda: 693a ldr r2, [r7, #16]
8001cdc: 69bb ldr r3, [r7, #24]
8001cde: 1ad3 subs r3, r2, r3
8001ce0: 085b lsrs r3, r3, #1
8001ce2: 61fb str r3, [r7, #28]
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (uint32_t)(i2sodd << 8U);
8001ce4: 69bb ldr r3, [r7, #24]
8001ce6: 021b lsls r3, r3, #8
8001ce8: 61bb str r3, [r7, #24]
8001cea: e003 b.n 8001cf4 <HAL_I2S_Init+0x128>
}
else
{
/* Set the default values */
i2sdiv = 2U;
8001cec: 2302 movs r3, #2
8001cee: 61fb str r3, [r7, #28]
i2sodd = 0U;
8001cf0: 2300 movs r3, #0
8001cf2: 61bb str r3, [r7, #24]
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
8001cf4: 69fb ldr r3, [r7, #28]
8001cf6: 2b01 cmp r3, #1
8001cf8: d902 bls.n 8001d00 <HAL_I2S_Init+0x134>
8001cfa: 69fb ldr r3, [r7, #28]
8001cfc: 2bff cmp r3, #255 ; 0xff
8001cfe: d907 bls.n 8001d10 <HAL_I2S_Init+0x144>
{
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
8001d00: 687b ldr r3, [r7, #4]
8001d02: 6c5b ldr r3, [r3, #68] ; 0x44
8001d04: f043 0210 orr.w r2, r3, #16
8001d08: 687b ldr r3, [r7, #4]
8001d0a: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
8001d0c: 2301 movs r3, #1
8001d0e: e08f b.n 8001e30 <HAL_I2S_Init+0x264>
}
/*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Write to SPIx I2SPR register the computed value */
hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
8001d10: 687b ldr r3, [r7, #4]
8001d12: 691a ldr r2, [r3, #16]
8001d14: 69bb ldr r3, [r7, #24]
8001d16: ea42 0103 orr.w r1, r2, r3
8001d1a: 687b ldr r3, [r7, #4]
8001d1c: 681b ldr r3, [r3, #0]
8001d1e: 69fa ldr r2, [r7, #28]
8001d20: 430a orrs r2, r1
8001d22: 621a str r2, [r3, #32]
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
/* And configure the I2S with the I2S_InitStruct values */
MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
8001d24: 687b ldr r3, [r7, #4]
8001d26: 681b ldr r3, [r3, #0]
8001d28: 69db ldr r3, [r3, #28]
8001d2a: f423 637b bic.w r3, r3, #4016 ; 0xfb0
8001d2e: f023 030f bic.w r3, r3, #15
8001d32: 687a ldr r2, [r7, #4]
8001d34: 6851 ldr r1, [r2, #4]
8001d36: 687a ldr r2, [r7, #4]
8001d38: 6892 ldr r2, [r2, #8]
8001d3a: 4311 orrs r1, r2
8001d3c: 687a ldr r2, [r7, #4]
8001d3e: 68d2 ldr r2, [r2, #12]
8001d40: 4311 orrs r1, r2
8001d42: 687a ldr r2, [r7, #4]
8001d44: 6992 ldr r2, [r2, #24]
8001d46: 430a orrs r2, r1
8001d48: 431a orrs r2, r3
8001d4a: 687b ldr r3, [r7, #4]
8001d4c: 681b ldr r3, [r3, #0]
8001d4e: f442 6200 orr.w r2, r2, #2048 ; 0x800
8001d52: 61da str r2, [r3, #28]
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
/* Configure the I2S extended if the full duplex mode is enabled */
assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
if (hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
8001d54: 687b ldr r3, [r7, #4]
8001d56: 6a1b ldr r3, [r3, #32]
8001d58: 2b01 cmp r3, #1
8001d5a: d161 bne.n 8001e20 <HAL_I2S_Init+0x254>
{
/* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */
hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler;
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 4a38 ldr r2, [pc, #224] ; (8001e40 <HAL_I2S_Init+0x274>)
8001d60: 635a str r2, [r3, #52] ; 0x34
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
8001d62: 687b ldr r3, [r7, #4]
8001d64: 681b ldr r3, [r3, #0]
8001d66: 4a37 ldr r2, [pc, #220] ; (8001e44 <HAL_I2S_Init+0x278>)
8001d68: 4293 cmp r3, r2
8001d6a: d101 bne.n 8001d70 <HAL_I2S_Init+0x1a4>
8001d6c: 4b36 ldr r3, [pc, #216] ; (8001e48 <HAL_I2S_Init+0x27c>)
8001d6e: e001 b.n 8001d74 <HAL_I2S_Init+0x1a8>
8001d70: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
8001d74: 69db ldr r3, [r3, #28]
8001d76: 687a ldr r2, [r7, #4]
8001d78: 6812 ldr r2, [r2, #0]
8001d7a: 4932 ldr r1, [pc, #200] ; (8001e44 <HAL_I2S_Init+0x278>)
8001d7c: 428a cmp r2, r1
8001d7e: d101 bne.n 8001d84 <HAL_I2S_Init+0x1b8>
8001d80: 4a31 ldr r2, [pc, #196] ; (8001e48 <HAL_I2S_Init+0x27c>)
8001d82: e001 b.n 8001d88 <HAL_I2S_Init+0x1bc>
8001d84: f04f 2240 mov.w r2, #1073758208 ; 0x40004000
8001d88: f423 637b bic.w r3, r3, #4016 ; 0xfb0
8001d8c: f023 030f bic.w r3, r3, #15
8001d90: 61d3 str r3, [r2, #28]
SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
I2SxEXT(hi2s->Instance)->I2SPR = 2U;
8001d92: 687b ldr r3, [r7, #4]
8001d94: 681b ldr r3, [r3, #0]
8001d96: 4a2b ldr r2, [pc, #172] ; (8001e44 <HAL_I2S_Init+0x278>)
8001d98: 4293 cmp r3, r2
8001d9a: d101 bne.n 8001da0 <HAL_I2S_Init+0x1d4>
8001d9c: 4b2a ldr r3, [pc, #168] ; (8001e48 <HAL_I2S_Init+0x27c>)
8001d9e: e001 b.n 8001da4 <HAL_I2S_Init+0x1d8>
8001da0: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
8001da4: 2202 movs r2, #2
8001da6: 621a str r2, [r3, #32]
/* Get the I2SCFGR register value */
tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
8001da8: 687b ldr r3, [r7, #4]
8001daa: 681b ldr r3, [r3, #0]
8001dac: 4a25 ldr r2, [pc, #148] ; (8001e44 <HAL_I2S_Init+0x278>)
8001dae: 4293 cmp r3, r2
8001db0: d101 bne.n 8001db6 <HAL_I2S_Init+0x1ea>
8001db2: 4b25 ldr r3, [pc, #148] ; (8001e48 <HAL_I2S_Init+0x27c>)
8001db4: e001 b.n 8001dba <HAL_I2S_Init+0x1ee>
8001db6: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
8001dba: 69db ldr r3, [r3, #28]
8001dbc: 817b strh r3, [r7, #10]
/* Get the mode to be configured for the extended I2S */
if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
8001dbe: 687b ldr r3, [r7, #4]
8001dc0: 685b ldr r3, [r3, #4]
8001dc2: f5b3 7f00 cmp.w r3, #512 ; 0x200
8001dc6: d003 beq.n 8001dd0 <HAL_I2S_Init+0x204>
8001dc8: 687b ldr r3, [r7, #4]
8001dca: 685b ldr r3, [r3, #4]
8001dcc: 2b00 cmp r3, #0
8001dce: d103 bne.n 8001dd8 <HAL_I2S_Init+0x20c>
{
tmp = I2S_MODE_SLAVE_RX;
8001dd0: f44f 7380 mov.w r3, #256 ; 0x100
8001dd4: 613b str r3, [r7, #16]
8001dd6: e001 b.n 8001ddc <HAL_I2S_Init+0x210>
}
else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */
{
tmp = I2S_MODE_SLAVE_TX;
8001dd8: 2300 movs r3, #0
8001dda: 613b str r3, [r7, #16]
}
/* Configure the I2S Slave with the I2S Master parameter values */
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
(uint16_t)tmp | \
8001ddc: 693b ldr r3, [r7, #16]
8001dde: b29a uxth r2, r3
(uint16_t)hi2s->Init.Standard | \
8001de0: 687b ldr r3, [r7, #4]
8001de2: 689b ldr r3, [r3, #8]
8001de4: b29b uxth r3, r3
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
8001de6: 4313 orrs r3, r2
8001de8: b29a uxth r2, r3
(uint16_t)hi2s->Init.DataFormat | \
8001dea: 687b ldr r3, [r7, #4]
8001dec: 68db ldr r3, [r3, #12]
8001dee: b29b uxth r3, r3
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
8001df0: 4313 orrs r3, r2
8001df2: b29a uxth r2, r3
(uint16_t)hi2s->Init.CPOL);
8001df4: 687b ldr r3, [r7, #4]
8001df6: 699b ldr r3, [r3, #24]
8001df8: b29b uxth r3, r3
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
8001dfa: 4313 orrs r3, r2
8001dfc: b29a uxth r2, r3
8001dfe: 897b ldrh r3, [r7, #10]
8001e00: 4313 orrs r3, r2
8001e02: b29b uxth r3, r3
8001e04: f443 6300 orr.w r3, r3, #2048 ; 0x800
8001e08: 817b strh r3, [r7, #10]
/* Write to SPIx I2SCFGR */
WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg);
8001e0a: 687b ldr r3, [r7, #4]
8001e0c: 681b ldr r3, [r3, #0]
8001e0e: 4a0d ldr r2, [pc, #52] ; (8001e44 <HAL_I2S_Init+0x278>)
8001e10: 4293 cmp r3, r2
8001e12: d101 bne.n 8001e18 <HAL_I2S_Init+0x24c>
8001e14: 4b0c ldr r3, [pc, #48] ; (8001e48 <HAL_I2S_Init+0x27c>)
8001e16: e001 b.n 8001e1c <HAL_I2S_Init+0x250>
8001e18: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
8001e1c: 897a ldrh r2, [r7, #10]
8001e1e: 61da str r2, [r3, #28]
}
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
8001e20: 687b ldr r3, [r7, #4]
8001e22: 2200 movs r2, #0
8001e24: 645a str r2, [r3, #68] ; 0x44
hi2s->State = HAL_I2S_STATE_READY;
8001e26: 687b ldr r3, [r7, #4]
8001e28: 2201 movs r2, #1
8001e2a: f883 2041 strb.w r2, [r3, #65] ; 0x41
return HAL_OK;
8001e2e: 2300 movs r3, #0
}
8001e30: 4618 mov r0, r3
8001e32: 3720 adds r7, #32
8001e34: 46bd mov sp, r7
8001e36: bd80 pop {r7, pc}
8001e38: 08001f43 .word 0x08001f43
8001e3c: cccccccd .word 0xcccccccd
8001e40: 08002059 .word 0x08002059
8001e44: 40003800 .word 0x40003800
8001e48: 40003400 .word 0x40003400
08001e4c <HAL_I2S_TxCpltCallback>:
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
8001e4c: b480 push {r7}
8001e4e: b083 sub sp, #12
8001e50: af00 add r7, sp, #0
8001e52: 6078 str r0, [r7, #4]
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
*/
}
8001e54: bf00 nop
8001e56: 370c adds r7, #12
8001e58: 46bd mov sp, r7
8001e5a: f85d 7b04 ldr.w r7, [sp], #4
8001e5e: 4770 bx lr
08001e60 <HAL_I2S_RxCpltCallback>:
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
8001e60: b480 push {r7}
8001e62: b083 sub sp, #12
8001e64: af00 add r7, sp, #0
8001e66: 6078 str r0, [r7, #4]
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implemented in the user file
*/
}
8001e68: bf00 nop
8001e6a: 370c adds r7, #12
8001e6c: 46bd mov sp, r7
8001e6e: f85d 7b04 ldr.w r7, [sp], #4
8001e72: 4770 bx lr
08001e74 <HAL_I2S_ErrorCallback>:
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
8001e74: b480 push {r7}
8001e76: b083 sub sp, #12
8001e78: af00 add r7, sp, #0
8001e7a: 6078 str r0, [r7, #4]
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
*/
}
8001e7c: bf00 nop
8001e7e: 370c adds r7, #12
8001e80: 46bd mov sp, r7
8001e82: f85d 7b04 ldr.w r7, [sp], #4
8001e86: 4770 bx lr
08001e88 <I2S_Transmit_IT>:
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
8001e88: b580 push {r7, lr}
8001e8a: b082 sub sp, #8
8001e8c: af00 add r7, sp, #0
8001e8e: 6078 str r0, [r7, #4]
/* Transmit data */
hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
8001e90: 687b ldr r3, [r7, #4]
8001e92: 6a5b ldr r3, [r3, #36] ; 0x24
8001e94: 881a ldrh r2, [r3, #0]
8001e96: 687b ldr r3, [r7, #4]
8001e98: 681b ldr r3, [r3, #0]
8001e9a: 60da str r2, [r3, #12]
hi2s->pTxBuffPtr++;
8001e9c: 687b ldr r3, [r7, #4]
8001e9e: 6a5b ldr r3, [r3, #36] ; 0x24
8001ea0: 1c9a adds r2, r3, #2
8001ea2: 687b ldr r3, [r7, #4]
8001ea4: 625a str r2, [r3, #36] ; 0x24
hi2s->TxXferCount--;
8001ea6: 687b ldr r3, [r7, #4]
8001ea8: 8d5b ldrh r3, [r3, #42] ; 0x2a
8001eaa: b29b uxth r3, r3
8001eac: 3b01 subs r3, #1
8001eae: b29a uxth r2, r3
8001eb0: 687b ldr r3, [r7, #4]
8001eb2: 855a strh r2, [r3, #42] ; 0x2a
if (hi2s->TxXferCount == 0U)
8001eb4: 687b ldr r3, [r7, #4]
8001eb6: 8d5b ldrh r3, [r3, #42] ; 0x2a
8001eb8: b29b uxth r3, r3
8001eba: 2b00 cmp r3, #0
8001ebc: d10e bne.n 8001edc <I2S_Transmit_IT+0x54>
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
8001ebe: 687b ldr r3, [r7, #4]
8001ec0: 681b ldr r3, [r3, #0]
8001ec2: 685a ldr r2, [r3, #4]
8001ec4: 687b ldr r3, [r7, #4]
8001ec6: 681b ldr r3, [r3, #0]
8001ec8: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8001ecc: 605a str r2, [r3, #4]
hi2s->State = HAL_I2S_STATE_READY;
8001ece: 687b ldr r3, [r7, #4]
8001ed0: 2201 movs r2, #1
8001ed2: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Call user Tx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxCpltCallback(hi2s);
#else
HAL_I2S_TxCpltCallback(hi2s);
8001ed6: 6878 ldr r0, [r7, #4]
8001ed8: f7ff ffb8 bl 8001e4c <HAL_I2S_TxCpltCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
8001edc: bf00 nop
8001ede: 3708 adds r7, #8
8001ee0: 46bd mov sp, r7
8001ee2: bd80 pop {r7, pc}
08001ee4 <I2S_Receive_IT>:
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
8001ee4: b580 push {r7, lr}
8001ee6: b082 sub sp, #8
8001ee8: af00 add r7, sp, #0
8001eea: 6078 str r0, [r7, #4]
/* Receive data */
(*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
8001eec: 687b ldr r3, [r7, #4]
8001eee: 681b ldr r3, [r3, #0]
8001ef0: 68da ldr r2, [r3, #12]
8001ef2: 687b ldr r3, [r7, #4]
8001ef4: 6adb ldr r3, [r3, #44] ; 0x2c
8001ef6: b292 uxth r2, r2
8001ef8: 801a strh r2, [r3, #0]
hi2s->pRxBuffPtr++;
8001efa: 687b ldr r3, [r7, #4]
8001efc: 6adb ldr r3, [r3, #44] ; 0x2c
8001efe: 1c9a adds r2, r3, #2
8001f00: 687b ldr r3, [r7, #4]
8001f02: 62da str r2, [r3, #44] ; 0x2c
hi2s->RxXferCount--;
8001f04: 687b ldr r3, [r7, #4]
8001f06: 8e5b ldrh r3, [r3, #50] ; 0x32
8001f08: b29b uxth r3, r3
8001f0a: 3b01 subs r3, #1
8001f0c: b29a uxth r2, r3
8001f0e: 687b ldr r3, [r7, #4]
8001f10: 865a strh r2, [r3, #50] ; 0x32
if (hi2s->RxXferCount == 0U)
8001f12: 687b ldr r3, [r7, #4]
8001f14: 8e5b ldrh r3, [r3, #50] ; 0x32
8001f16: b29b uxth r3, r3
8001f18: 2b00 cmp r3, #0
8001f1a: d10e bne.n 8001f3a <I2S_Receive_IT+0x56>
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
8001f1c: 687b ldr r3, [r7, #4]
8001f1e: 681b ldr r3, [r3, #0]
8001f20: 685a ldr r2, [r3, #4]
8001f22: 687b ldr r3, [r7, #4]
8001f24: 681b ldr r3, [r3, #0]
8001f26: f022 0260 bic.w r2, r2, #96 ; 0x60
8001f2a: 605a str r2, [r3, #4]
hi2s->State = HAL_I2S_STATE_READY;
8001f2c: 687b ldr r3, [r7, #4]
8001f2e: 2201 movs r2, #1
8001f30: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Call user Rx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->RxCpltCallback(hi2s);
#else
HAL_I2S_RxCpltCallback(hi2s);
8001f34: 6878 ldr r0, [r7, #4]
8001f36: f7ff ff93 bl 8001e60 <HAL_I2S_RxCpltCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
8001f3a: bf00 nop
8001f3c: 3708 adds r7, #8
8001f3e: 46bd mov sp, r7
8001f40: bd80 pop {r7, pc}
08001f42 <I2S_IRQHandler>:
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
8001f42: b580 push {r7, lr}
8001f44: b086 sub sp, #24
8001f46: af00 add r7, sp, #0
8001f48: 6078 str r0, [r7, #4]
__IO uint32_t i2ssr = hi2s->Instance->SR;
8001f4a: 687b ldr r3, [r7, #4]
8001f4c: 681b ldr r3, [r3, #0]
8001f4e: 689b ldr r3, [r3, #8]
8001f50: 617b str r3, [r7, #20]
if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
8001f52: 687b ldr r3, [r7, #4]
8001f54: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8001f58: b2db uxtb r3, r3
8001f5a: 2b04 cmp r3, #4
8001f5c: d13a bne.n 8001fd4 <I2S_IRQHandler+0x92>
{
/* I2S in mode Receiver ------------------------------------------------*/
if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
8001f5e: 697b ldr r3, [r7, #20]
8001f60: f003 0301 and.w r3, r3, #1
8001f64: 2b01 cmp r3, #1
8001f66: d109 bne.n 8001f7c <I2S_IRQHandler+0x3a>
8001f68: 687b ldr r3, [r7, #4]
8001f6a: 681b ldr r3, [r3, #0]
8001f6c: 685b ldr r3, [r3, #4]
8001f6e: f003 0340 and.w r3, r3, #64 ; 0x40
8001f72: 2b40 cmp r3, #64 ; 0x40
8001f74: d102 bne.n 8001f7c <I2S_IRQHandler+0x3a>
{
I2S_Receive_IT(hi2s);
8001f76: 6878 ldr r0, [r7, #4]
8001f78: f7ff ffb4 bl 8001ee4 <I2S_Receive_IT>
}
/* I2S Overrun error interrupt occurred -------------------------------------*/
if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
8001f7c: 697b ldr r3, [r7, #20]
8001f7e: f003 0340 and.w r3, r3, #64 ; 0x40
8001f82: 2b40 cmp r3, #64 ; 0x40
8001f84: d126 bne.n 8001fd4 <I2S_IRQHandler+0x92>
8001f86: 687b ldr r3, [r7, #4]
8001f88: 681b ldr r3, [r3, #0]
8001f8a: 685b ldr r3, [r3, #4]
8001f8c: f003 0320 and.w r3, r3, #32
8001f90: 2b20 cmp r3, #32
8001f92: d11f bne.n 8001fd4 <I2S_IRQHandler+0x92>
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
8001f94: 687b ldr r3, [r7, #4]
8001f96: 681b ldr r3, [r3, #0]
8001f98: 685a ldr r2, [r3, #4]
8001f9a: 687b ldr r3, [r7, #4]
8001f9c: 681b ldr r3, [r3, #0]
8001f9e: f022 0260 bic.w r2, r2, #96 ; 0x60
8001fa2: 605a str r2, [r3, #4]
/* Clear Overrun flag */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
8001fa4: 2300 movs r3, #0
8001fa6: 613b str r3, [r7, #16]
8001fa8: 687b ldr r3, [r7, #4]
8001faa: 681b ldr r3, [r3, #0]
8001fac: 68db ldr r3, [r3, #12]
8001fae: 613b str r3, [r7, #16]
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 681b ldr r3, [r3, #0]
8001fb4: 689b ldr r3, [r3, #8]
8001fb6: 613b str r3, [r7, #16]
8001fb8: 693b ldr r3, [r7, #16]
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
8001fba: 687b ldr r3, [r7, #4]
8001fbc: 2201 movs r2, #1
8001fbe: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
8001fc2: 687b ldr r3, [r7, #4]
8001fc4: 6c5b ldr r3, [r3, #68] ; 0x44
8001fc6: f043 0202 orr.w r2, r3, #2
8001fca: 687b ldr r3, [r7, #4]
8001fcc: 645a str r2, [r3, #68] ; 0x44
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
8001fce: 6878 ldr r0, [r7, #4]
8001fd0: f7ff ff50 bl 8001e74 <HAL_I2S_ErrorCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
8001fd4: 687b ldr r3, [r7, #4]
8001fd6: f893 3041 ldrb.w r3, [r3, #65] ; 0x41
8001fda: b2db uxtb r3, r3
8001fdc: 2b03 cmp r3, #3
8001fde: d136 bne.n 800204e <I2S_IRQHandler+0x10c>
{
/* I2S in mode Transmitter -----------------------------------------------*/
if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
8001fe0: 697b ldr r3, [r7, #20]
8001fe2: f003 0302 and.w r3, r3, #2
8001fe6: 2b02 cmp r3, #2
8001fe8: d109 bne.n 8001ffe <I2S_IRQHandler+0xbc>
8001fea: 687b ldr r3, [r7, #4]
8001fec: 681b ldr r3, [r3, #0]
8001fee: 685b ldr r3, [r3, #4]
8001ff0: f003 0380 and.w r3, r3, #128 ; 0x80
8001ff4: 2b80 cmp r3, #128 ; 0x80
8001ff6: d102 bne.n 8001ffe <I2S_IRQHandler+0xbc>
{
I2S_Transmit_IT(hi2s);
8001ff8: 6878 ldr r0, [r7, #4]
8001ffa: f7ff ff45 bl 8001e88 <I2S_Transmit_IT>
}
/* I2S Underrun error interrupt occurred --------------------------------*/
if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
8001ffe: 697b ldr r3, [r7, #20]
8002000: f003 0308 and.w r3, r3, #8
8002004: 2b08 cmp r3, #8
8002006: d122 bne.n 800204e <I2S_IRQHandler+0x10c>
8002008: 687b ldr r3, [r7, #4]
800200a: 681b ldr r3, [r3, #0]
800200c: 685b ldr r3, [r3, #4]
800200e: f003 0320 and.w r3, r3, #32
8002012: 2b20 cmp r3, #32
8002014: d11b bne.n 800204e <I2S_IRQHandler+0x10c>
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
8002016: 687b ldr r3, [r7, #4]
8002018: 681b ldr r3, [r3, #0]
800201a: 685a ldr r2, [r3, #4]
800201c: 687b ldr r3, [r7, #4]
800201e: 681b ldr r3, [r3, #0]
8002020: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8002024: 605a str r2, [r3, #4]
/* Clear Underrun flag */
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
8002026: 2300 movs r3, #0
8002028: 60fb str r3, [r7, #12]
800202a: 687b ldr r3, [r7, #4]
800202c: 681b ldr r3, [r3, #0]
800202e: 689b ldr r3, [r3, #8]
8002030: 60fb str r3, [r7, #12]
8002032: 68fb ldr r3, [r7, #12]
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
8002034: 687b ldr r3, [r7, #4]
8002036: 2201 movs r2, #1
8002038: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
800203c: 687b ldr r3, [r7, #4]
800203e: 6c5b ldr r3, [r3, #68] ; 0x44
8002040: f043 0204 orr.w r2, r3, #4
8002044: 687b ldr r3, [r7, #4]
8002046: 645a str r2, [r3, #68] ; 0x44
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
8002048: 6878 ldr r0, [r7, #4]
800204a: f7ff ff13 bl 8001e74 <HAL_I2S_ErrorCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
800204e: bf00 nop
8002050: 3718 adds r7, #24
8002052: 46bd mov sp, r7
8002054: bd80 pop {r7, pc}
...
08002058 <HAL_I2SEx_FullDuplex_IRQHandler>:
* @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
* @param hi2s I2S handle
* @retval HAL status
*/
void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
{
8002058: b580 push {r7, lr}
800205a: b088 sub sp, #32
800205c: af00 add r7, sp, #0
800205e: 6078 str r0, [r7, #4]
__IO uint32_t i2ssr = hi2s->Instance->SR;
8002060: 687b ldr r3, [r7, #4]
8002062: 681b ldr r3, [r3, #0]
8002064: 689b ldr r3, [r3, #8]
8002066: 61fb str r3, [r7, #28]
__IO uint32_t i2sextsr = I2SxEXT(hi2s->Instance)->SR;
8002068: 687b ldr r3, [r7, #4]
800206a: 681b ldr r3, [r3, #0]
800206c: 4aa2 ldr r2, [pc, #648] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
800206e: 4293 cmp r3, r2
8002070: d101 bne.n 8002076 <HAL_I2SEx_FullDuplex_IRQHandler+0x1e>
8002072: 4ba2 ldr r3, [pc, #648] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
8002074: e001 b.n 800207a <HAL_I2SEx_FullDuplex_IRQHandler+0x22>
8002076: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
800207a: 689b ldr r3, [r3, #8]
800207c: 61bb str r3, [r7, #24]
__IO uint32_t i2scr2 = hi2s->Instance->CR2;
800207e: 687b ldr r3, [r7, #4]
8002080: 681b ldr r3, [r3, #0]
8002082: 685b ldr r3, [r3, #4]
8002084: 617b str r3, [r7, #20]
__IO uint32_t i2sextcr2 = I2SxEXT(hi2s->Instance)->CR2;
8002086: 687b ldr r3, [r7, #4]
8002088: 681b ldr r3, [r3, #0]
800208a: 4a9b ldr r2, [pc, #620] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
800208c: 4293 cmp r3, r2
800208e: d101 bne.n 8002094 <HAL_I2SEx_FullDuplex_IRQHandler+0x3c>
8002090: 4b9a ldr r3, [pc, #616] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
8002092: e001 b.n 8002098 <HAL_I2SEx_FullDuplex_IRQHandler+0x40>
8002094: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
8002098: 685b ldr r3, [r3, #4]
800209a: 613b str r3, [r7, #16]
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
800209c: 687b ldr r3, [r7, #4]
800209e: 685b ldr r3, [r3, #4]
80020a0: f5b3 7f00 cmp.w r3, #512 ; 0x200
80020a4: d004 beq.n 80020b0 <HAL_I2SEx_FullDuplex_IRQHandler+0x58>
80020a6: 687b ldr r3, [r7, #4]
80020a8: 685b ldr r3, [r3, #4]
80020aa: 2b00 cmp r3, #0
80020ac: f040 8099 bne.w 80021e2 <HAL_I2SEx_FullDuplex_IRQHandler+0x18a>
{
/* I2S in mode Transmitter -------------------------------------------------*/
if (((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2scr2 & I2S_IT_TXE) != RESET))
80020b0: 69fb ldr r3, [r7, #28]
80020b2: f003 0302 and.w r3, r3, #2
80020b6: 2b02 cmp r3, #2
80020b8: d107 bne.n 80020ca <HAL_I2SEx_FullDuplex_IRQHandler+0x72>
80020ba: 697b ldr r3, [r7, #20]
80020bc: f003 0380 and.w r3, r3, #128 ; 0x80
80020c0: 2b00 cmp r3, #0
80020c2: d002 beq.n 80020ca <HAL_I2SEx_FullDuplex_IRQHandler+0x72>
{
/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
I2SEx_TxISR_I2S(hi2s);
80020c4: 6878 ldr r0, [r7, #4]
80020c6: f000 f925 bl 8002314 <I2SEx_TxISR_I2S>
}
/* I2Sext in mode Receiver -----------------------------------------------*/
if (((i2sextsr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2sextcr2 & I2S_IT_RXNE) != RESET))
80020ca: 69bb ldr r3, [r7, #24]
80020cc: f003 0301 and.w r3, r3, #1
80020d0: 2b01 cmp r3, #1
80020d2: d107 bne.n 80020e4 <HAL_I2SEx_FullDuplex_IRQHandler+0x8c>
80020d4: 693b ldr r3, [r7, #16]
80020d6: f003 0340 and.w r3, r3, #64 ; 0x40
80020da: 2b00 cmp r3, #0
80020dc: d002 beq.n 80020e4 <HAL_I2SEx_FullDuplex_IRQHandler+0x8c>
{
/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
I2SEx_RxISR_I2SExt(hi2s);
80020de: 6878 ldr r0, [r7, #4]
80020e0: f000 f9c8 bl 8002474 <I2SEx_RxISR_I2SExt>
}
/* I2Sext Overrun error interrupt occurred --------------------------------*/
if (((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
80020e4: 69bb ldr r3, [r7, #24]
80020e6: f003 0340 and.w r3, r3, #64 ; 0x40
80020ea: 2b40 cmp r3, #64 ; 0x40
80020ec: d13a bne.n 8002164 <HAL_I2SEx_FullDuplex_IRQHandler+0x10c>
80020ee: 693b ldr r3, [r7, #16]
80020f0: f003 0320 and.w r3, r3, #32
80020f4: 2b00 cmp r3, #0
80020f6: d035 beq.n 8002164 <HAL_I2SEx_FullDuplex_IRQHandler+0x10c>
{
/* Disable RXNE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
80020f8: 687b ldr r3, [r7, #4]
80020fa: 681b ldr r3, [r3, #0]
80020fc: 4a7e ldr r2, [pc, #504] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
80020fe: 4293 cmp r3, r2
8002100: d101 bne.n 8002106 <HAL_I2SEx_FullDuplex_IRQHandler+0xae>
8002102: 4b7e ldr r3, [pc, #504] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
8002104: e001 b.n 800210a <HAL_I2SEx_FullDuplex_IRQHandler+0xb2>
8002106: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
800210a: 685a ldr r2, [r3, #4]
800210c: 687b ldr r3, [r7, #4]
800210e: 681b ldr r3, [r3, #0]
8002110: 4979 ldr r1, [pc, #484] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
8002112: 428b cmp r3, r1
8002114: d101 bne.n 800211a <HAL_I2SEx_FullDuplex_IRQHandler+0xc2>
8002116: 4b79 ldr r3, [pc, #484] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
8002118: e001 b.n 800211e <HAL_I2SEx_FullDuplex_IRQHandler+0xc6>
800211a: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
800211e: f022 0260 bic.w r2, r2, #96 ; 0x60
8002122: 605a str r2, [r3, #4]
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
8002124: 687b ldr r3, [r7, #4]
8002126: 681b ldr r3, [r3, #0]
8002128: 685a ldr r2, [r3, #4]
800212a: 687b ldr r3, [r7, #4]
800212c: 681b ldr r3, [r3, #0]
800212e: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8002132: 605a str r2, [r3, #4]
/* Clear Overrun flag */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
8002134: 2300 movs r3, #0
8002136: 60fb str r3, [r7, #12]
8002138: 687b ldr r3, [r7, #4]
800213a: 681b ldr r3, [r3, #0]
800213c: 68db ldr r3, [r3, #12]
800213e: 60fb str r3, [r7, #12]
8002140: 687b ldr r3, [r7, #4]
8002142: 681b ldr r3, [r3, #0]
8002144: 689b ldr r3, [r3, #8]
8002146: 60fb str r3, [r7, #12]
8002148: 68fb ldr r3, [r7, #12]
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
800214a: 687b ldr r3, [r7, #4]
800214c: 2201 movs r2, #1
800214e: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
8002152: 687b ldr r3, [r7, #4]
8002154: 6c5b ldr r3, [r3, #68] ; 0x44
8002156: f043 0202 orr.w r2, r3, #2
800215a: 687b ldr r3, [r7, #4]
800215c: 645a str r2, [r3, #68] ; 0x44
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
800215e: 6878 ldr r0, [r7, #4]
8002160: f7ff fe88 bl 8001e74 <HAL_I2S_ErrorCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/* I2S Underrun error interrupt occurred ----------------------------------*/
if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET))
8002164: 69fb ldr r3, [r7, #28]
8002166: f003 0308 and.w r3, r3, #8
800216a: 2b08 cmp r3, #8
800216c: f040 80be bne.w 80022ec <HAL_I2SEx_FullDuplex_IRQHandler+0x294>
8002170: 697b ldr r3, [r7, #20]
8002172: f003 0320 and.w r3, r3, #32
8002176: 2b00 cmp r3, #0
8002178: f000 80b8 beq.w 80022ec <HAL_I2SEx_FullDuplex_IRQHandler+0x294>
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
800217c: 687b ldr r3, [r7, #4]
800217e: 681b ldr r3, [r3, #0]
8002180: 685a ldr r2, [r3, #4]
8002182: 687b ldr r3, [r7, #4]
8002184: 681b ldr r3, [r3, #0]
8002186: f022 02a0 bic.w r2, r2, #160 ; 0xa0
800218a: 605a str r2, [r3, #4]
/* Disable RXNE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
800218c: 687b ldr r3, [r7, #4]
800218e: 681b ldr r3, [r3, #0]
8002190: 4a59 ldr r2, [pc, #356] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
8002192: 4293 cmp r3, r2
8002194: d101 bne.n 800219a <HAL_I2SEx_FullDuplex_IRQHandler+0x142>
8002196: 4b59 ldr r3, [pc, #356] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
8002198: e001 b.n 800219e <HAL_I2SEx_FullDuplex_IRQHandler+0x146>
800219a: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
800219e: 685a ldr r2, [r3, #4]
80021a0: 687b ldr r3, [r7, #4]
80021a2: 681b ldr r3, [r3, #0]
80021a4: 4954 ldr r1, [pc, #336] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
80021a6: 428b cmp r3, r1
80021a8: d101 bne.n 80021ae <HAL_I2SEx_FullDuplex_IRQHandler+0x156>
80021aa: 4b54 ldr r3, [pc, #336] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
80021ac: e001 b.n 80021b2 <HAL_I2SEx_FullDuplex_IRQHandler+0x15a>
80021ae: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
80021b2: f022 0260 bic.w r2, r2, #96 ; 0x60
80021b6: 605a str r2, [r3, #4]
/* Clear underrun flag */
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
80021b8: 2300 movs r3, #0
80021ba: 60bb str r3, [r7, #8]
80021bc: 687b ldr r3, [r7, #4]
80021be: 681b ldr r3, [r3, #0]
80021c0: 689b ldr r3, [r3, #8]
80021c2: 60bb str r3, [r7, #8]
80021c4: 68bb ldr r3, [r7, #8]
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
80021c6: 687b ldr r3, [r7, #4]
80021c8: 2201 movs r2, #1
80021ca: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
80021ce: 687b ldr r3, [r7, #4]
80021d0: 6c5b ldr r3, [r3, #68] ; 0x44
80021d2: f043 0204 orr.w r2, r3, #4
80021d6: 687b ldr r3, [r7, #4]
80021d8: 645a str r2, [r3, #68] ; 0x44
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
80021da: 6878 ldr r0, [r7, #4]
80021dc: f7ff fe4a bl 8001e74 <HAL_I2S_ErrorCallback>
if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET))
80021e0: e084 b.n 80022ec <HAL_I2SEx_FullDuplex_IRQHandler+0x294>
}
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
else
{
/* I2Sext in mode Transmitter ----------------------------------------------*/
if (((i2sextsr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && ((i2sextcr2 & I2S_IT_TXE) != RESET))
80021e2: 69bb ldr r3, [r7, #24]
80021e4: f003 0302 and.w r3, r3, #2
80021e8: 2b02 cmp r3, #2
80021ea: d107 bne.n 80021fc <HAL_I2SEx_FullDuplex_IRQHandler+0x1a4>
80021ec: 693b ldr r3, [r7, #16]
80021ee: f003 0380 and.w r3, r3, #128 ; 0x80
80021f2: 2b00 cmp r3, #0
80021f4: d002 beq.n 80021fc <HAL_I2SEx_FullDuplex_IRQHandler+0x1a4>
{
/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
I2SEx_TxISR_I2SExt(hi2s);
80021f6: 6878 ldr r0, [r7, #4]
80021f8: f000 f8be bl 8002378 <I2SEx_TxISR_I2SExt>
}
/* I2S in mode Receiver --------------------------------------------------*/
if (((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && ((i2scr2 & I2S_IT_RXNE) != RESET))
80021fc: 69fb ldr r3, [r7, #28]
80021fe: f003 0301 and.w r3, r3, #1
8002202: 2b01 cmp r3, #1
8002204: d107 bne.n 8002216 <HAL_I2SEx_FullDuplex_IRQHandler+0x1be>
8002206: 697b ldr r3, [r7, #20]
8002208: f003 0340 and.w r3, r3, #64 ; 0x40
800220c: 2b00 cmp r3, #0
800220e: d002 beq.n 8002216 <HAL_I2SEx_FullDuplex_IRQHandler+0x1be>
{
/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
I2SEx_RxISR_I2S(hi2s);
8002210: 6878 ldr r0, [r7, #4]
8002212: f000 f8fd bl 8002410 <I2SEx_RxISR_I2S>
}
/* I2S Overrun error interrupt occurred -------------------------------------*/
if (((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && ((i2scr2 & I2S_IT_ERR) != RESET))
8002216: 69fb ldr r3, [r7, #28]
8002218: f003 0340 and.w r3, r3, #64 ; 0x40
800221c: 2b40 cmp r3, #64 ; 0x40
800221e: d12f bne.n 8002280 <HAL_I2SEx_FullDuplex_IRQHandler+0x228>
8002220: 697b ldr r3, [r7, #20]
8002222: f003 0320 and.w r3, r3, #32
8002226: 2b00 cmp r3, #0
8002228: d02a beq.n 8002280 <HAL_I2SEx_FullDuplex_IRQHandler+0x228>
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
800222a: 687b ldr r3, [r7, #4]
800222c: 681b ldr r3, [r3, #0]
800222e: 685a ldr r2, [r3, #4]
8002230: 687b ldr r3, [r7, #4]
8002232: 681b ldr r3, [r3, #0]
8002234: f022 0260 bic.w r2, r2, #96 ; 0x60
8002238: 605a str r2, [r3, #4]
/* Disable TXE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
800223a: 687b ldr r3, [r7, #4]
800223c: 681b ldr r3, [r3, #0]
800223e: 4a2e ldr r2, [pc, #184] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
8002240: 4293 cmp r3, r2
8002242: d101 bne.n 8002248 <HAL_I2SEx_FullDuplex_IRQHandler+0x1f0>
8002244: 4b2d ldr r3, [pc, #180] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
8002246: e001 b.n 800224c <HAL_I2SEx_FullDuplex_IRQHandler+0x1f4>
8002248: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
800224c: 685a ldr r2, [r3, #4]
800224e: 687b ldr r3, [r7, #4]
8002250: 681b ldr r3, [r3, #0]
8002252: 4929 ldr r1, [pc, #164] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
8002254: 428b cmp r3, r1
8002256: d101 bne.n 800225c <HAL_I2SEx_FullDuplex_IRQHandler+0x204>
8002258: 4b28 ldr r3, [pc, #160] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
800225a: e001 b.n 8002260 <HAL_I2SEx_FullDuplex_IRQHandler+0x208>
800225c: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
8002260: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8002264: 605a str r2, [r3, #4]
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
8002266: 687b ldr r3, [r7, #4]
8002268: 2201 movs r2, #1
800226a: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
800226e: 687b ldr r3, [r7, #4]
8002270: 6c5b ldr r3, [r3, #68] ; 0x44
8002272: f043 0202 orr.w r2, r3, #2
8002276: 687b ldr r3, [r7, #4]
8002278: 645a str r2, [r3, #68] ; 0x44
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
800227a: 6878 ldr r0, [r7, #4]
800227c: f7ff fdfa bl 8001e74 <HAL_I2S_ErrorCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/* I2Sext Underrun error interrupt occurred -------------------------------*/
if (((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2sextcr2 & I2S_IT_ERR) != RESET))
8002280: 69bb ldr r3, [r7, #24]
8002282: f003 0308 and.w r3, r3, #8
8002286: 2b08 cmp r3, #8
8002288: d131 bne.n 80022ee <HAL_I2SEx_FullDuplex_IRQHandler+0x296>
800228a: 693b ldr r3, [r7, #16]
800228c: f003 0320 and.w r3, r3, #32
8002290: 2b00 cmp r3, #0
8002292: d02c beq.n 80022ee <HAL_I2SEx_FullDuplex_IRQHandler+0x296>
{
/* Disable TXE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
8002294: 687b ldr r3, [r7, #4]
8002296: 681b ldr r3, [r3, #0]
8002298: 4a17 ldr r2, [pc, #92] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
800229a: 4293 cmp r3, r2
800229c: d101 bne.n 80022a2 <HAL_I2SEx_FullDuplex_IRQHandler+0x24a>
800229e: 4b17 ldr r3, [pc, #92] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
80022a0: e001 b.n 80022a6 <HAL_I2SEx_FullDuplex_IRQHandler+0x24e>
80022a2: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
80022a6: 685a ldr r2, [r3, #4]
80022a8: 687b ldr r3, [r7, #4]
80022aa: 681b ldr r3, [r3, #0]
80022ac: 4912 ldr r1, [pc, #72] ; (80022f8 <HAL_I2SEx_FullDuplex_IRQHandler+0x2a0>)
80022ae: 428b cmp r3, r1
80022b0: d101 bne.n 80022b6 <HAL_I2SEx_FullDuplex_IRQHandler+0x25e>
80022b2: 4b12 ldr r3, [pc, #72] ; (80022fc <HAL_I2SEx_FullDuplex_IRQHandler+0x2a4>)
80022b4: e001 b.n 80022ba <HAL_I2SEx_FullDuplex_IRQHandler+0x262>
80022b6: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
80022ba: f022 02a0 bic.w r2, r2, #160 ; 0xa0
80022be: 605a str r2, [r3, #4]
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
80022c0: 687b ldr r3, [r7, #4]
80022c2: 681b ldr r3, [r3, #0]
80022c4: 685a ldr r2, [r3, #4]
80022c6: 687b ldr r3, [r7, #4]
80022c8: 681b ldr r3, [r3, #0]
80022ca: f022 0260 bic.w r2, r2, #96 ; 0x60
80022ce: 605a str r2, [r3, #4]
/* Set the I2S State ready */
hi2s->State = HAL_I2S_STATE_READY;
80022d0: 687b ldr r3, [r7, #4]
80022d2: 2201 movs r2, #1
80022d4: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Set the error code and execute error callback*/
SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
80022d8: 687b ldr r3, [r7, #4]
80022da: 6c5b ldr r3, [r3, #68] ; 0x44
80022dc: f043 0204 orr.w r2, r3, #4
80022e0: 687b ldr r3, [r7, #4]
80022e2: 645a str r2, [r3, #68] ; 0x44
/* Call user error callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->ErrorCallback(hi2s);
#else
HAL_I2S_ErrorCallback(hi2s);
80022e4: 6878 ldr r0, [r7, #4]
80022e6: f7ff fdc5 bl 8001e74 <HAL_I2S_ErrorCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
80022ea: e000 b.n 80022ee <HAL_I2SEx_FullDuplex_IRQHandler+0x296>
if (((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && ((i2scr2 & I2S_IT_ERR) != RESET))
80022ec: bf00 nop
}
80022ee: bf00 nop
80022f0: 3720 adds r7, #32
80022f2: 46bd mov sp, r7
80022f4: bd80 pop {r7, pc}
80022f6: bf00 nop
80022f8: 40003800 .word 0x40003800
80022fc: 40003400 .word 0x40003400
08002300 <HAL_I2SEx_TxRxCpltCallback>:
* @brief Tx and Rx Transfer completed callback
* @param hi2s I2S handle
* @retval None
*/
__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
{
8002300: b480 push {r7}
8002302: b083 sub sp, #12
8002304: af00 add r7, sp, #0
8002306: 6078 str r0, [r7, #4]
UNUSED(hi2s);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file
*/
}
8002308: bf00 nop
800230a: 370c adds r7, #12
800230c: 46bd mov sp, r7
800230e: f85d 7b04 ldr.w r7, [sp], #4
8002312: 4770 bx lr
08002314 <I2SEx_TxISR_I2S>:
* @brief I2S Full-Duplex IT handler transmit function
* @param hi2s I2S handle
* @retval None
*/
static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s)
{
8002314: b580 push {r7, lr}
8002316: b082 sub sp, #8
8002318: af00 add r7, sp, #0
800231a: 6078 str r0, [r7, #4]
/* Write Data on DR register */
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
800231c: 687b ldr r3, [r7, #4]
800231e: 6a5b ldr r3, [r3, #36] ; 0x24
8002320: 1c99 adds r1, r3, #2
8002322: 687a ldr r2, [r7, #4]
8002324: 6251 str r1, [r2, #36] ; 0x24
8002326: 881a ldrh r2, [r3, #0]
8002328: 687b ldr r3, [r7, #4]
800232a: 681b ldr r3, [r3, #0]
800232c: 60da str r2, [r3, #12]
hi2s->TxXferCount--;
800232e: 687b ldr r3, [r7, #4]
8002330: 8d5b ldrh r3, [r3, #42] ; 0x2a
8002332: b29b uxth r3, r3
8002334: 3b01 subs r3, #1
8002336: b29a uxth r2, r3
8002338: 687b ldr r3, [r7, #4]
800233a: 855a strh r2, [r3, #42] ; 0x2a
if (hi2s->TxXferCount == 0U)
800233c: 687b ldr r3, [r7, #4]
800233e: 8d5b ldrh r3, [r3, #42] ; 0x2a
8002340: b29b uxth r3, r3
8002342: 2b00 cmp r3, #0
8002344: d113 bne.n 800236e <I2SEx_TxISR_I2S+0x5a>
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
8002346: 687b ldr r3, [r7, #4]
8002348: 681b ldr r3, [r3, #0]
800234a: 685a ldr r2, [r3, #4]
800234c: 687b ldr r3, [r7, #4]
800234e: 681b ldr r3, [r3, #0]
8002350: f022 02a0 bic.w r2, r2, #160 ; 0xa0
8002354: 605a str r2, [r3, #4]
if (hi2s->RxXferCount == 0U)
8002356: 687b ldr r3, [r7, #4]
8002358: 8e5b ldrh r3, [r3, #50] ; 0x32
800235a: b29b uxth r3, r3
800235c: 2b00 cmp r3, #0
800235e: d106 bne.n 800236e <I2SEx_TxISR_I2S+0x5a>
{
hi2s->State = HAL_I2S_STATE_READY;
8002360: 687b ldr r3, [r7, #4]
8002362: 2201 movs r2, #1
8002364: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Call user TxRx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxRxCpltCallback(hi2s);
#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
8002368: 6878 ldr r0, [r7, #4]
800236a: f7ff ffc9 bl 8002300 <HAL_I2SEx_TxRxCpltCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
800236e: bf00 nop
8002370: 3708 adds r7, #8
8002372: 46bd mov sp, r7
8002374: bd80 pop {r7, pc}
...
08002378 <I2SEx_TxISR_I2SExt>:
* @brief I2SExt Full-Duplex IT handler transmit function
* @param hi2s I2S handle
* @retval None
*/
static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s)
{
8002378: b580 push {r7, lr}
800237a: b082 sub sp, #8
800237c: af00 add r7, sp, #0
800237e: 6078 str r0, [r7, #4]
/* Write Data on DR register */
I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
8002380: 687b ldr r3, [r7, #4]
8002382: 6a5b ldr r3, [r3, #36] ; 0x24
8002384: 1c99 adds r1, r3, #2
8002386: 687a ldr r2, [r7, #4]
8002388: 6251 str r1, [r2, #36] ; 0x24
800238a: 8819 ldrh r1, [r3, #0]
800238c: 687b ldr r3, [r7, #4]
800238e: 681b ldr r3, [r3, #0]
8002390: 4a1d ldr r2, [pc, #116] ; (8002408 <I2SEx_TxISR_I2SExt+0x90>)
8002392: 4293 cmp r3, r2
8002394: d101 bne.n 800239a <I2SEx_TxISR_I2SExt+0x22>
8002396: 4b1d ldr r3, [pc, #116] ; (800240c <I2SEx_TxISR_I2SExt+0x94>)
8002398: e001 b.n 800239e <I2SEx_TxISR_I2SExt+0x26>
800239a: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
800239e: 460a mov r2, r1
80023a0: 60da str r2, [r3, #12]
hi2s->TxXferCount--;
80023a2: 687b ldr r3, [r7, #4]
80023a4: 8d5b ldrh r3, [r3, #42] ; 0x2a
80023a6: b29b uxth r3, r3
80023a8: 3b01 subs r3, #1
80023aa: b29a uxth r2, r3
80023ac: 687b ldr r3, [r7, #4]
80023ae: 855a strh r2, [r3, #42] ; 0x2a
if (hi2s->TxXferCount == 0U)
80023b0: 687b ldr r3, [r7, #4]
80023b2: 8d5b ldrh r3, [r3, #42] ; 0x2a
80023b4: b29b uxth r3, r3
80023b6: 2b00 cmp r3, #0
80023b8: d121 bne.n 80023fe <I2SEx_TxISR_I2SExt+0x86>
{
/* Disable I2Sext TXE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
80023ba: 687b ldr r3, [r7, #4]
80023bc: 681b ldr r3, [r3, #0]
80023be: 4a12 ldr r2, [pc, #72] ; (8002408 <I2SEx_TxISR_I2SExt+0x90>)
80023c0: 4293 cmp r3, r2
80023c2: d101 bne.n 80023c8 <I2SEx_TxISR_I2SExt+0x50>
80023c4: 4b11 ldr r3, [pc, #68] ; (800240c <I2SEx_TxISR_I2SExt+0x94>)
80023c6: e001 b.n 80023cc <I2SEx_TxISR_I2SExt+0x54>
80023c8: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
80023cc: 685a ldr r2, [r3, #4]
80023ce: 687b ldr r3, [r7, #4]
80023d0: 681b ldr r3, [r3, #0]
80023d2: 490d ldr r1, [pc, #52] ; (8002408 <I2SEx_TxISR_I2SExt+0x90>)
80023d4: 428b cmp r3, r1
80023d6: d101 bne.n 80023dc <I2SEx_TxISR_I2SExt+0x64>
80023d8: 4b0c ldr r3, [pc, #48] ; (800240c <I2SEx_TxISR_I2SExt+0x94>)
80023da: e001 b.n 80023e0 <I2SEx_TxISR_I2SExt+0x68>
80023dc: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
80023e0: f022 02a0 bic.w r2, r2, #160 ; 0xa0
80023e4: 605a str r2, [r3, #4]
if (hi2s->RxXferCount == 0U)
80023e6: 687b ldr r3, [r7, #4]
80023e8: 8e5b ldrh r3, [r3, #50] ; 0x32
80023ea: b29b uxth r3, r3
80023ec: 2b00 cmp r3, #0
80023ee: d106 bne.n 80023fe <I2SEx_TxISR_I2SExt+0x86>
{
hi2s->State = HAL_I2S_STATE_READY;
80023f0: 687b ldr r3, [r7, #4]
80023f2: 2201 movs r2, #1
80023f4: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Call user TxRx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxRxCpltCallback(hi2s);
#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
80023f8: 6878 ldr r0, [r7, #4]
80023fa: f7ff ff81 bl 8002300 <HAL_I2SEx_TxRxCpltCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
80023fe: bf00 nop
8002400: 3708 adds r7, #8
8002402: 46bd mov sp, r7
8002404: bd80 pop {r7, pc}
8002406: bf00 nop
8002408: 40003800 .word 0x40003800
800240c: 40003400 .word 0x40003400
08002410 <I2SEx_RxISR_I2S>:
* @brief I2S Full-Duplex IT handler receive function
* @param hi2s I2S handle
* @retval None
*/
static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s)
{
8002410: b580 push {r7, lr}
8002412: b082 sub sp, #8
8002414: af00 add r7, sp, #0
8002416: 6078 str r0, [r7, #4]
/* Read Data from DR register */
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
8002418: 687b ldr r3, [r7, #4]
800241a: 681b ldr r3, [r3, #0]
800241c: 68d8 ldr r0, [r3, #12]
800241e: 687b ldr r3, [r7, #4]
8002420: 6adb ldr r3, [r3, #44] ; 0x2c
8002422: 1c99 adds r1, r3, #2
8002424: 687a ldr r2, [r7, #4]
8002426: 62d1 str r1, [r2, #44] ; 0x2c
8002428: b282 uxth r2, r0
800242a: 801a strh r2, [r3, #0]
hi2s->RxXferCount--;
800242c: 687b ldr r3, [r7, #4]
800242e: 8e5b ldrh r3, [r3, #50] ; 0x32
8002430: b29b uxth r3, r3
8002432: 3b01 subs r3, #1
8002434: b29a uxth r2, r3
8002436: 687b ldr r3, [r7, #4]
8002438: 865a strh r2, [r3, #50] ; 0x32
if (hi2s->RxXferCount == 0U)
800243a: 687b ldr r3, [r7, #4]
800243c: 8e5b ldrh r3, [r3, #50] ; 0x32
800243e: b29b uxth r3, r3
8002440: 2b00 cmp r3, #0
8002442: d113 bne.n 800246c <I2SEx_RxISR_I2S+0x5c>
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
8002444: 687b ldr r3, [r7, #4]
8002446: 681b ldr r3, [r3, #0]
8002448: 685a ldr r2, [r3, #4]
800244a: 687b ldr r3, [r7, #4]
800244c: 681b ldr r3, [r3, #0]
800244e: f022 0260 bic.w r2, r2, #96 ; 0x60
8002452: 605a str r2, [r3, #4]
if (hi2s->TxXferCount == 0U)
8002454: 687b ldr r3, [r7, #4]
8002456: 8d5b ldrh r3, [r3, #42] ; 0x2a
8002458: b29b uxth r3, r3
800245a: 2b00 cmp r3, #0
800245c: d106 bne.n 800246c <I2SEx_RxISR_I2S+0x5c>
{
hi2s->State = HAL_I2S_STATE_READY;
800245e: 687b ldr r3, [r7, #4]
8002460: 2201 movs r2, #1
8002462: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Call user TxRx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxRxCpltCallback(hi2s);
#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
8002466: 6878 ldr r0, [r7, #4]
8002468: f7ff ff4a bl 8002300 <HAL_I2SEx_TxRxCpltCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
800246c: bf00 nop
800246e: 3708 adds r7, #8
8002470: 46bd mov sp, r7
8002472: bd80 pop {r7, pc}
08002474 <I2SEx_RxISR_I2SExt>:
* @brief I2SExt Full-Duplex IT handler receive function
* @param hi2s I2S handle
* @retval None
*/
static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
{
8002474: b580 push {r7, lr}
8002476: b082 sub sp, #8
8002478: af00 add r7, sp, #0
800247a: 6078 str r0, [r7, #4]
/* Read Data from DR register */
(*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
800247c: 687b ldr r3, [r7, #4]
800247e: 681b ldr r3, [r3, #0]
8002480: 4a20 ldr r2, [pc, #128] ; (8002504 <I2SEx_RxISR_I2SExt+0x90>)
8002482: 4293 cmp r3, r2
8002484: d101 bne.n 800248a <I2SEx_RxISR_I2SExt+0x16>
8002486: 4b20 ldr r3, [pc, #128] ; (8002508 <I2SEx_RxISR_I2SExt+0x94>)
8002488: e001 b.n 800248e <I2SEx_RxISR_I2SExt+0x1a>
800248a: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
800248e: 68d8 ldr r0, [r3, #12]
8002490: 687b ldr r3, [r7, #4]
8002492: 6adb ldr r3, [r3, #44] ; 0x2c
8002494: 1c99 adds r1, r3, #2
8002496: 687a ldr r2, [r7, #4]
8002498: 62d1 str r1, [r2, #44] ; 0x2c
800249a: b282 uxth r2, r0
800249c: 801a strh r2, [r3, #0]
hi2s->RxXferCount--;
800249e: 687b ldr r3, [r7, #4]
80024a0: 8e5b ldrh r3, [r3, #50] ; 0x32
80024a2: b29b uxth r3, r3
80024a4: 3b01 subs r3, #1
80024a6: b29a uxth r2, r3
80024a8: 687b ldr r3, [r7, #4]
80024aa: 865a strh r2, [r3, #50] ; 0x32
if (hi2s->RxXferCount == 0U)
80024ac: 687b ldr r3, [r7, #4]
80024ae: 8e5b ldrh r3, [r3, #50] ; 0x32
80024b0: b29b uxth r3, r3
80024b2: 2b00 cmp r3, #0
80024b4: d121 bne.n 80024fa <I2SEx_RxISR_I2SExt+0x86>
{
/* Disable I2Sext RXNE and ERR interrupt */
__HAL_I2SEXT_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
80024b6: 687b ldr r3, [r7, #4]
80024b8: 681b ldr r3, [r3, #0]
80024ba: 4a12 ldr r2, [pc, #72] ; (8002504 <I2SEx_RxISR_I2SExt+0x90>)
80024bc: 4293 cmp r3, r2
80024be: d101 bne.n 80024c4 <I2SEx_RxISR_I2SExt+0x50>
80024c0: 4b11 ldr r3, [pc, #68] ; (8002508 <I2SEx_RxISR_I2SExt+0x94>)
80024c2: e001 b.n 80024c8 <I2SEx_RxISR_I2SExt+0x54>
80024c4: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
80024c8: 685a ldr r2, [r3, #4]
80024ca: 687b ldr r3, [r7, #4]
80024cc: 681b ldr r3, [r3, #0]
80024ce: 490d ldr r1, [pc, #52] ; (8002504 <I2SEx_RxISR_I2SExt+0x90>)
80024d0: 428b cmp r3, r1
80024d2: d101 bne.n 80024d8 <I2SEx_RxISR_I2SExt+0x64>
80024d4: 4b0c ldr r3, [pc, #48] ; (8002508 <I2SEx_RxISR_I2SExt+0x94>)
80024d6: e001 b.n 80024dc <I2SEx_RxISR_I2SExt+0x68>
80024d8: f04f 2340 mov.w r3, #1073758208 ; 0x40004000
80024dc: f022 0260 bic.w r2, r2, #96 ; 0x60
80024e0: 605a str r2, [r3, #4]
if (hi2s->TxXferCount == 0U)
80024e2: 687b ldr r3, [r7, #4]
80024e4: 8d5b ldrh r3, [r3, #42] ; 0x2a
80024e6: b29b uxth r3, r3
80024e8: 2b00 cmp r3, #0
80024ea: d106 bne.n 80024fa <I2SEx_RxISR_I2SExt+0x86>
{
hi2s->State = HAL_I2S_STATE_READY;
80024ec: 687b ldr r3, [r7, #4]
80024ee: 2201 movs r2, #1
80024f0: f883 2041 strb.w r2, [r3, #65] ; 0x41
/* Call user TxRx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxRxCpltCallback(hi2s);
#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
80024f4: 6878 ldr r0, [r7, #4]
80024f6: f7ff ff03 bl 8002300 <HAL_I2SEx_TxRxCpltCallback>
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
}
80024fa: bf00 nop
80024fc: 3708 adds r7, #8
80024fe: 46bd mov sp, r7
8002500: bd80 pop {r7, pc}
8002502: bf00 nop
8002504: 40003800 .word 0x40003800
8002508: 40003400 .word 0x40003400
0800250c <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800250c: b580 push {r7, lr}
800250e: b086 sub sp, #24
8002510: af00 add r7, sp, #0
8002512: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8002514: 687b ldr r3, [r7, #4]
8002516: 2b00 cmp r3, #0
8002518: d101 bne.n 800251e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800251a: 2301 movs r3, #1
800251c: e264 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800251e: 687b ldr r3, [r7, #4]
8002520: 681b ldr r3, [r3, #0]
8002522: f003 0301 and.w r3, r3, #1
8002526: 2b00 cmp r3, #0
8002528: d075 beq.n 8002616 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
800252a: 4ba3 ldr r3, [pc, #652] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800252c: 689b ldr r3, [r3, #8]
800252e: f003 030c and.w r3, r3, #12
8002532: 2b04 cmp r3, #4
8002534: d00c beq.n 8002550 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8002536: 4ba0 ldr r3, [pc, #640] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002538: 689b ldr r3, [r3, #8]
800253a: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
800253e: 2b08 cmp r3, #8
8002540: d112 bne.n 8002568 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8002542: 4b9d ldr r3, [pc, #628] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002544: 685b ldr r3, [r3, #4]
8002546: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800254a: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
800254e: d10b bne.n 8002568 <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002550: 4b99 ldr r3, [pc, #612] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002552: 681b ldr r3, [r3, #0]
8002554: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002558: 2b00 cmp r3, #0
800255a: d05b beq.n 8002614 <HAL_RCC_OscConfig+0x108>
800255c: 687b ldr r3, [r7, #4]
800255e: 685b ldr r3, [r3, #4]
8002560: 2b00 cmp r3, #0
8002562: d157 bne.n 8002614 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8002564: 2301 movs r3, #1
8002566: e23f b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002568: 687b ldr r3, [r7, #4]
800256a: 685b ldr r3, [r3, #4]
800256c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8002570: d106 bne.n 8002580 <HAL_RCC_OscConfig+0x74>
8002572: 4b91 ldr r3, [pc, #580] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002574: 681b ldr r3, [r3, #0]
8002576: 4a90 ldr r2, [pc, #576] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002578: f443 3380 orr.w r3, r3, #65536 ; 0x10000
800257c: 6013 str r3, [r2, #0]
800257e: e01d b.n 80025bc <HAL_RCC_OscConfig+0xb0>
8002580: 687b ldr r3, [r7, #4]
8002582: 685b ldr r3, [r3, #4]
8002584: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8002588: d10c bne.n 80025a4 <HAL_RCC_OscConfig+0x98>
800258a: 4b8b ldr r3, [pc, #556] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800258c: 681b ldr r3, [r3, #0]
800258e: 4a8a ldr r2, [pc, #552] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002590: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8002594: 6013 str r3, [r2, #0]
8002596: 4b88 ldr r3, [pc, #544] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002598: 681b ldr r3, [r3, #0]
800259a: 4a87 ldr r2, [pc, #540] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800259c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80025a0: 6013 str r3, [r2, #0]
80025a2: e00b b.n 80025bc <HAL_RCC_OscConfig+0xb0>
80025a4: 4b84 ldr r3, [pc, #528] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80025a6: 681b ldr r3, [r3, #0]
80025a8: 4a83 ldr r2, [pc, #524] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80025aa: f423 3380 bic.w r3, r3, #65536 ; 0x10000
80025ae: 6013 str r3, [r2, #0]
80025b0: 4b81 ldr r3, [pc, #516] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80025b2: 681b ldr r3, [r3, #0]
80025b4: 4a80 ldr r2, [pc, #512] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80025b6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
80025ba: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
80025bc: 687b ldr r3, [r7, #4]
80025be: 685b ldr r3, [r3, #4]
80025c0: 2b00 cmp r3, #0
80025c2: d013 beq.n 80025ec <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80025c4: f7fe fcd0 bl 8000f68 <HAL_GetTick>
80025c8: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80025ca: e008 b.n 80025de <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80025cc: f7fe fccc bl 8000f68 <HAL_GetTick>
80025d0: 4602 mov r2, r0
80025d2: 693b ldr r3, [r7, #16]
80025d4: 1ad3 subs r3, r2, r3
80025d6: 2b64 cmp r3, #100 ; 0x64
80025d8: d901 bls.n 80025de <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
80025da: 2303 movs r3, #3
80025dc: e204 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80025de: 4b76 ldr r3, [pc, #472] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80025e0: 681b ldr r3, [r3, #0]
80025e2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80025e6: 2b00 cmp r3, #0
80025e8: d0f0 beq.n 80025cc <HAL_RCC_OscConfig+0xc0>
80025ea: e014 b.n 8002616 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80025ec: f7fe fcbc bl 8000f68 <HAL_GetTick>
80025f0: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80025f2: e008 b.n 8002606 <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80025f4: f7fe fcb8 bl 8000f68 <HAL_GetTick>
80025f8: 4602 mov r2, r0
80025fa: 693b ldr r3, [r7, #16]
80025fc: 1ad3 subs r3, r2, r3
80025fe: 2b64 cmp r3, #100 ; 0x64
8002600: d901 bls.n 8002606 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8002602: 2303 movs r3, #3
8002604: e1f0 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8002606: 4b6c ldr r3, [pc, #432] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002608: 681b ldr r3, [r3, #0]
800260a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800260e: 2b00 cmp r3, #0
8002610: d1f0 bne.n 80025f4 <HAL_RCC_OscConfig+0xe8>
8002612: e000 b.n 8002616 <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002614: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8002616: 687b ldr r3, [r7, #4]
8002618: 681b ldr r3, [r3, #0]
800261a: f003 0302 and.w r3, r3, #2
800261e: 2b00 cmp r3, #0
8002620: d063 beq.n 80026ea <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8002622: 4b65 ldr r3, [pc, #404] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002624: 689b ldr r3, [r3, #8]
8002626: f003 030c and.w r3, r3, #12
800262a: 2b00 cmp r3, #0
800262c: d00b beq.n 8002646 <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800262e: 4b62 ldr r3, [pc, #392] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002630: 689b ldr r3, [r3, #8]
8002632: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8002636: 2b08 cmp r3, #8
8002638: d11c bne.n 8002674 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800263a: 4b5f ldr r3, [pc, #380] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800263c: 685b ldr r3, [r3, #4]
800263e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002642: 2b00 cmp r3, #0
8002644: d116 bne.n 8002674 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002646: 4b5c ldr r3, [pc, #368] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002648: 681b ldr r3, [r3, #0]
800264a: f003 0302 and.w r3, r3, #2
800264e: 2b00 cmp r3, #0
8002650: d005 beq.n 800265e <HAL_RCC_OscConfig+0x152>
8002652: 687b ldr r3, [r7, #4]
8002654: 68db ldr r3, [r3, #12]
8002656: 2b01 cmp r3, #1
8002658: d001 beq.n 800265e <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
800265a: 2301 movs r3, #1
800265c: e1c4 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800265e: 4b56 ldr r3, [pc, #344] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002660: 681b ldr r3, [r3, #0]
8002662: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8002666: 687b ldr r3, [r7, #4]
8002668: 691b ldr r3, [r3, #16]
800266a: 00db lsls r3, r3, #3
800266c: 4952 ldr r1, [pc, #328] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800266e: 4313 orrs r3, r2
8002670: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8002672: e03a b.n 80026ea <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8002674: 687b ldr r3, [r7, #4]
8002676: 68db ldr r3, [r3, #12]
8002678: 2b00 cmp r3, #0
800267a: d020 beq.n 80026be <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800267c: 4b4f ldr r3, [pc, #316] ; (80027bc <HAL_RCC_OscConfig+0x2b0>)
800267e: 2201 movs r2, #1
8002680: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002682: f7fe fc71 bl 8000f68 <HAL_GetTick>
8002686: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002688: e008 b.n 800269c <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800268a: f7fe fc6d bl 8000f68 <HAL_GetTick>
800268e: 4602 mov r2, r0
8002690: 693b ldr r3, [r7, #16]
8002692: 1ad3 subs r3, r2, r3
8002694: 2b02 cmp r3, #2
8002696: d901 bls.n 800269c <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8002698: 2303 movs r3, #3
800269a: e1a5 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800269c: 4b46 ldr r3, [pc, #280] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800269e: 681b ldr r3, [r3, #0]
80026a0: f003 0302 and.w r3, r3, #2
80026a4: 2b00 cmp r3, #0
80026a6: d0f0 beq.n 800268a <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80026a8: 4b43 ldr r3, [pc, #268] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80026aa: 681b ldr r3, [r3, #0]
80026ac: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80026b0: 687b ldr r3, [r7, #4]
80026b2: 691b ldr r3, [r3, #16]
80026b4: 00db lsls r3, r3, #3
80026b6: 4940 ldr r1, [pc, #256] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80026b8: 4313 orrs r3, r2
80026ba: 600b str r3, [r1, #0]
80026bc: e015 b.n 80026ea <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80026be: 4b3f ldr r3, [pc, #252] ; (80027bc <HAL_RCC_OscConfig+0x2b0>)
80026c0: 2200 movs r2, #0
80026c2: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80026c4: f7fe fc50 bl 8000f68 <HAL_GetTick>
80026c8: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80026ca: e008 b.n 80026de <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80026cc: f7fe fc4c bl 8000f68 <HAL_GetTick>
80026d0: 4602 mov r2, r0
80026d2: 693b ldr r3, [r7, #16]
80026d4: 1ad3 subs r3, r2, r3
80026d6: 2b02 cmp r3, #2
80026d8: d901 bls.n 80026de <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
80026da: 2303 movs r3, #3
80026dc: e184 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80026de: 4b36 ldr r3, [pc, #216] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
80026e0: 681b ldr r3, [r3, #0]
80026e2: f003 0302 and.w r3, r3, #2
80026e6: 2b00 cmp r3, #0
80026e8: d1f0 bne.n 80026cc <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80026ea: 687b ldr r3, [r7, #4]
80026ec: 681b ldr r3, [r3, #0]
80026ee: f003 0308 and.w r3, r3, #8
80026f2: 2b00 cmp r3, #0
80026f4: d030 beq.n 8002758 <HAL_RCC_OscConfig+0x24c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
80026f6: 687b ldr r3, [r7, #4]
80026f8: 695b ldr r3, [r3, #20]
80026fa: 2b00 cmp r3, #0
80026fc: d016 beq.n 800272c <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80026fe: 4b30 ldr r3, [pc, #192] ; (80027c0 <HAL_RCC_OscConfig+0x2b4>)
8002700: 2201 movs r2, #1
8002702: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002704: f7fe fc30 bl 8000f68 <HAL_GetTick>
8002708: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800270a: e008 b.n 800271e <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800270c: f7fe fc2c bl 8000f68 <HAL_GetTick>
8002710: 4602 mov r2, r0
8002712: 693b ldr r3, [r7, #16]
8002714: 1ad3 subs r3, r2, r3
8002716: 2b02 cmp r3, #2
8002718: d901 bls.n 800271e <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
800271a: 2303 movs r3, #3
800271c: e164 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800271e: 4b26 ldr r3, [pc, #152] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002720: 6f5b ldr r3, [r3, #116] ; 0x74
8002722: f003 0302 and.w r3, r3, #2
8002726: 2b00 cmp r3, #0
8002728: d0f0 beq.n 800270c <HAL_RCC_OscConfig+0x200>
800272a: e015 b.n 8002758 <HAL_RCC_OscConfig+0x24c>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
800272c: 4b24 ldr r3, [pc, #144] ; (80027c0 <HAL_RCC_OscConfig+0x2b4>)
800272e: 2200 movs r2, #0
8002730: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002732: f7fe fc19 bl 8000f68 <HAL_GetTick>
8002736: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8002738: e008 b.n 800274c <HAL_RCC_OscConfig+0x240>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800273a: f7fe fc15 bl 8000f68 <HAL_GetTick>
800273e: 4602 mov r2, r0
8002740: 693b ldr r3, [r7, #16]
8002742: 1ad3 subs r3, r2, r3
8002744: 2b02 cmp r3, #2
8002746: d901 bls.n 800274c <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
8002748: 2303 movs r3, #3
800274a: e14d b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800274c: 4b1a ldr r3, [pc, #104] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800274e: 6f5b ldr r3, [r3, #116] ; 0x74
8002750: f003 0302 and.w r3, r3, #2
8002754: 2b00 cmp r3, #0
8002756: d1f0 bne.n 800273a <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002758: 687b ldr r3, [r7, #4]
800275a: 681b ldr r3, [r3, #0]
800275c: f003 0304 and.w r3, r3, #4
8002760: 2b00 cmp r3, #0
8002762: f000 80a0 beq.w 80028a6 <HAL_RCC_OscConfig+0x39a>
{
FlagStatus pwrclkchanged = RESET;
8002766: 2300 movs r3, #0
8002768: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800276a: 4b13 ldr r3, [pc, #76] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800276c: 6c1b ldr r3, [r3, #64] ; 0x40
800276e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002772: 2b00 cmp r3, #0
8002774: d10f bne.n 8002796 <HAL_RCC_OscConfig+0x28a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002776: 2300 movs r3, #0
8002778: 60bb str r3, [r7, #8]
800277a: 4b0f ldr r3, [pc, #60] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
800277c: 6c1b ldr r3, [r3, #64] ; 0x40
800277e: 4a0e ldr r2, [pc, #56] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002780: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8002784: 6413 str r3, [r2, #64] ; 0x40
8002786: 4b0c ldr r3, [pc, #48] ; (80027b8 <HAL_RCC_OscConfig+0x2ac>)
8002788: 6c1b ldr r3, [r3, #64] ; 0x40
800278a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800278e: 60bb str r3, [r7, #8]
8002790: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8002792: 2301 movs r3, #1
8002794: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002796: 4b0b ldr r3, [pc, #44] ; (80027c4 <HAL_RCC_OscConfig+0x2b8>)
8002798: 681b ldr r3, [r3, #0]
800279a: f403 7380 and.w r3, r3, #256 ; 0x100
800279e: 2b00 cmp r3, #0
80027a0: d121 bne.n 80027e6 <HAL_RCC_OscConfig+0x2da>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80027a2: 4b08 ldr r3, [pc, #32] ; (80027c4 <HAL_RCC_OscConfig+0x2b8>)
80027a4: 681b ldr r3, [r3, #0]
80027a6: 4a07 ldr r2, [pc, #28] ; (80027c4 <HAL_RCC_OscConfig+0x2b8>)
80027a8: f443 7380 orr.w r3, r3, #256 ; 0x100
80027ac: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80027ae: f7fe fbdb bl 8000f68 <HAL_GetTick>
80027b2: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80027b4: e011 b.n 80027da <HAL_RCC_OscConfig+0x2ce>
80027b6: bf00 nop
80027b8: 40023800 .word 0x40023800
80027bc: 42470000 .word 0x42470000
80027c0: 42470e80 .word 0x42470e80
80027c4: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80027c8: f7fe fbce bl 8000f68 <HAL_GetTick>
80027cc: 4602 mov r2, r0
80027ce: 693b ldr r3, [r7, #16]
80027d0: 1ad3 subs r3, r2, r3
80027d2: 2b02 cmp r3, #2
80027d4: d901 bls.n 80027da <HAL_RCC_OscConfig+0x2ce>
{
return HAL_TIMEOUT;
80027d6: 2303 movs r3, #3
80027d8: e106 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80027da: 4b85 ldr r3, [pc, #532] ; (80029f0 <HAL_RCC_OscConfig+0x4e4>)
80027dc: 681b ldr r3, [r3, #0]
80027de: f403 7380 and.w r3, r3, #256 ; 0x100
80027e2: 2b00 cmp r3, #0
80027e4: d0f0 beq.n 80027c8 <HAL_RCC_OscConfig+0x2bc>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80027e6: 687b ldr r3, [r7, #4]
80027e8: 689b ldr r3, [r3, #8]
80027ea: 2b01 cmp r3, #1
80027ec: d106 bne.n 80027fc <HAL_RCC_OscConfig+0x2f0>
80027ee: 4b81 ldr r3, [pc, #516] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
80027f0: 6f1b ldr r3, [r3, #112] ; 0x70
80027f2: 4a80 ldr r2, [pc, #512] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
80027f4: f043 0301 orr.w r3, r3, #1
80027f8: 6713 str r3, [r2, #112] ; 0x70
80027fa: e01c b.n 8002836 <HAL_RCC_OscConfig+0x32a>
80027fc: 687b ldr r3, [r7, #4]
80027fe: 689b ldr r3, [r3, #8]
8002800: 2b05 cmp r3, #5
8002802: d10c bne.n 800281e <HAL_RCC_OscConfig+0x312>
8002804: 4b7b ldr r3, [pc, #492] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002806: 6f1b ldr r3, [r3, #112] ; 0x70
8002808: 4a7a ldr r2, [pc, #488] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
800280a: f043 0304 orr.w r3, r3, #4
800280e: 6713 str r3, [r2, #112] ; 0x70
8002810: 4b78 ldr r3, [pc, #480] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002812: 6f1b ldr r3, [r3, #112] ; 0x70
8002814: 4a77 ldr r2, [pc, #476] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002816: f043 0301 orr.w r3, r3, #1
800281a: 6713 str r3, [r2, #112] ; 0x70
800281c: e00b b.n 8002836 <HAL_RCC_OscConfig+0x32a>
800281e: 4b75 ldr r3, [pc, #468] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002820: 6f1b ldr r3, [r3, #112] ; 0x70
8002822: 4a74 ldr r2, [pc, #464] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002824: f023 0301 bic.w r3, r3, #1
8002828: 6713 str r3, [r2, #112] ; 0x70
800282a: 4b72 ldr r3, [pc, #456] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
800282c: 6f1b ldr r3, [r3, #112] ; 0x70
800282e: 4a71 ldr r2, [pc, #452] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002830: f023 0304 bic.w r3, r3, #4
8002834: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8002836: 687b ldr r3, [r7, #4]
8002838: 689b ldr r3, [r3, #8]
800283a: 2b00 cmp r3, #0
800283c: d015 beq.n 800286a <HAL_RCC_OscConfig+0x35e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800283e: f7fe fb93 bl 8000f68 <HAL_GetTick>
8002842: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002844: e00a b.n 800285c <HAL_RCC_OscConfig+0x350>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002846: f7fe fb8f bl 8000f68 <HAL_GetTick>
800284a: 4602 mov r2, r0
800284c: 693b ldr r3, [r7, #16]
800284e: 1ad3 subs r3, r2, r3
8002850: f241 3288 movw r2, #5000 ; 0x1388
8002854: 4293 cmp r3, r2
8002856: d901 bls.n 800285c <HAL_RCC_OscConfig+0x350>
{
return HAL_TIMEOUT;
8002858: 2303 movs r3, #3
800285a: e0c5 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800285c: 4b65 ldr r3, [pc, #404] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
800285e: 6f1b ldr r3, [r3, #112] ; 0x70
8002860: f003 0302 and.w r3, r3, #2
8002864: 2b00 cmp r3, #0
8002866: d0ee beq.n 8002846 <HAL_RCC_OscConfig+0x33a>
8002868: e014 b.n 8002894 <HAL_RCC_OscConfig+0x388>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800286a: f7fe fb7d bl 8000f68 <HAL_GetTick>
800286e: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002870: e00a b.n 8002888 <HAL_RCC_OscConfig+0x37c>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002872: f7fe fb79 bl 8000f68 <HAL_GetTick>
8002876: 4602 mov r2, r0
8002878: 693b ldr r3, [r7, #16]
800287a: 1ad3 subs r3, r2, r3
800287c: f241 3288 movw r2, #5000 ; 0x1388
8002880: 4293 cmp r3, r2
8002882: d901 bls.n 8002888 <HAL_RCC_OscConfig+0x37c>
{
return HAL_TIMEOUT;
8002884: 2303 movs r3, #3
8002886: e0af b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8002888: 4b5a ldr r3, [pc, #360] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
800288a: 6f1b ldr r3, [r3, #112] ; 0x70
800288c: f003 0302 and.w r3, r3, #2
8002890: 2b00 cmp r3, #0
8002892: d1ee bne.n 8002872 <HAL_RCC_OscConfig+0x366>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8002894: 7dfb ldrb r3, [r7, #23]
8002896: 2b01 cmp r3, #1
8002898: d105 bne.n 80028a6 <HAL_RCC_OscConfig+0x39a>
{
__HAL_RCC_PWR_CLK_DISABLE();
800289a: 4b56 ldr r3, [pc, #344] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
800289c: 6c1b ldr r3, [r3, #64] ; 0x40
800289e: 4a55 ldr r2, [pc, #340] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
80028a0: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80028a4: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80028a6: 687b ldr r3, [r7, #4]
80028a8: 699b ldr r3, [r3, #24]
80028aa: 2b00 cmp r3, #0
80028ac: f000 809b beq.w 80029e6 <HAL_RCC_OscConfig+0x4da>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
80028b0: 4b50 ldr r3, [pc, #320] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
80028b2: 689b ldr r3, [r3, #8]
80028b4: f003 030c and.w r3, r3, #12
80028b8: 2b08 cmp r3, #8
80028ba: d05c beq.n 8002976 <HAL_RCC_OscConfig+0x46a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80028bc: 687b ldr r3, [r7, #4]
80028be: 699b ldr r3, [r3, #24]
80028c0: 2b02 cmp r3, #2
80028c2: d141 bne.n 8002948 <HAL_RCC_OscConfig+0x43c>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80028c4: 4b4c ldr r3, [pc, #304] ; (80029f8 <HAL_RCC_OscConfig+0x4ec>)
80028c6: 2200 movs r2, #0
80028c8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80028ca: f7fe fb4d bl 8000f68 <HAL_GetTick>
80028ce: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80028d0: e008 b.n 80028e4 <HAL_RCC_OscConfig+0x3d8>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80028d2: f7fe fb49 bl 8000f68 <HAL_GetTick>
80028d6: 4602 mov r2, r0
80028d8: 693b ldr r3, [r7, #16]
80028da: 1ad3 subs r3, r2, r3
80028dc: 2b02 cmp r3, #2
80028de: d901 bls.n 80028e4 <HAL_RCC_OscConfig+0x3d8>
{
return HAL_TIMEOUT;
80028e0: 2303 movs r3, #3
80028e2: e081 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80028e4: 4b43 ldr r3, [pc, #268] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
80028e6: 681b ldr r3, [r3, #0]
80028e8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80028ec: 2b00 cmp r3, #0
80028ee: d1f0 bne.n 80028d2 <HAL_RCC_OscConfig+0x3c6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
80028f0: 687b ldr r3, [r7, #4]
80028f2: 69da ldr r2, [r3, #28]
80028f4: 687b ldr r3, [r7, #4]
80028f6: 6a1b ldr r3, [r3, #32]
80028f8: 431a orrs r2, r3
80028fa: 687b ldr r3, [r7, #4]
80028fc: 6a5b ldr r3, [r3, #36] ; 0x24
80028fe: 019b lsls r3, r3, #6
8002900: 431a orrs r2, r3
8002902: 687b ldr r3, [r7, #4]
8002904: 6a9b ldr r3, [r3, #40] ; 0x28
8002906: 085b lsrs r3, r3, #1
8002908: 3b01 subs r3, #1
800290a: 041b lsls r3, r3, #16
800290c: 431a orrs r2, r3
800290e: 687b ldr r3, [r7, #4]
8002910: 6adb ldr r3, [r3, #44] ; 0x2c
8002912: 061b lsls r3, r3, #24
8002914: 4937 ldr r1, [pc, #220] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002916: 4313 orrs r3, r2
8002918: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800291a: 4b37 ldr r3, [pc, #220] ; (80029f8 <HAL_RCC_OscConfig+0x4ec>)
800291c: 2201 movs r2, #1
800291e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002920: f7fe fb22 bl 8000f68 <HAL_GetTick>
8002924: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002926: e008 b.n 800293a <HAL_RCC_OscConfig+0x42e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002928: f7fe fb1e bl 8000f68 <HAL_GetTick>
800292c: 4602 mov r2, r0
800292e: 693b ldr r3, [r7, #16]
8002930: 1ad3 subs r3, r2, r3
8002932: 2b02 cmp r3, #2
8002934: d901 bls.n 800293a <HAL_RCC_OscConfig+0x42e>
{
return HAL_TIMEOUT;
8002936: 2303 movs r3, #3
8002938: e056 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800293a: 4b2e ldr r3, [pc, #184] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
800293c: 681b ldr r3, [r3, #0]
800293e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002942: 2b00 cmp r3, #0
8002944: d0f0 beq.n 8002928 <HAL_RCC_OscConfig+0x41c>
8002946: e04e b.n 80029e6 <HAL_RCC_OscConfig+0x4da>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002948: 4b2b ldr r3, [pc, #172] ; (80029f8 <HAL_RCC_OscConfig+0x4ec>)
800294a: 2200 movs r2, #0
800294c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800294e: f7fe fb0b bl 8000f68 <HAL_GetTick>
8002952: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002954: e008 b.n 8002968 <HAL_RCC_OscConfig+0x45c>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002956: f7fe fb07 bl 8000f68 <HAL_GetTick>
800295a: 4602 mov r2, r0
800295c: 693b ldr r3, [r7, #16]
800295e: 1ad3 subs r3, r2, r3
8002960: 2b02 cmp r3, #2
8002962: d901 bls.n 8002968 <HAL_RCC_OscConfig+0x45c>
{
return HAL_TIMEOUT;
8002964: 2303 movs r3, #3
8002966: e03f b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002968: 4b22 ldr r3, [pc, #136] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
800296a: 681b ldr r3, [r3, #0]
800296c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002970: 2b00 cmp r3, #0
8002972: d1f0 bne.n 8002956 <HAL_RCC_OscConfig+0x44a>
8002974: e037 b.n 80029e6 <HAL_RCC_OscConfig+0x4da>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002976: 687b ldr r3, [r7, #4]
8002978: 699b ldr r3, [r3, #24]
800297a: 2b01 cmp r3, #1
800297c: d101 bne.n 8002982 <HAL_RCC_OscConfig+0x476>
{
return HAL_ERROR;
800297e: 2301 movs r3, #1
8002980: e032 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8002982: 4b1c ldr r3, [pc, #112] ; (80029f4 <HAL_RCC_OscConfig+0x4e8>)
8002984: 685b ldr r3, [r3, #4]
8002986: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8002988: 687b ldr r3, [r7, #4]
800298a: 699b ldr r3, [r3, #24]
800298c: 2b01 cmp r3, #1
800298e: d028 beq.n 80029e2 <HAL_RCC_OscConfig+0x4d6>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002990: 68fb ldr r3, [r7, #12]
8002992: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8002996: 687b ldr r3, [r7, #4]
8002998: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
800299a: 429a cmp r2, r3
800299c: d121 bne.n 80029e2 <HAL_RCC_OscConfig+0x4d6>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
800299e: 68fb ldr r3, [r7, #12]
80029a0: f003 023f and.w r2, r3, #63 ; 0x3f
80029a4: 687b ldr r3, [r7, #4]
80029a6: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80029a8: 429a cmp r2, r3
80029aa: d11a bne.n 80029e2 <HAL_RCC_OscConfig+0x4d6>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80029ac: 68fa ldr r2, [r7, #12]
80029ae: f647 73c0 movw r3, #32704 ; 0x7fc0
80029b2: 4013 ands r3, r2
80029b4: 687a ldr r2, [r7, #4]
80029b6: 6a52 ldr r2, [r2, #36] ; 0x24
80029b8: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
80029ba: 4293 cmp r3, r2
80029bc: d111 bne.n 80029e2 <HAL_RCC_OscConfig+0x4d6>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80029be: 68fb ldr r3, [r7, #12]
80029c0: f403 3240 and.w r2, r3, #196608 ; 0x30000
80029c4: 687b ldr r3, [r7, #4]
80029c6: 6a9b ldr r3, [r3, #40] ; 0x28
80029c8: 085b lsrs r3, r3, #1
80029ca: 3b01 subs r3, #1
80029cc: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80029ce: 429a cmp r2, r3
80029d0: d107 bne.n 80029e2 <HAL_RCC_OscConfig+0x4d6>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
80029d2: 68fb ldr r3, [r7, #12]
80029d4: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
80029d8: 687b ldr r3, [r7, #4]
80029da: 6adb ldr r3, [r3, #44] ; 0x2c
80029dc: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80029de: 429a cmp r2, r3
80029e0: d001 beq.n 80029e6 <HAL_RCC_OscConfig+0x4da>
#endif
{
return HAL_ERROR;
80029e2: 2301 movs r3, #1
80029e4: e000 b.n 80029e8 <HAL_RCC_OscConfig+0x4dc>
}
}
}
}
return HAL_OK;
80029e6: 2300 movs r3, #0
}
80029e8: 4618 mov r0, r3
80029ea: 3718 adds r7, #24
80029ec: 46bd mov sp, r7
80029ee: bd80 pop {r7, pc}
80029f0: 40007000 .word 0x40007000
80029f4: 40023800 .word 0x40023800
80029f8: 42470060 .word 0x42470060
080029fc <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80029fc: b580 push {r7, lr}
80029fe: b084 sub sp, #16
8002a00: af00 add r7, sp, #0
8002a02: 6078 str r0, [r7, #4]
8002a04: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002a06: 687b ldr r3, [r7, #4]
8002a08: 2b00 cmp r3, #0
8002a0a: d101 bne.n 8002a10 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8002a0c: 2301 movs r3, #1
8002a0e: e0cc b.n 8002baa <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002a10: 4b68 ldr r3, [pc, #416] ; (8002bb4 <HAL_RCC_ClockConfig+0x1b8>)
8002a12: 681b ldr r3, [r3, #0]
8002a14: f003 0307 and.w r3, r3, #7
8002a18: 683a ldr r2, [r7, #0]
8002a1a: 429a cmp r2, r3
8002a1c: d90c bls.n 8002a38 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002a1e: 4b65 ldr r3, [pc, #404] ; (8002bb4 <HAL_RCC_ClockConfig+0x1b8>)
8002a20: 683a ldr r2, [r7, #0]
8002a22: b2d2 uxtb r2, r2
8002a24: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002a26: 4b63 ldr r3, [pc, #396] ; (8002bb4 <HAL_RCC_ClockConfig+0x1b8>)
8002a28: 681b ldr r3, [r3, #0]
8002a2a: f003 0307 and.w r3, r3, #7
8002a2e: 683a ldr r2, [r7, #0]
8002a30: 429a cmp r2, r3
8002a32: d001 beq.n 8002a38 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8002a34: 2301 movs r3, #1
8002a36: e0b8 b.n 8002baa <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002a38: 687b ldr r3, [r7, #4]
8002a3a: 681b ldr r3, [r3, #0]
8002a3c: f003 0302 and.w r3, r3, #2
8002a40: 2b00 cmp r3, #0
8002a42: d020 beq.n 8002a86 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002a44: 687b ldr r3, [r7, #4]
8002a46: 681b ldr r3, [r3, #0]
8002a48: f003 0304 and.w r3, r3, #4
8002a4c: 2b00 cmp r3, #0
8002a4e: d005 beq.n 8002a5c <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8002a50: 4b59 ldr r3, [pc, #356] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002a52: 689b ldr r3, [r3, #8]
8002a54: 4a58 ldr r2, [pc, #352] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002a56: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
8002a5a: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002a5c: 687b ldr r3, [r7, #4]
8002a5e: 681b ldr r3, [r3, #0]
8002a60: f003 0308 and.w r3, r3, #8
8002a64: 2b00 cmp r3, #0
8002a66: d005 beq.n 8002a74 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8002a68: 4b53 ldr r3, [pc, #332] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002a6a: 689b ldr r3, [r3, #8]
8002a6c: 4a52 ldr r2, [pc, #328] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002a6e: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8002a72: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002a74: 4b50 ldr r3, [pc, #320] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002a76: 689b ldr r3, [r3, #8]
8002a78: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8002a7c: 687b ldr r3, [r7, #4]
8002a7e: 689b ldr r3, [r3, #8]
8002a80: 494d ldr r1, [pc, #308] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002a82: 4313 orrs r3, r2
8002a84: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002a86: 687b ldr r3, [r7, #4]
8002a88: 681b ldr r3, [r3, #0]
8002a8a: f003 0301 and.w r3, r3, #1
8002a8e: 2b00 cmp r3, #0
8002a90: d044 beq.n 8002b1c <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002a92: 687b ldr r3, [r7, #4]
8002a94: 685b ldr r3, [r3, #4]
8002a96: 2b01 cmp r3, #1
8002a98: d107 bne.n 8002aaa <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002a9a: 4b47 ldr r3, [pc, #284] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002a9c: 681b ldr r3, [r3, #0]
8002a9e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002aa2: 2b00 cmp r3, #0
8002aa4: d119 bne.n 8002ada <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002aa6: 2301 movs r3, #1
8002aa8: e07f b.n 8002baa <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8002aaa: 687b ldr r3, [r7, #4]
8002aac: 685b ldr r3, [r3, #4]
8002aae: 2b02 cmp r3, #2
8002ab0: d003 beq.n 8002aba <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8002ab6: 2b03 cmp r3, #3
8002ab8: d107 bne.n 8002aca <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002aba: 4b3f ldr r3, [pc, #252] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002abc: 681b ldr r3, [r3, #0]
8002abe: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8002ac2: 2b00 cmp r3, #0
8002ac4: d109 bne.n 8002ada <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002ac6: 2301 movs r3, #1
8002ac8: e06f b.n 8002baa <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002aca: 4b3b ldr r3, [pc, #236] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002acc: 681b ldr r3, [r3, #0]
8002ace: f003 0302 and.w r3, r3, #2
8002ad2: 2b00 cmp r3, #0
8002ad4: d101 bne.n 8002ada <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8002ad6: 2301 movs r3, #1
8002ad8: e067 b.n 8002baa <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8002ada: 4b37 ldr r3, [pc, #220] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002adc: 689b ldr r3, [r3, #8]
8002ade: f023 0203 bic.w r2, r3, #3
8002ae2: 687b ldr r3, [r7, #4]
8002ae4: 685b ldr r3, [r3, #4]
8002ae6: 4934 ldr r1, [pc, #208] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002ae8: 4313 orrs r3, r2
8002aea: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002aec: f7fe fa3c bl 8000f68 <HAL_GetTick>
8002af0: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002af2: e00a b.n 8002b0a <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002af4: f7fe fa38 bl 8000f68 <HAL_GetTick>
8002af8: 4602 mov r2, r0
8002afa: 68fb ldr r3, [r7, #12]
8002afc: 1ad3 subs r3, r2, r3
8002afe: f241 3288 movw r2, #5000 ; 0x1388
8002b02: 4293 cmp r3, r2
8002b04: d901 bls.n 8002b0a <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8002b06: 2303 movs r3, #3
8002b08: e04f b.n 8002baa <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002b0a: 4b2b ldr r3, [pc, #172] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002b0c: 689b ldr r3, [r3, #8]
8002b0e: f003 020c and.w r2, r3, #12
8002b12: 687b ldr r3, [r7, #4]
8002b14: 685b ldr r3, [r3, #4]
8002b16: 009b lsls r3, r3, #2
8002b18: 429a cmp r2, r3
8002b1a: d1eb bne.n 8002af4 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8002b1c: 4b25 ldr r3, [pc, #148] ; (8002bb4 <HAL_RCC_ClockConfig+0x1b8>)
8002b1e: 681b ldr r3, [r3, #0]
8002b20: f003 0307 and.w r3, r3, #7
8002b24: 683a ldr r2, [r7, #0]
8002b26: 429a cmp r2, r3
8002b28: d20c bcs.n 8002b44 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002b2a: 4b22 ldr r3, [pc, #136] ; (8002bb4 <HAL_RCC_ClockConfig+0x1b8>)
8002b2c: 683a ldr r2, [r7, #0]
8002b2e: b2d2 uxtb r2, r2
8002b30: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002b32: 4b20 ldr r3, [pc, #128] ; (8002bb4 <HAL_RCC_ClockConfig+0x1b8>)
8002b34: 681b ldr r3, [r3, #0]
8002b36: f003 0307 and.w r3, r3, #7
8002b3a: 683a ldr r2, [r7, #0]
8002b3c: 429a cmp r2, r3
8002b3e: d001 beq.n 8002b44 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
8002b40: 2301 movs r3, #1
8002b42: e032 b.n 8002baa <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002b44: 687b ldr r3, [r7, #4]
8002b46: 681b ldr r3, [r3, #0]
8002b48: f003 0304 and.w r3, r3, #4
8002b4c: 2b00 cmp r3, #0
8002b4e: d008 beq.n 8002b62 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002b50: 4b19 ldr r3, [pc, #100] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002b52: 689b ldr r3, [r3, #8]
8002b54: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8002b58: 687b ldr r3, [r7, #4]
8002b5a: 68db ldr r3, [r3, #12]
8002b5c: 4916 ldr r1, [pc, #88] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002b5e: 4313 orrs r3, r2
8002b60: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002b62: 687b ldr r3, [r7, #4]
8002b64: 681b ldr r3, [r3, #0]
8002b66: f003 0308 and.w r3, r3, #8
8002b6a: 2b00 cmp r3, #0
8002b6c: d009 beq.n 8002b82 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8002b6e: 4b12 ldr r3, [pc, #72] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002b70: 689b ldr r3, [r3, #8]
8002b72: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8002b76: 687b ldr r3, [r7, #4]
8002b78: 691b ldr r3, [r3, #16]
8002b7a: 00db lsls r3, r3, #3
8002b7c: 490e ldr r1, [pc, #56] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002b7e: 4313 orrs r3, r2
8002b80: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8002b82: f000 f821 bl 8002bc8 <HAL_RCC_GetSysClockFreq>
8002b86: 4602 mov r2, r0
8002b88: 4b0b ldr r3, [pc, #44] ; (8002bb8 <HAL_RCC_ClockConfig+0x1bc>)
8002b8a: 689b ldr r3, [r3, #8]
8002b8c: 091b lsrs r3, r3, #4
8002b8e: f003 030f and.w r3, r3, #15
8002b92: 490a ldr r1, [pc, #40] ; (8002bbc <HAL_RCC_ClockConfig+0x1c0>)
8002b94: 5ccb ldrb r3, [r1, r3]
8002b96: fa22 f303 lsr.w r3, r2, r3
8002b9a: 4a09 ldr r2, [pc, #36] ; (8002bc0 <HAL_RCC_ClockConfig+0x1c4>)
8002b9c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
8002b9e: 4b09 ldr r3, [pc, #36] ; (8002bc4 <HAL_RCC_ClockConfig+0x1c8>)
8002ba0: 681b ldr r3, [r3, #0]
8002ba2: 4618 mov r0, r3
8002ba4: f7fe f99c bl 8000ee0 <HAL_InitTick>
return HAL_OK;
8002ba8: 2300 movs r3, #0
}
8002baa: 4618 mov r0, r3
8002bac: 3710 adds r7, #16
8002bae: 46bd mov sp, r7
8002bb0: bd80 pop {r7, pc}
8002bb2: bf00 nop
8002bb4: 40023c00 .word 0x40023c00
8002bb8: 40023800 .word 0x40023800
8002bbc: 08005b14 .word 0x08005b14
8002bc0: 20000000 .word 0x20000000
8002bc4: 20000004 .word 0x20000004
08002bc8 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8002bc8: b5b0 push {r4, r5, r7, lr}
8002bca: b084 sub sp, #16
8002bcc: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8002bce: 2100 movs r1, #0
8002bd0: 6079 str r1, [r7, #4]
8002bd2: 2100 movs r1, #0
8002bd4: 60f9 str r1, [r7, #12]
8002bd6: 2100 movs r1, #0
8002bd8: 6039 str r1, [r7, #0]
uint32_t sysclockfreq = 0U;
8002bda: 2100 movs r1, #0
8002bdc: 60b9 str r1, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8002bde: 4952 ldr r1, [pc, #328] ; (8002d28 <HAL_RCC_GetSysClockFreq+0x160>)
8002be0: 6889 ldr r1, [r1, #8]
8002be2: f001 010c and.w r1, r1, #12
8002be6: 2908 cmp r1, #8
8002be8: d00d beq.n 8002c06 <HAL_RCC_GetSysClockFreq+0x3e>
8002bea: 2908 cmp r1, #8
8002bec: f200 8094 bhi.w 8002d18 <HAL_RCC_GetSysClockFreq+0x150>
8002bf0: 2900 cmp r1, #0
8002bf2: d002 beq.n 8002bfa <HAL_RCC_GetSysClockFreq+0x32>
8002bf4: 2904 cmp r1, #4
8002bf6: d003 beq.n 8002c00 <HAL_RCC_GetSysClockFreq+0x38>
8002bf8: e08e b.n 8002d18 <HAL_RCC_GetSysClockFreq+0x150>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8002bfa: 4b4c ldr r3, [pc, #304] ; (8002d2c <HAL_RCC_GetSysClockFreq+0x164>)
8002bfc: 60bb str r3, [r7, #8]
break;
8002bfe: e08e b.n 8002d1e <HAL_RCC_GetSysClockFreq+0x156>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8002c00: 4b4b ldr r3, [pc, #300] ; (8002d30 <HAL_RCC_GetSysClockFreq+0x168>)
8002c02: 60bb str r3, [r7, #8]
break;
8002c04: e08b b.n 8002d1e <HAL_RCC_GetSysClockFreq+0x156>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8002c06: 4948 ldr r1, [pc, #288] ; (8002d28 <HAL_RCC_GetSysClockFreq+0x160>)
8002c08: 6849 ldr r1, [r1, #4]
8002c0a: f001 013f and.w r1, r1, #63 ; 0x3f
8002c0e: 6079 str r1, [r7, #4]
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8002c10: 4945 ldr r1, [pc, #276] ; (8002d28 <HAL_RCC_GetSysClockFreq+0x160>)
8002c12: 6849 ldr r1, [r1, #4]
8002c14: f401 0180 and.w r1, r1, #4194304 ; 0x400000
8002c18: 2900 cmp r1, #0
8002c1a: d024 beq.n 8002c66 <HAL_RCC_GetSysClockFreq+0x9e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002c1c: 4942 ldr r1, [pc, #264] ; (8002d28 <HAL_RCC_GetSysClockFreq+0x160>)
8002c1e: 6849 ldr r1, [r1, #4]
8002c20: 0989 lsrs r1, r1, #6
8002c22: 4608 mov r0, r1
8002c24: f04f 0100 mov.w r1, #0
8002c28: f240 14ff movw r4, #511 ; 0x1ff
8002c2c: f04f 0500 mov.w r5, #0
8002c30: ea00 0204 and.w r2, r0, r4
8002c34: ea01 0305 and.w r3, r1, r5
8002c38: 493d ldr r1, [pc, #244] ; (8002d30 <HAL_RCC_GetSysClockFreq+0x168>)
8002c3a: fb01 f003 mul.w r0, r1, r3
8002c3e: 2100 movs r1, #0
8002c40: fb01 f102 mul.w r1, r1, r2
8002c44: 1844 adds r4, r0, r1
8002c46: 493a ldr r1, [pc, #232] ; (8002d30 <HAL_RCC_GetSysClockFreq+0x168>)
8002c48: fba2 0101 umull r0, r1, r2, r1
8002c4c: 1863 adds r3, r4, r1
8002c4e: 4619 mov r1, r3
8002c50: 687b ldr r3, [r7, #4]
8002c52: 461a mov r2, r3
8002c54: f04f 0300 mov.w r3, #0
8002c58: f7fd fabe bl 80001d8 <__aeabi_uldivmod>
8002c5c: 4602 mov r2, r0
8002c5e: 460b mov r3, r1
8002c60: 4613 mov r3, r2
8002c62: 60fb str r3, [r7, #12]
8002c64: e04a b.n 8002cfc <HAL_RCC_GetSysClockFreq+0x134>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002c66: 4b30 ldr r3, [pc, #192] ; (8002d28 <HAL_RCC_GetSysClockFreq+0x160>)
8002c68: 685b ldr r3, [r3, #4]
8002c6a: 099b lsrs r3, r3, #6
8002c6c: 461a mov r2, r3
8002c6e: f04f 0300 mov.w r3, #0
8002c72: f240 10ff movw r0, #511 ; 0x1ff
8002c76: f04f 0100 mov.w r1, #0
8002c7a: ea02 0400 and.w r4, r2, r0
8002c7e: ea03 0501 and.w r5, r3, r1
8002c82: 4620 mov r0, r4
8002c84: 4629 mov r1, r5
8002c86: f04f 0200 mov.w r2, #0
8002c8a: f04f 0300 mov.w r3, #0
8002c8e: 014b lsls r3, r1, #5
8002c90: ea43 63d0 orr.w r3, r3, r0, lsr #27
8002c94: 0142 lsls r2, r0, #5
8002c96: 4610 mov r0, r2
8002c98: 4619 mov r1, r3
8002c9a: 1b00 subs r0, r0, r4
8002c9c: eb61 0105 sbc.w r1, r1, r5
8002ca0: f04f 0200 mov.w r2, #0
8002ca4: f04f 0300 mov.w r3, #0
8002ca8: 018b lsls r3, r1, #6
8002caa: ea43 6390 orr.w r3, r3, r0, lsr #26
8002cae: 0182 lsls r2, r0, #6
8002cb0: 1a12 subs r2, r2, r0
8002cb2: eb63 0301 sbc.w r3, r3, r1
8002cb6: f04f 0000 mov.w r0, #0
8002cba: f04f 0100 mov.w r1, #0
8002cbe: 00d9 lsls r1, r3, #3
8002cc0: ea41 7152 orr.w r1, r1, r2, lsr #29
8002cc4: 00d0 lsls r0, r2, #3
8002cc6: 4602 mov r2, r0
8002cc8: 460b mov r3, r1
8002cca: 1912 adds r2, r2, r4
8002ccc: eb45 0303 adc.w r3, r5, r3
8002cd0: f04f 0000 mov.w r0, #0
8002cd4: f04f 0100 mov.w r1, #0
8002cd8: 0299 lsls r1, r3, #10
8002cda: ea41 5192 orr.w r1, r1, r2, lsr #22
8002cde: 0290 lsls r0, r2, #10
8002ce0: 4602 mov r2, r0
8002ce2: 460b mov r3, r1
8002ce4: 4610 mov r0, r2
8002ce6: 4619 mov r1, r3
8002ce8: 687b ldr r3, [r7, #4]
8002cea: 461a mov r2, r3
8002cec: f04f 0300 mov.w r3, #0
8002cf0: f7fd fa72 bl 80001d8 <__aeabi_uldivmod>
8002cf4: 4602 mov r2, r0
8002cf6: 460b mov r3, r1
8002cf8: 4613 mov r3, r2
8002cfa: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8002cfc: 4b0a ldr r3, [pc, #40] ; (8002d28 <HAL_RCC_GetSysClockFreq+0x160>)
8002cfe: 685b ldr r3, [r3, #4]
8002d00: 0c1b lsrs r3, r3, #16
8002d02: f003 0303 and.w r3, r3, #3
8002d06: 3301 adds r3, #1
8002d08: 005b lsls r3, r3, #1
8002d0a: 603b str r3, [r7, #0]
sysclockfreq = pllvco/pllp;
8002d0c: 68fa ldr r2, [r7, #12]
8002d0e: 683b ldr r3, [r7, #0]
8002d10: fbb2 f3f3 udiv r3, r2, r3
8002d14: 60bb str r3, [r7, #8]
break;
8002d16: e002 b.n 8002d1e <HAL_RCC_GetSysClockFreq+0x156>
}
default:
{
sysclockfreq = HSI_VALUE;
8002d18: 4b04 ldr r3, [pc, #16] ; (8002d2c <HAL_RCC_GetSysClockFreq+0x164>)
8002d1a: 60bb str r3, [r7, #8]
break;
8002d1c: bf00 nop
}
}
return sysclockfreq;
8002d1e: 68bb ldr r3, [r7, #8]
}
8002d20: 4618 mov r0, r3
8002d22: 3710 adds r7, #16
8002d24: 46bd mov sp, r7
8002d26: bdb0 pop {r4, r5, r7, pc}
8002d28: 40023800 .word 0x40023800
8002d2c: 00f42400 .word 0x00f42400
8002d30: 016e3600 .word 0x016e3600
08002d34 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002d34: b480 push {r7}
8002d36: af00 add r7, sp, #0
return SystemCoreClock;
8002d38: 4b03 ldr r3, [pc, #12] ; (8002d48 <HAL_RCC_GetHCLKFreq+0x14>)
8002d3a: 681b ldr r3, [r3, #0]
}
8002d3c: 4618 mov r0, r3
8002d3e: 46bd mov sp, r7
8002d40: f85d 7b04 ldr.w r7, [sp], #4
8002d44: 4770 bx lr
8002d46: bf00 nop
8002d48: 20000000 .word 0x20000000
08002d4c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002d4c: b580 push {r7, lr}
8002d4e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8002d50: f7ff fff0 bl 8002d34 <HAL_RCC_GetHCLKFreq>
8002d54: 4602 mov r2, r0
8002d56: 4b05 ldr r3, [pc, #20] ; (8002d6c <HAL_RCC_GetPCLK1Freq+0x20>)
8002d58: 689b ldr r3, [r3, #8]
8002d5a: 0a9b lsrs r3, r3, #10
8002d5c: f003 0307 and.w r3, r3, #7
8002d60: 4903 ldr r1, [pc, #12] ; (8002d70 <HAL_RCC_GetPCLK1Freq+0x24>)
8002d62: 5ccb ldrb r3, [r1, r3]
8002d64: fa22 f303 lsr.w r3, r2, r3
}
8002d68: 4618 mov r0, r3
8002d6a: bd80 pop {r7, pc}
8002d6c: 40023800 .word 0x40023800
8002d70: 08005b24 .word 0x08005b24
08002d74 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002d74: b580 push {r7, lr}
8002d76: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
8002d78: f7ff ffdc bl 8002d34 <HAL_RCC_GetHCLKFreq>
8002d7c: 4602 mov r2, r0
8002d7e: 4b05 ldr r3, [pc, #20] ; (8002d94 <HAL_RCC_GetPCLK2Freq+0x20>)
8002d80: 689b ldr r3, [r3, #8]
8002d82: 0b5b lsrs r3, r3, #13
8002d84: f003 0307 and.w r3, r3, #7
8002d88: 4903 ldr r1, [pc, #12] ; (8002d98 <HAL_RCC_GetPCLK2Freq+0x24>)
8002d8a: 5ccb ldrb r3, [r1, r3]
8002d8c: fa22 f303 lsr.w r3, r2, r3
}
8002d90: 4618 mov r0, r3
8002d92: bd80 pop {r7, pc}
8002d94: 40023800 .word 0x40023800
8002d98: 08005b24 .word 0x08005b24
08002d9c <HAL_RCCEx_PeriphCLKConfig>:
* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8002d9c: b580 push {r7, lr}
8002d9e: b086 sub sp, #24
8002da0: af00 add r7, sp, #0
8002da2: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8002da4: 2300 movs r3, #0
8002da6: 617b str r3, [r7, #20]
uint32_t tmpreg1 = 0U;
8002da8: 2300 movs r3, #0
8002daa: 613b str r3, [r7, #16]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*---------------------------- I2S configuration ---------------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
8002dac: 687b ldr r3, [r7, #4]
8002dae: 681b ldr r3, [r3, #0]
8002db0: f003 0301 and.w r3, r3, #1
8002db4: 2b00 cmp r3, #0
8002db6: d105 bne.n 8002dc4 <HAL_RCCEx_PeriphCLKConfig+0x28>
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
8002db8: 687b ldr r3, [r7, #4]
8002dba: 681b ldr r3, [r3, #0]
8002dbc: f003 0304 and.w r3, r3, #4
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
8002dc0: 2b00 cmp r3, #0
8002dc2: d038 beq.n 8002e36 <HAL_RCCEx_PeriphCLKConfig+0x9a>
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
#if defined(STM32F411xE)
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
#endif /* STM32F411xE */
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8002dc4: 4b68 ldr r3, [pc, #416] ; (8002f68 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
8002dc6: 2200 movs r2, #0
8002dc8: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002dca: f7fe f8cd bl 8000f68 <HAL_GetTick>
8002dce: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8002dd0: e008 b.n 8002de4 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
8002dd2: f7fe f8c9 bl 8000f68 <HAL_GetTick>
8002dd6: 4602 mov r2, r0
8002dd8: 697b ldr r3, [r7, #20]
8002dda: 1ad3 subs r3, r2, r3
8002ddc: 2b02 cmp r3, #2
8002dde: d901 bls.n 8002de4 <HAL_RCCEx_PeriphCLKConfig+0x48>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002de0: 2303 movs r3, #3
8002de2: e0bd b.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x1c4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8002de4: 4b61 ldr r3, [pc, #388] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002de6: 681b ldr r3, [r3, #0]
8002de8: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8002dec: 2b00 cmp r3, #0
8002dee: d1f0 bne.n 8002dd2 <HAL_RCCEx_PeriphCLKConfig+0x36>
#if defined(STM32F411xE)
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
8002df0: 687b ldr r3, [r7, #4]
8002df2: 685a ldr r2, [r3, #4]
8002df4: 687b ldr r3, [r7, #4]
8002df6: 689b ldr r3, [r3, #8]
8002df8: 019b lsls r3, r3, #6
8002dfa: 431a orrs r2, r3
8002dfc: 687b ldr r3, [r7, #4]
8002dfe: 68db ldr r3, [r3, #12]
8002e00: 071b lsls r3, r3, #28
8002e02: 495a ldr r1, [pc, #360] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002e04: 4313 orrs r3, r2
8002e06: f8c1 3084 str.w r3, [r1, #132] ; 0x84
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
#endif /* STM32F411xE */
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
8002e0a: 4b57 ldr r3, [pc, #348] ; (8002f68 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
8002e0c: 2201 movs r2, #1
8002e0e: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002e10: f7fe f8aa bl 8000f68 <HAL_GetTick>
8002e14: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8002e16: e008 b.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x8e>
{
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
8002e18: f7fe f8a6 bl 8000f68 <HAL_GetTick>
8002e1c: 4602 mov r2, r0
8002e1e: 697b ldr r3, [r7, #20]
8002e20: 1ad3 subs r3, r2, r3
8002e22: 2b02 cmp r3, #2
8002e24: d901 bls.n 8002e2a <HAL_RCCEx_PeriphCLKConfig+0x8e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8002e26: 2303 movs r3, #3
8002e28: e09a b.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x1c4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8002e2a: 4b50 ldr r3, [pc, #320] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002e2c: 681b ldr r3, [r3, #0]
8002e2e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8002e32: 2b00 cmp r3, #0
8002e34: d0f0 beq.n 8002e18 <HAL_RCCEx_PeriphCLKConfig+0x7c>
}
}
}
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
8002e36: 687b ldr r3, [r7, #4]
8002e38: 681b ldr r3, [r3, #0]
8002e3a: f003 0302 and.w r3, r3, #2
8002e3e: 2b00 cmp r3, #0
8002e40: f000 8083 beq.w 8002f4a <HAL_RCCEx_PeriphCLKConfig+0x1ae>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
8002e44: 2300 movs r3, #0
8002e46: 60fb str r3, [r7, #12]
8002e48: 4b48 ldr r3, [pc, #288] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002e4a: 6c1b ldr r3, [r3, #64] ; 0x40
8002e4c: 4a47 ldr r2, [pc, #284] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002e4e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8002e52: 6413 str r3, [r2, #64] ; 0x40
8002e54: 4b45 ldr r3, [pc, #276] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002e56: 6c1b ldr r3, [r3, #64] ; 0x40
8002e58: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002e5c: 60fb str r3, [r7, #12]
8002e5e: 68fb ldr r3, [r7, #12]
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
8002e60: 4b43 ldr r3, [pc, #268] ; (8002f70 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8002e62: 681b ldr r3, [r3, #0]
8002e64: 4a42 ldr r2, [pc, #264] ; (8002f70 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8002e66: f443 7380 orr.w r3, r3, #256 ; 0x100
8002e6a: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002e6c: f7fe f87c bl 8000f68 <HAL_GetTick>
8002e70: 6178 str r0, [r7, #20]
while((PWR->CR & PWR_CR_DBP) == RESET)
8002e72: e008 b.n 8002e86 <HAL_RCCEx_PeriphCLKConfig+0xea>
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
8002e74: f7fe f878 bl 8000f68 <HAL_GetTick>
8002e78: 4602 mov r2, r0
8002e7a: 697b ldr r3, [r7, #20]
8002e7c: 1ad3 subs r3, r2, r3
8002e7e: 2b02 cmp r3, #2
8002e80: d901 bls.n 8002e86 <HAL_RCCEx_PeriphCLKConfig+0xea>
{
return HAL_TIMEOUT;
8002e82: 2303 movs r3, #3
8002e84: e06c b.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x1c4>
while((PWR->CR & PWR_CR_DBP) == RESET)
8002e86: 4b3a ldr r3, [pc, #232] ; (8002f70 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
8002e88: 681b ldr r3, [r3, #0]
8002e8a: f403 7380 and.w r3, r3, #256 ; 0x100
8002e8e: 2b00 cmp r3, #0
8002e90: d0f0 beq.n 8002e74 <HAL_RCCEx_PeriphCLKConfig+0xd8>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
8002e92: 4b36 ldr r3, [pc, #216] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002e94: 6f1b ldr r3, [r3, #112] ; 0x70
8002e96: f403 7340 and.w r3, r3, #768 ; 0x300
8002e9a: 613b str r3, [r7, #16]
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8002e9c: 693b ldr r3, [r7, #16]
8002e9e: 2b00 cmp r3, #0
8002ea0: d02f beq.n 8002f02 <HAL_RCCEx_PeriphCLKConfig+0x166>
8002ea2: 687b ldr r3, [r7, #4]
8002ea4: 691b ldr r3, [r3, #16]
8002ea6: f403 7340 and.w r3, r3, #768 ; 0x300
8002eaa: 693a ldr r2, [r7, #16]
8002eac: 429a cmp r2, r3
8002eae: d028 beq.n 8002f02 <HAL_RCCEx_PeriphCLKConfig+0x166>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8002eb0: 4b2e ldr r3, [pc, #184] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002eb2: 6f1b ldr r3, [r3, #112] ; 0x70
8002eb4: f423 7340 bic.w r3, r3, #768 ; 0x300
8002eb8: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8002eba: 4b2e ldr r3, [pc, #184] ; (8002f74 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
8002ebc: 2201 movs r2, #1
8002ebe: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
8002ec0: 4b2c ldr r3, [pc, #176] ; (8002f74 <HAL_RCCEx_PeriphCLKConfig+0x1d8>)
8002ec2: 2200 movs r2, #0
8002ec4: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg1;
8002ec6: 4a29 ldr r2, [pc, #164] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002ec8: 693b ldr r3, [r7, #16]
8002eca: 6713 str r3, [r2, #112] ; 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8002ecc: 4b27 ldr r3, [pc, #156] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002ece: 6f1b ldr r3, [r3, #112] ; 0x70
8002ed0: f003 0301 and.w r3, r3, #1
8002ed4: 2b01 cmp r3, #1
8002ed6: d114 bne.n 8002f02 <HAL_RCCEx_PeriphCLKConfig+0x166>
{
/* Get tick */
tickstart = HAL_GetTick();
8002ed8: f7fe f846 bl 8000f68 <HAL_GetTick>
8002edc: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002ede: e00a b.n 8002ef6 <HAL_RCCEx_PeriphCLKConfig+0x15a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8002ee0: f7fe f842 bl 8000f68 <HAL_GetTick>
8002ee4: 4602 mov r2, r0
8002ee6: 697b ldr r3, [r7, #20]
8002ee8: 1ad3 subs r3, r2, r3
8002eea: f241 3288 movw r2, #5000 ; 0x1388
8002eee: 4293 cmp r3, r2
8002ef0: d901 bls.n 8002ef6 <HAL_RCCEx_PeriphCLKConfig+0x15a>
{
return HAL_TIMEOUT;
8002ef2: 2303 movs r3, #3
8002ef4: e034 b.n 8002f60 <HAL_RCCEx_PeriphCLKConfig+0x1c4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8002ef6: 4b1d ldr r3, [pc, #116] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002ef8: 6f1b ldr r3, [r3, #112] ; 0x70
8002efa: f003 0302 and.w r3, r3, #2
8002efe: 2b00 cmp r3, #0
8002f00: d0ee beq.n 8002ee0 <HAL_RCCEx_PeriphCLKConfig+0x144>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8002f02: 687b ldr r3, [r7, #4]
8002f04: 691b ldr r3, [r3, #16]
8002f06: f403 7340 and.w r3, r3, #768 ; 0x300
8002f0a: f5b3 7f40 cmp.w r3, #768 ; 0x300
8002f0e: d10d bne.n 8002f2c <HAL_RCCEx_PeriphCLKConfig+0x190>
8002f10: 4b16 ldr r3, [pc, #88] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002f12: 689b ldr r3, [r3, #8]
8002f14: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000
8002f18: 687b ldr r3, [r7, #4]
8002f1a: 691b ldr r3, [r3, #16]
8002f1c: f023 4370 bic.w r3, r3, #4026531840 ; 0xf0000000
8002f20: f423 7340 bic.w r3, r3, #768 ; 0x300
8002f24: 4911 ldr r1, [pc, #68] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002f26: 4313 orrs r3, r2
8002f28: 608b str r3, [r1, #8]
8002f2a: e005 b.n 8002f38 <HAL_RCCEx_PeriphCLKConfig+0x19c>
8002f2c: 4b0f ldr r3, [pc, #60] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002f2e: 689b ldr r3, [r3, #8]
8002f30: 4a0e ldr r2, [pc, #56] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002f32: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000
8002f36: 6093 str r3, [r2, #8]
8002f38: 4b0c ldr r3, [pc, #48] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002f3a: 6f1a ldr r2, [r3, #112] ; 0x70
8002f3c: 687b ldr r3, [r7, #4]
8002f3e: 691b ldr r3, [r3, #16]
8002f40: f3c3 030b ubfx r3, r3, #0, #12
8002f44: 4909 ldr r1, [pc, #36] ; (8002f6c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
8002f46: 4313 orrs r3, r2
8002f48: 670b str r3, [r1, #112] ; 0x70
}
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8002f4a: 687b ldr r3, [r7, #4]
8002f4c: 681b ldr r3, [r3, #0]
8002f4e: f003 0308 and.w r3, r3, #8
8002f52: 2b00 cmp r3, #0
8002f54: d003 beq.n 8002f5e <HAL_RCCEx_PeriphCLKConfig+0x1c2>
{
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8002f56: 687b ldr r3, [r7, #4]
8002f58: 7d1a ldrb r2, [r3, #20]
8002f5a: 4b07 ldr r3, [pc, #28] ; (8002f78 <HAL_RCCEx_PeriphCLKConfig+0x1dc>)
8002f5c: 601a str r2, [r3, #0]
}
#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
return HAL_OK;
8002f5e: 2300 movs r3, #0
}
8002f60: 4618 mov r0, r3
8002f62: 3718 adds r7, #24
8002f64: 46bd mov sp, r7
8002f66: bd80 pop {r7, pc}
8002f68: 42470068 .word 0x42470068
8002f6c: 40023800 .word 0x40023800
8002f70: 40007000 .word 0x40007000
8002f74: 42470e40 .word 0x42470e40
8002f78: 424711e0 .word 0x424711e0
08002f7c <HAL_RCCEx_GetPeriphCLKFreq>:
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
* @retval Frequency in KHz
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
8002f7c: b480 push {r7}
8002f7e: b087 sub sp, #28
8002f80: af00 add r7, sp, #0
8002f82: 6078 str r0, [r7, #4]
/* This variable used to store the I2S clock frequency (value in Hz) */
uint32_t frequency = 0U;
8002f84: 2300 movs r3, #0
8002f86: 617b str r3, [r7, #20]
/* This variable used to store the VCO Input (value in Hz) */
uint32_t vcoinput = 0U;
8002f88: 2300 movs r3, #0
8002f8a: 613b str r3, [r7, #16]
uint32_t srcclk = 0U;
8002f8c: 2300 movs r3, #0
8002f8e: 60fb str r3, [r7, #12]
/* This variable used to store the VCO Output (value in Hz) */
uint32_t vcooutput = 0U;
8002f90: 2300 movs r3, #0
8002f92: 60bb str r3, [r7, #8]
switch (PeriphClk)
8002f94: 687b ldr r3, [r7, #4]
8002f96: 2b01 cmp r3, #1
8002f98: d140 bne.n 800301c <HAL_RCCEx_GetPeriphCLKFreq+0xa0>
{
case RCC_PERIPHCLK_I2S:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_SOURCE();
8002f9a: 4b24 ldr r3, [pc, #144] ; (800302c <HAL_RCCEx_GetPeriphCLKFreq+0xb0>)
8002f9c: 689b ldr r3, [r3, #8]
8002f9e: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8002fa2: 60fb str r3, [r7, #12]
8002fa4: 68fb ldr r3, [r7, #12]
8002fa6: 2b00 cmp r3, #0
8002fa8: d005 beq.n 8002fb6 <HAL_RCCEx_GetPeriphCLKFreq+0x3a>
8002faa: 68fb ldr r3, [r7, #12]
8002fac: 2b01 cmp r3, #1
8002fae: d131 bne.n 8003014 <HAL_RCCEx_GetPeriphCLKFreq+0x98>
{
/* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
8002fb0: 4b1f ldr r3, [pc, #124] ; (8003030 <HAL_RCCEx_GetPeriphCLKFreq+0xb4>)
8002fb2: 617b str r3, [r7, #20]
break;
8002fb4: e031 b.n 800301a <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
case RCC_I2SCLKSOURCE_PLLI2S:
{
#if defined(STM32F411xE)
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
8002fb6: 4b1d ldr r3, [pc, #116] ; (800302c <HAL_RCCEx_GetPeriphCLKFreq+0xb0>)
8002fb8: 685b ldr r3, [r3, #4]
8002fba: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8002fbe: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8002fc2: d109 bne.n 8002fd8 <HAL_RCCEx_GetPeriphCLKFreq+0x5c>
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
8002fc4: 4b19 ldr r3, [pc, #100] ; (800302c <HAL_RCCEx_GetPeriphCLKFreq+0xb0>)
8002fc6: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8002fca: f003 033f and.w r3, r3, #63 ; 0x3f
8002fce: 4a19 ldr r2, [pc, #100] ; (8003034 <HAL_RCCEx_GetPeriphCLKFreq+0xb8>)
8002fd0: fbb2 f3f3 udiv r3, r2, r3
8002fd4: 613b str r3, [r7, #16]
8002fd6: e008 b.n 8002fea <HAL_RCCEx_GetPeriphCLKFreq+0x6e>
}
else
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
8002fd8: 4b14 ldr r3, [pc, #80] ; (800302c <HAL_RCCEx_GetPeriphCLKFreq+0xb0>)
8002fda: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8002fde: f003 033f and.w r3, r3, #63 ; 0x3f
8002fe2: 4a15 ldr r2, [pc, #84] ; (8003038 <HAL_RCCEx_GetPeriphCLKFreq+0xbc>)
8002fe4: fbb2 f3f3 udiv r3, r2, r3
8002fe8: 613b str r3, [r7, #16]
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
#endif /* STM32F411xE */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
8002fea: 4b10 ldr r3, [pc, #64] ; (800302c <HAL_RCCEx_GetPeriphCLKFreq+0xb0>)
8002fec: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8002ff0: 099b lsrs r3, r3, #6
8002ff2: f3c3 0208 ubfx r2, r3, #0, #9
8002ff6: 693b ldr r3, [r7, #16]
8002ff8: fb02 f303 mul.w r3, r2, r3
8002ffc: 60bb str r3, [r7, #8]
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
8002ffe: 4b0b ldr r3, [pc, #44] ; (800302c <HAL_RCCEx_GetPeriphCLKFreq+0xb0>)
8003000: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84
8003004: 0f1b lsrs r3, r3, #28
8003006: f003 0307 and.w r3, r3, #7
800300a: 68ba ldr r2, [r7, #8]
800300c: fbb2 f3f3 udiv r3, r2, r3
8003010: 617b str r3, [r7, #20]
break;
8003012: e002 b.n 800301a <HAL_RCCEx_GetPeriphCLKFreq+0x9e>
}
/* Clock not enabled for I2S*/
default:
{
frequency = 0U;
8003014: 2300 movs r3, #0
8003016: 617b str r3, [r7, #20]
break;
8003018: bf00 nop
}
}
break;
800301a: bf00 nop
}
}
return frequency;
800301c: 697b ldr r3, [r7, #20]
}
800301e: 4618 mov r0, r3
8003020: 371c adds r7, #28
8003022: 46bd mov sp, r7
8003024: f85d 7b04 ldr.w r7, [sp], #4
8003028: 4770 bx lr
800302a: bf00 nop
800302c: 40023800 .word 0x40023800
8003030: 00bb8000 .word 0x00bb8000
8003034: 016e3600 .word 0x016e3600
8003038: 00f42400 .word 0x00f42400
0800303c <HAL_SD_Init>:
SD_HandleTypeDef and create the associated handle.
* @param hsd: Pointer to the SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
{
800303c: b580 push {r7, lr}
800303e: b082 sub sp, #8
8003040: af00 add r7, sp, #0
8003042: 6078 str r0, [r7, #4]
/* Check the SD handle allocation */
if(hsd == NULL)
8003044: 687b ldr r3, [r7, #4]
8003046: 2b00 cmp r3, #0
8003048: d101 bne.n 800304e <HAL_SD_Init+0x12>
{
return HAL_ERROR;
800304a: 2301 movs r3, #1
800304c: e022 b.n 8003094 <HAL_SD_Init+0x58>
assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
if(hsd->State == HAL_SD_STATE_RESET)
800304e: 687b ldr r3, [r7, #4]
8003050: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
8003054: b2db uxtb r3, r3
8003056: 2b00 cmp r3, #0
8003058: d105 bne.n 8003066 <HAL_SD_Init+0x2a>
{
/* Allocate lock resource and initialize it */
hsd->Lock = HAL_UNLOCKED;
800305a: 687b ldr r3, [r7, #4]
800305c: 2200 movs r2, #0
800305e: 771a strb r2, [r3, #28]
/* Init the low level hardware */
hsd->MspInitCallback(hsd);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SD_MspInit(hsd);
8003060: 6878 ldr r0, [r7, #4]
8003062: f7fd fd2f bl 8000ac4 <HAL_SD_MspInit>
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
}
hsd->State = HAL_SD_STATE_BUSY;
8003066: 687b ldr r3, [r7, #4]
8003068: 2203 movs r2, #3
800306a: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Initialize the Card parameters */
if (HAL_SD_InitCard(hsd) != HAL_OK)
800306e: 6878 ldr r0, [r7, #4]
8003070: f000 f814 bl 800309c <HAL_SD_InitCard>
8003074: 4603 mov r3, r0
8003076: 2b00 cmp r3, #0
8003078: d001 beq.n 800307e <HAL_SD_Init+0x42>
{
return HAL_ERROR;
800307a: 2301 movs r3, #1
800307c: e00a b.n 8003094 <HAL_SD_Init+0x58>
}
/* Initialize the error code */
hsd->ErrorCode = HAL_SD_ERROR_NONE;
800307e: 687b ldr r3, [r7, #4]
8003080: 2200 movs r2, #0
8003082: 639a str r2, [r3, #56] ; 0x38
/* Initialize the SD operation */
hsd->Context = SD_CONTEXT_NONE;
8003084: 687b ldr r3, [r7, #4]
8003086: 2200 movs r2, #0
8003088: 631a str r2, [r3, #48] ; 0x30
/* Initialize the SD state */
hsd->State = HAL_SD_STATE_READY;
800308a: 687b ldr r3, [r7, #4]
800308c: 2201 movs r2, #1
800308e: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_OK;
8003092: 2300 movs r3, #0
}
8003094: 4618 mov r0, r3
8003096: 3708 adds r7, #8
8003098: 46bd mov sp, r7
800309a: bd80 pop {r7, pc}
0800309c <HAL_SD_InitCard>:
* @note This function initializes the SD card. It could be used when a card
re-initialization is needed.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
{
800309c: b5b0 push {r4, r5, r7, lr}
800309e: b08e sub sp, #56 ; 0x38
80030a0: af04 add r7, sp, #16
80030a2: 6078 str r0, [r7, #4]
uint32_t errorstate;
HAL_StatusTypeDef status;
SD_InitTypeDef Init;
/* Default SDIO peripheral configuration for SD card initialization */
Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
80030a4: 2300 movs r3, #0
80030a6: 60bb str r3, [r7, #8]
Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
80030a8: 2300 movs r3, #0
80030aa: 60fb str r3, [r7, #12]
Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
80030ac: 2300 movs r3, #0
80030ae: 613b str r3, [r7, #16]
Init.BusWide = SDIO_BUS_WIDE_1B;
80030b0: 2300 movs r3, #0
80030b2: 617b str r3, [r7, #20]
Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
80030b4: 2300 movs r3, #0
80030b6: 61bb str r3, [r7, #24]
Init.ClockDiv = SDIO_INIT_CLK_DIV;
80030b8: 2376 movs r3, #118 ; 0x76
80030ba: 61fb str r3, [r7, #28]
/* Initialize SDIO peripheral interface with default configuration */
status = SDIO_Init(hsd->Instance, Init);
80030bc: 687b ldr r3, [r7, #4]
80030be: 681d ldr r5, [r3, #0]
80030c0: 466c mov r4, sp
80030c2: f107 0314 add.w r3, r7, #20
80030c6: e893 0007 ldmia.w r3, {r0, r1, r2}
80030ca: e884 0007 stmia.w r4, {r0, r1, r2}
80030ce: f107 0308 add.w r3, r7, #8
80030d2: cb0e ldmia r3, {r1, r2, r3}
80030d4: 4628 mov r0, r5
80030d6: f001 fae5 bl 80046a4 <SDIO_Init>
80030da: 4603 mov r3, r0
80030dc: f887 3027 strb.w r3, [r7, #39] ; 0x27
if(status != HAL_OK)
80030e0: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
80030e4: 2b00 cmp r3, #0
80030e6: d001 beq.n 80030ec <HAL_SD_InitCard+0x50>
{
return HAL_ERROR;
80030e8: 2301 movs r3, #1
80030ea: e04c b.n 8003186 <HAL_SD_InitCard+0xea>
}
/* Disable SDIO Clock */
__HAL_SD_DISABLE(hsd);
80030ec: 4b28 ldr r3, [pc, #160] ; (8003190 <HAL_SD_InitCard+0xf4>)
80030ee: 2200 movs r2, #0
80030f0: 601a str r2, [r3, #0]
/* Set Power State to ON */
(void)SDIO_PowerState_ON(hsd->Instance);
80030f2: 687b ldr r3, [r7, #4]
80030f4: 681b ldr r3, [r3, #0]
80030f6: 4618 mov r0, r3
80030f8: f001 fb0c bl 8004714 <SDIO_PowerState_ON>
/* Enable SDIO Clock */
__HAL_SD_ENABLE(hsd);
80030fc: 4b24 ldr r3, [pc, #144] ; (8003190 <HAL_SD_InitCard+0xf4>)
80030fe: 2201 movs r2, #1
8003100: 601a str r2, [r3, #0]
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
8003102: 6878 ldr r0, [r7, #4]
8003104: f000 fe10 bl 8003d28 <SD_PowerON>
8003108: 6238 str r0, [r7, #32]
if(errorstate != HAL_SD_ERROR_NONE)
800310a: 6a3b ldr r3, [r7, #32]
800310c: 2b00 cmp r3, #0
800310e: d00b beq.n 8003128 <HAL_SD_InitCard+0x8c>
{
hsd->State = HAL_SD_STATE_READY;
8003110: 687b ldr r3, [r7, #4]
8003112: 2201 movs r2, #1
8003114: f883 2034 strb.w r2, [r3, #52] ; 0x34
hsd->ErrorCode |= errorstate;
8003118: 687b ldr r3, [r7, #4]
800311a: 6b9a ldr r2, [r3, #56] ; 0x38
800311c: 6a3b ldr r3, [r7, #32]
800311e: 431a orrs r2, r3
8003120: 687b ldr r3, [r7, #4]
8003122: 639a str r2, [r3, #56] ; 0x38
return HAL_ERROR;
8003124: 2301 movs r3, #1
8003126: e02e b.n 8003186 <HAL_SD_InitCard+0xea>
}
/* Card initialization */
errorstate = SD_InitCard(hsd);
8003128: 6878 ldr r0, [r7, #4]
800312a: f000 fd31 bl 8003b90 <SD_InitCard>
800312e: 6238 str r0, [r7, #32]
if(errorstate != HAL_SD_ERROR_NONE)
8003130: 6a3b ldr r3, [r7, #32]
8003132: 2b00 cmp r3, #0
8003134: d00b beq.n 800314e <HAL_SD_InitCard+0xb2>
{
hsd->State = HAL_SD_STATE_READY;
8003136: 687b ldr r3, [r7, #4]
8003138: 2201 movs r2, #1
800313a: f883 2034 strb.w r2, [r3, #52] ; 0x34
hsd->ErrorCode |= errorstate;
800313e: 687b ldr r3, [r7, #4]
8003140: 6b9a ldr r2, [r3, #56] ; 0x38
8003142: 6a3b ldr r3, [r7, #32]
8003144: 431a orrs r2, r3
8003146: 687b ldr r3, [r7, #4]
8003148: 639a str r2, [r3, #56] ; 0x38
return HAL_ERROR;
800314a: 2301 movs r3, #1
800314c: e01b b.n 8003186 <HAL_SD_InitCard+0xea>
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
800314e: 687b ldr r3, [r7, #4]
8003150: 681b ldr r3, [r3, #0]
8003152: f44f 7100 mov.w r1, #512 ; 0x200
8003156: 4618 mov r0, r3
8003158: f001 fb6f bl 800483a <SDMMC_CmdBlockLength>
800315c: 6238 str r0, [r7, #32]
if(errorstate != HAL_SD_ERROR_NONE)
800315e: 6a3b ldr r3, [r7, #32]
8003160: 2b00 cmp r3, #0
8003162: d00f beq.n 8003184 <HAL_SD_InitCard+0xe8>
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
8003164: 687b ldr r3, [r7, #4]
8003166: 681b ldr r3, [r3, #0]
8003168: 4a0a ldr r2, [pc, #40] ; (8003194 <HAL_SD_InitCard+0xf8>)
800316a: 639a str r2, [r3, #56] ; 0x38
hsd->ErrorCode |= errorstate;
800316c: 687b ldr r3, [r7, #4]
800316e: 6b9a ldr r2, [r3, #56] ; 0x38
8003170: 6a3b ldr r3, [r7, #32]
8003172: 431a orrs r2, r3
8003174: 687b ldr r3, [r7, #4]
8003176: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
8003178: 687b ldr r3, [r7, #4]
800317a: 2201 movs r2, #1
800317c: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_ERROR;
8003180: 2301 movs r3, #1
8003182: e000 b.n 8003186 <HAL_SD_InitCard+0xea>
}
return HAL_OK;
8003184: 2300 movs r3, #0
}
8003186: 4618 mov r0, r3
8003188: 3728 adds r7, #40 ; 0x28
800318a: 46bd mov sp, r7
800318c: bdb0 pop {r4, r5, r7, pc}
800318e: bf00 nop
8003190: 422580a0 .word 0x422580a0
8003194: 004005ff .word 0x004005ff
08003198 <HAL_SD_ReadBlocks_DMA>:
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
8003198: b580 push {r7, lr}
800319a: b08c sub sp, #48 ; 0x30
800319c: af00 add r7, sp, #0
800319e: 60f8 str r0, [r7, #12]
80031a0: 60b9 str r1, [r7, #8]
80031a2: 607a str r2, [r7, #4]
80031a4: 603b str r3, [r7, #0]
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
80031a6: 687b ldr r3, [r7, #4]
80031a8: 62bb str r3, [r7, #40] ; 0x28
if(NULL == pData)
80031aa: 68bb ldr r3, [r7, #8]
80031ac: 2b00 cmp r3, #0
80031ae: d107 bne.n 80031c0 <HAL_SD_ReadBlocks_DMA+0x28>
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
80031b0: 68fb ldr r3, [r7, #12]
80031b2: 6b9b ldr r3, [r3, #56] ; 0x38
80031b4: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000
80031b8: 68fb ldr r3, [r7, #12]
80031ba: 639a str r2, [r3, #56] ; 0x38
return HAL_ERROR;
80031bc: 2301 movs r3, #1
80031be: e0c0 b.n 8003342 <HAL_SD_ReadBlocks_DMA+0x1aa>
}
if(hsd->State == HAL_SD_STATE_READY)
80031c0: 68fb ldr r3, [r7, #12]
80031c2: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
80031c6: b2db uxtb r3, r3
80031c8: 2b01 cmp r3, #1
80031ca: f040 80b9 bne.w 8003340 <HAL_SD_ReadBlocks_DMA+0x1a8>
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
80031ce: 68fb ldr r3, [r7, #12]
80031d0: 2200 movs r2, #0
80031d2: 639a str r2, [r3, #56] ; 0x38
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
80031d4: 6aba ldr r2, [r7, #40] ; 0x28
80031d6: 683b ldr r3, [r7, #0]
80031d8: 441a add r2, r3
80031da: 68fb ldr r3, [r7, #12]
80031dc: 6ddb ldr r3, [r3, #92] ; 0x5c
80031de: 429a cmp r2, r3
80031e0: d907 bls.n 80031f2 <HAL_SD_ReadBlocks_DMA+0x5a>
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
80031e2: 68fb ldr r3, [r7, #12]
80031e4: 6b9b ldr r3, [r3, #56] ; 0x38
80031e6: f043 7200 orr.w r2, r3, #33554432 ; 0x2000000
80031ea: 68fb ldr r3, [r7, #12]
80031ec: 639a str r2, [r3, #56] ; 0x38
return HAL_ERROR;
80031ee: 2301 movs r3, #1
80031f0: e0a7 b.n 8003342 <HAL_SD_ReadBlocks_DMA+0x1aa>
}
hsd->State = HAL_SD_STATE_BUSY;
80031f2: 68fb ldr r3, [r7, #12]
80031f4: 2203 movs r2, #3
80031f6: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
80031fa: 68fb ldr r3, [r7, #12]
80031fc: 681b ldr r3, [r3, #0]
80031fe: 2200 movs r2, #0
8003200: 62da str r2, [r3, #44] ; 0x2c
#if defined(SDIO_STA_STBITERR)
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
8003202: 68fb ldr r3, [r7, #12]
8003204: 681b ldr r3, [r3, #0]
8003206: 6bdb ldr r3, [r3, #60] ; 0x3c
8003208: 68fa ldr r2, [r7, #12]
800320a: 6812 ldr r2, [r2, #0]
800320c: f443 734a orr.w r3, r3, #808 ; 0x328
8003210: f043 0302 orr.w r3, r3, #2
8003214: 63d3 str r3, [r2, #60] ; 0x3c
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
#endif /* SDIO_STA_STBITERR */
/* Set the DMA transfer complete callback */
hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
8003216: 68fb ldr r3, [r7, #12]
8003218: 6c1b ldr r3, [r3, #64] ; 0x40
800321a: 4a4c ldr r2, [pc, #304] ; (800334c <HAL_SD_ReadBlocks_DMA+0x1b4>)
800321c: 63da str r2, [r3, #60] ; 0x3c
/* Set the DMA error callback */
hsd->hdmarx->XferErrorCallback = SD_DMAError;
800321e: 68fb ldr r3, [r7, #12]
8003220: 6c1b ldr r3, [r3, #64] ; 0x40
8003222: 4a4b ldr r2, [pc, #300] ; (8003350 <HAL_SD_ReadBlocks_DMA+0x1b8>)
8003224: 64da str r2, [r3, #76] ; 0x4c
/* Set the DMA Abort callback */
hsd->hdmarx->XferAbortCallback = NULL;
8003226: 68fb ldr r3, [r7, #12]
8003228: 6c1b ldr r3, [r3, #64] ; 0x40
800322a: 2200 movs r2, #0
800322c: 651a str r2, [r3, #80] ; 0x50
/* Force DMA Direction */
hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY;
800322e: 68fb ldr r3, [r7, #12]
8003230: 6c1b ldr r3, [r3, #64] ; 0x40
8003232: 2200 movs r2, #0
8003234: 609a str r2, [r3, #8]
MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction);
8003236: 68fb ldr r3, [r7, #12]
8003238: 6c1b ldr r3, [r3, #64] ; 0x40
800323a: 681b ldr r3, [r3, #0]
800323c: 681b ldr r3, [r3, #0]
800323e: f023 01c0 bic.w r1, r3, #192 ; 0xc0
8003242: 68fb ldr r3, [r7, #12]
8003244: 6c1b ldr r3, [r3, #64] ; 0x40
8003246: 689a ldr r2, [r3, #8]
8003248: 68fb ldr r3, [r7, #12]
800324a: 6c1b ldr r3, [r3, #64] ; 0x40
800324c: 681b ldr r3, [r3, #0]
800324e: 430a orrs r2, r1
8003250: 601a str r2, [r3, #0]
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
8003252: 68fb ldr r3, [r7, #12]
8003254: 6c18 ldr r0, [r3, #64] ; 0x40
8003256: 68fb ldr r3, [r7, #12]
8003258: 681b ldr r3, [r3, #0]
800325a: 3380 adds r3, #128 ; 0x80
800325c: 4619 mov r1, r3
800325e: 68ba ldr r2, [r7, #8]
8003260: 683b ldr r3, [r7, #0]
8003262: 025b lsls r3, r3, #9
8003264: 089b lsrs r3, r3, #2
8003266: f7fe fa06 bl 8001676 <HAL_DMA_Start_IT>
800326a: 4603 mov r3, r0
800326c: 2b00 cmp r3, #0
800326e: d017 beq.n 80032a0 <HAL_SD_ReadBlocks_DMA+0x108>
{
__HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
8003270: 68fb ldr r3, [r7, #12]
8003272: 681b ldr r3, [r3, #0]
8003274: 6bda ldr r2, [r3, #60] ; 0x3c
8003276: 68fb ldr r3, [r7, #12]
8003278: 681b ldr r3, [r3, #0]
800327a: f422 7295 bic.w r2, r2, #298 ; 0x12a
800327e: 63da str r2, [r3, #60] ; 0x3c
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
8003280: 68fb ldr r3, [r7, #12]
8003282: 681b ldr r3, [r3, #0]
8003284: 4a33 ldr r2, [pc, #204] ; (8003354 <HAL_SD_ReadBlocks_DMA+0x1bc>)
8003286: 639a str r2, [r3, #56] ; 0x38
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
8003288: 68fb ldr r3, [r7, #12]
800328a: 6b9b ldr r3, [r3, #56] ; 0x38
800328c: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000
8003290: 68fb ldr r3, [r7, #12]
8003292: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
8003294: 68fb ldr r3, [r7, #12]
8003296: 2201 movs r2, #1
8003298: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_ERROR;
800329c: 2301 movs r3, #1
800329e: e050 b.n 8003342 <HAL_SD_ReadBlocks_DMA+0x1aa>
}
else
{
/* Enable SD DMA transfer */
__HAL_SD_DMA_ENABLE(hsd);
80032a0: 4b2d ldr r3, [pc, #180] ; (8003358 <HAL_SD_ReadBlocks_DMA+0x1c0>)
80032a2: 2201 movs r2, #1
80032a4: 601a str r2, [r3, #0]
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
80032a6: 68fb ldr r3, [r7, #12]
80032a8: 6c5b ldr r3, [r3, #68] ; 0x44
80032aa: 2b01 cmp r3, #1
80032ac: d002 beq.n 80032b4 <HAL_SD_ReadBlocks_DMA+0x11c>
{
add *= 512U;
80032ae: 6abb ldr r3, [r7, #40] ; 0x28
80032b0: 025b lsls r3, r3, #9
80032b2: 62bb str r3, [r7, #40] ; 0x28
}
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
80032b4: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80032b8: 613b str r3, [r7, #16]
config.DataLength = BLOCKSIZE * NumberOfBlocks;
80032ba: 683b ldr r3, [r7, #0]
80032bc: 025b lsls r3, r3, #9
80032be: 617b str r3, [r7, #20]
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
80032c0: 2390 movs r3, #144 ; 0x90
80032c2: 61bb str r3, [r7, #24]
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
80032c4: 2302 movs r3, #2
80032c6: 61fb str r3, [r7, #28]
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
80032c8: 2300 movs r3, #0
80032ca: 623b str r3, [r7, #32]
config.DPSM = SDIO_DPSM_ENABLE;
80032cc: 2301 movs r3, #1
80032ce: 627b str r3, [r7, #36] ; 0x24
(void)SDIO_ConfigData(hsd->Instance, &config);
80032d0: 68fb ldr r3, [r7, #12]
80032d2: 681b ldr r3, [r3, #0]
80032d4: f107 0210 add.w r2, r7, #16
80032d8: 4611 mov r1, r2
80032da: 4618 mov r0, r3
80032dc: f001 fa81 bl 80047e2 <SDIO_ConfigData>
/* Read Blocks in DMA mode */
if(NumberOfBlocks > 1U)
80032e0: 683b ldr r3, [r7, #0]
80032e2: 2b01 cmp r3, #1
80032e4: d90a bls.n 80032fc <HAL_SD_ReadBlocks_DMA+0x164>
{
hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
80032e6: 68fb ldr r3, [r7, #12]
80032e8: 2282 movs r2, #130 ; 0x82
80032ea: 631a str r2, [r3, #48] ; 0x30
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add);
80032ec: 68fb ldr r3, [r7, #12]
80032ee: 681b ldr r3, [r3, #0]
80032f0: 6ab9 ldr r1, [r7, #40] ; 0x28
80032f2: 4618 mov r0, r3
80032f4: f001 fae5 bl 80048c2 <SDMMC_CmdReadMultiBlock>
80032f8: 62f8 str r0, [r7, #44] ; 0x2c
80032fa: e009 b.n 8003310 <HAL_SD_ReadBlocks_DMA+0x178>
}
else
{
hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
80032fc: 68fb ldr r3, [r7, #12]
80032fe: 2281 movs r2, #129 ; 0x81
8003300: 631a str r2, [r3, #48] ; 0x30
/* Read Single Block command */
errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add);
8003302: 68fb ldr r3, [r7, #12]
8003304: 681b ldr r3, [r3, #0]
8003306: 6ab9 ldr r1, [r7, #40] ; 0x28
8003308: 4618 mov r0, r3
800330a: f001 fab8 bl 800487e <SDMMC_CmdReadSingleBlock>
800330e: 62f8 str r0, [r7, #44] ; 0x2c
}
if(errorstate != HAL_SD_ERROR_NONE)
8003310: 6afb ldr r3, [r7, #44] ; 0x2c
8003312: 2b00 cmp r3, #0
8003314: d012 beq.n 800333c <HAL_SD_ReadBlocks_DMA+0x1a4>
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
8003316: 68fb ldr r3, [r7, #12]
8003318: 681b ldr r3, [r3, #0]
800331a: 4a0e ldr r2, [pc, #56] ; (8003354 <HAL_SD_ReadBlocks_DMA+0x1bc>)
800331c: 639a str r2, [r3, #56] ; 0x38
hsd->ErrorCode |= errorstate;
800331e: 68fb ldr r3, [r7, #12]
8003320: 6b9a ldr r2, [r3, #56] ; 0x38
8003322: 6afb ldr r3, [r7, #44] ; 0x2c
8003324: 431a orrs r2, r3
8003326: 68fb ldr r3, [r7, #12]
8003328: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
800332a: 68fb ldr r3, [r7, #12]
800332c: 2201 movs r2, #1
800332e: f883 2034 strb.w r2, [r3, #52] ; 0x34
hsd->Context = SD_CONTEXT_NONE;
8003332: 68fb ldr r3, [r7, #12]
8003334: 2200 movs r2, #0
8003336: 631a str r2, [r3, #48] ; 0x30
return HAL_ERROR;
8003338: 2301 movs r3, #1
800333a: e002 b.n 8003342 <HAL_SD_ReadBlocks_DMA+0x1aa>
}
return HAL_OK;
800333c: 2300 movs r3, #0
800333e: e000 b.n 8003342 <HAL_SD_ReadBlocks_DMA+0x1aa>
}
}
else
{
return HAL_BUSY;
8003340: 2302 movs r3, #2
}
}
8003342: 4618 mov r0, r3
8003344: 3730 adds r7, #48 ; 0x30
8003346: 46bd mov sp, r7
8003348: bd80 pop {r7, pc}
800334a: bf00 nop
800334c: 08003a7b .word 0x08003a7b
8003350: 08003aed .word 0x08003aed
8003354: 004005ff .word 0x004005ff
8003358: 4225858c .word 0x4225858c
0800335c <HAL_SD_WriteBlocks_DMA>:
* @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
800335c: b580 push {r7, lr}
800335e: b08c sub sp, #48 ; 0x30
8003360: af00 add r7, sp, #0
8003362: 60f8 str r0, [r7, #12]
8003364: 60b9 str r1, [r7, #8]
8003366: 607a str r2, [r7, #4]
8003368: 603b str r3, [r7, #0]
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t add = BlockAdd;
800336a: 687b ldr r3, [r7, #4]
800336c: 62bb str r3, [r7, #40] ; 0x28
if(NULL == pData)
800336e: 68bb ldr r3, [r7, #8]
8003370: 2b00 cmp r3, #0
8003372: d107 bne.n 8003384 <HAL_SD_WriteBlocks_DMA+0x28>
{
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
8003374: 68fb ldr r3, [r7, #12]
8003376: 6b9b ldr r3, [r3, #56] ; 0x38
8003378: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000
800337c: 68fb ldr r3, [r7, #12]
800337e: 639a str r2, [r3, #56] ; 0x38
return HAL_ERROR;
8003380: 2301 movs r3, #1
8003382: e0c5 b.n 8003510 <HAL_SD_WriteBlocks_DMA+0x1b4>
}
if(hsd->State == HAL_SD_STATE_READY)
8003384: 68fb ldr r3, [r7, #12]
8003386: f893 3034 ldrb.w r3, [r3, #52] ; 0x34
800338a: b2db uxtb r3, r3
800338c: 2b01 cmp r3, #1
800338e: f040 80be bne.w 800350e <HAL_SD_WriteBlocks_DMA+0x1b2>
{
hsd->ErrorCode = HAL_SD_ERROR_NONE;
8003392: 68fb ldr r3, [r7, #12]
8003394: 2200 movs r2, #0
8003396: 639a str r2, [r3, #56] ; 0x38
if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
8003398: 6aba ldr r2, [r7, #40] ; 0x28
800339a: 683b ldr r3, [r7, #0]
800339c: 441a add r2, r3
800339e: 68fb ldr r3, [r7, #12]
80033a0: 6ddb ldr r3, [r3, #92] ; 0x5c
80033a2: 429a cmp r2, r3
80033a4: d907 bls.n 80033b6 <HAL_SD_WriteBlocks_DMA+0x5a>
{
hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
80033a6: 68fb ldr r3, [r7, #12]
80033a8: 6b9b ldr r3, [r3, #56] ; 0x38
80033aa: f043 7200 orr.w r2, r3, #33554432 ; 0x2000000
80033ae: 68fb ldr r3, [r7, #12]
80033b0: 639a str r2, [r3, #56] ; 0x38
return HAL_ERROR;
80033b2: 2301 movs r3, #1
80033b4: e0ac b.n 8003510 <HAL_SD_WriteBlocks_DMA+0x1b4>
}
hsd->State = HAL_SD_STATE_BUSY;
80033b6: 68fb ldr r3, [r7, #12]
80033b8: 2203 movs r2, #3
80033ba: f883 2034 strb.w r2, [r3, #52] ; 0x34
/* Initialize data control register */
hsd->Instance->DCTRL = 0U;
80033be: 68fb ldr r3, [r7, #12]
80033c0: 681b ldr r3, [r3, #0]
80033c2: 2200 movs r2, #0
80033c4: 62da str r2, [r3, #44] ; 0x2c
/* Enable SD Error interrupts */
#if defined(SDIO_STA_STBITERR)
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
80033c6: 68fb ldr r3, [r7, #12]
80033c8: 681b ldr r3, [r3, #0]
80033ca: 6bdb ldr r3, [r3, #60] ; 0x3c
80033cc: 68fa ldr r2, [r7, #12]
80033ce: 6812 ldr r2, [r2, #0]
80033d0: f443 7306 orr.w r3, r3, #536 ; 0x218
80033d4: f043 0302 orr.w r3, r3, #2
80033d8: 63d3 str r3, [r2, #60] ; 0x3c
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
#endif /* SDIO_STA_STBITERR */
/* Set the DMA transfer complete callback */
hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
80033da: 68fb ldr r3, [r7, #12]
80033dc: 6bdb ldr r3, [r3, #60] ; 0x3c
80033de: 4a4e ldr r2, [pc, #312] ; (8003518 <HAL_SD_WriteBlocks_DMA+0x1bc>)
80033e0: 63da str r2, [r3, #60] ; 0x3c
/* Set the DMA error callback */
hsd->hdmatx->XferErrorCallback = SD_DMAError;
80033e2: 68fb ldr r3, [r7, #12]
80033e4: 6bdb ldr r3, [r3, #60] ; 0x3c
80033e6: 4a4d ldr r2, [pc, #308] ; (800351c <HAL_SD_WriteBlocks_DMA+0x1c0>)
80033e8: 64da str r2, [r3, #76] ; 0x4c
/* Set the DMA Abort callback */
hsd->hdmatx->XferAbortCallback = NULL;
80033ea: 68fb ldr r3, [r7, #12]
80033ec: 6bdb ldr r3, [r3, #60] ; 0x3c
80033ee: 2200 movs r2, #0
80033f0: 651a str r2, [r3, #80] ; 0x50
if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
80033f2: 68fb ldr r3, [r7, #12]
80033f4: 6c5b ldr r3, [r3, #68] ; 0x44
80033f6: 2b01 cmp r3, #1
80033f8: d002 beq.n 8003400 <HAL_SD_WriteBlocks_DMA+0xa4>
{
add *= 512U;
80033fa: 6abb ldr r3, [r7, #40] ; 0x28
80033fc: 025b lsls r3, r3, #9
80033fe: 62bb str r3, [r7, #40] ; 0x28
}
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
8003400: 683b ldr r3, [r7, #0]
8003402: 2b01 cmp r3, #1
8003404: d90a bls.n 800341c <HAL_SD_WriteBlocks_DMA+0xc0>
{
hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
8003406: 68fb ldr r3, [r7, #12]
8003408: 22a0 movs r2, #160 ; 0xa0
800340a: 631a str r2, [r3, #48] ; 0x30
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
800340c: 68fb ldr r3, [r7, #12]
800340e: 681b ldr r3, [r3, #0]
8003410: 6ab9 ldr r1, [r7, #40] ; 0x28
8003412: 4618 mov r0, r3
8003414: f001 fa99 bl 800494a <SDMMC_CmdWriteMultiBlock>
8003418: 62f8 str r0, [r7, #44] ; 0x2c
800341a: e009 b.n 8003430 <HAL_SD_WriteBlocks_DMA+0xd4>
}
else
{
hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
800341c: 68fb ldr r3, [r7, #12]
800341e: 2290 movs r2, #144 ; 0x90
8003420: 631a str r2, [r3, #48] ; 0x30
/* Write Single Block command */
errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add);
8003422: 68fb ldr r3, [r7, #12]
8003424: 681b ldr r3, [r3, #0]
8003426: 6ab9 ldr r1, [r7, #40] ; 0x28
8003428: 4618 mov r0, r3
800342a: f001 fa6c bl 8004906 <SDMMC_CmdWriteSingleBlock>
800342e: 62f8 str r0, [r7, #44] ; 0x2c
}
if(errorstate != HAL_SD_ERROR_NONE)
8003430: 6afb ldr r3, [r7, #44] ; 0x2c
8003432: 2b00 cmp r3, #0
8003434: d012 beq.n 800345c <HAL_SD_WriteBlocks_DMA+0x100>
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
8003436: 68fb ldr r3, [r7, #12]
8003438: 681b ldr r3, [r3, #0]
800343a: 4a39 ldr r2, [pc, #228] ; (8003520 <HAL_SD_WriteBlocks_DMA+0x1c4>)
800343c: 639a str r2, [r3, #56] ; 0x38
hsd->ErrorCode |= errorstate;
800343e: 68fb ldr r3, [r7, #12]
8003440: 6b9a ldr r2, [r3, #56] ; 0x38
8003442: 6afb ldr r3, [r7, #44] ; 0x2c
8003444: 431a orrs r2, r3
8003446: 68fb ldr r3, [r7, #12]
8003448: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
800344a: 68fb ldr r3, [r7, #12]
800344c: 2201 movs r2, #1
800344e: f883 2034 strb.w r2, [r3, #52] ; 0x34
hsd->Context = SD_CONTEXT_NONE;
8003452: 68fb ldr r3, [r7, #12]
8003454: 2200 movs r2, #0
8003456: 631a str r2, [r3, #48] ; 0x30
return HAL_ERROR;
8003458: 2301 movs r3, #1
800345a: e059 b.n 8003510 <HAL_SD_WriteBlocks_DMA+0x1b4>
}
/* Enable SDIO DMA transfer */
__HAL_SD_DMA_ENABLE(hsd);
800345c: 4b31 ldr r3, [pc, #196] ; (8003524 <HAL_SD_WriteBlocks_DMA+0x1c8>)
800345e: 2201 movs r2, #1
8003460: 601a str r2, [r3, #0]
/* Force DMA Direction */
hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH;
8003462: 68fb ldr r3, [r7, #12]
8003464: 6bdb ldr r3, [r3, #60] ; 0x3c
8003466: 2240 movs r2, #64 ; 0x40
8003468: 609a str r2, [r3, #8]
MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction);
800346a: 68fb ldr r3, [r7, #12]
800346c: 6bdb ldr r3, [r3, #60] ; 0x3c
800346e: 681b ldr r3, [r3, #0]
8003470: 681b ldr r3, [r3, #0]
8003472: f023 01c0 bic.w r1, r3, #192 ; 0xc0
8003476: 68fb ldr r3, [r7, #12]
8003478: 6bdb ldr r3, [r3, #60] ; 0x3c
800347a: 689a ldr r2, [r3, #8]
800347c: 68fb ldr r3, [r7, #12]
800347e: 6bdb ldr r3, [r3, #60] ; 0x3c
8003480: 681b ldr r3, [r3, #0]
8003482: 430a orrs r2, r1
8003484: 601a str r2, [r3, #0]
/* Enable the DMA Channel */
if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
8003486: 68fb ldr r3, [r7, #12]
8003488: 6bd8 ldr r0, [r3, #60] ; 0x3c
800348a: 68b9 ldr r1, [r7, #8]
800348c: 68fb ldr r3, [r7, #12]
800348e: 681b ldr r3, [r3, #0]
8003490: 3380 adds r3, #128 ; 0x80
8003492: 461a mov r2, r3
8003494: 683b ldr r3, [r7, #0]
8003496: 025b lsls r3, r3, #9
8003498: 089b lsrs r3, r3, #2
800349a: f7fe f8ec bl 8001676 <HAL_DMA_Start_IT>
800349e: 4603 mov r3, r0
80034a0: 2b00 cmp r3, #0
80034a2: d01c beq.n 80034de <HAL_SD_WriteBlocks_DMA+0x182>
{
#if defined(SDIO_STA_STBITERR)
__HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
80034a4: 68fb ldr r3, [r7, #12]
80034a6: 681b ldr r3, [r3, #0]
80034a8: 6bdb ldr r3, [r3, #60] ; 0x3c
80034aa: 68fa ldr r2, [r7, #12]
80034ac: 6812 ldr r2, [r2, #0]
80034ae: f423 7306 bic.w r3, r3, #536 ; 0x218
80034b2: f023 0302 bic.w r3, r3, #2
80034b6: 63d3 str r3, [r2, #60] ; 0x3c
#else /* SDIO_STA_STBITERR not defined */
__HAL_SD_DISABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
#endif /* SDIO_STA_STBITERR */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
80034b8: 68fb ldr r3, [r7, #12]
80034ba: 681b ldr r3, [r3, #0]
80034bc: 4a18 ldr r2, [pc, #96] ; (8003520 <HAL_SD_WriteBlocks_DMA+0x1c4>)
80034be: 639a str r2, [r3, #56] ; 0x38
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
80034c0: 68fb ldr r3, [r7, #12]
80034c2: 6b9b ldr r3, [r3, #56] ; 0x38
80034c4: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000
80034c8: 68fb ldr r3, [r7, #12]
80034ca: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
80034cc: 68fb ldr r3, [r7, #12]
80034ce: 2201 movs r2, #1
80034d0: f883 2034 strb.w r2, [r3, #52] ; 0x34
hsd->Context = SD_CONTEXT_NONE;
80034d4: 68fb ldr r3, [r7, #12]
80034d6: 2200 movs r2, #0
80034d8: 631a str r2, [r3, #48] ; 0x30
return HAL_ERROR;
80034da: 2301 movs r3, #1
80034dc: e018 b.n 8003510 <HAL_SD_WriteBlocks_DMA+0x1b4>
}
else
{
/* Configure the SD DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
80034de: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
80034e2: 613b str r3, [r7, #16]
config.DataLength = BLOCKSIZE * NumberOfBlocks;
80034e4: 683b ldr r3, [r7, #0]
80034e6: 025b lsls r3, r3, #9
80034e8: 617b str r3, [r7, #20]
config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
80034ea: 2390 movs r3, #144 ; 0x90
80034ec: 61bb str r3, [r7, #24]
config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
80034ee: 2300 movs r3, #0
80034f0: 61fb str r3, [r7, #28]
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
80034f2: 2300 movs r3, #0
80034f4: 623b str r3, [r7, #32]
config.DPSM = SDIO_DPSM_ENABLE;
80034f6: 2301 movs r3, #1
80034f8: 627b str r3, [r7, #36] ; 0x24
(void)SDIO_ConfigData(hsd->Instance, &config);
80034fa: 68fb ldr r3, [r7, #12]
80034fc: 681b ldr r3, [r3, #0]
80034fe: f107 0210 add.w r2, r7, #16
8003502: 4611 mov r1, r2
8003504: 4618 mov r0, r3
8003506: f001 f96c bl 80047e2 <SDIO_ConfigData>
return HAL_OK;
800350a: 2300 movs r3, #0
800350c: e000 b.n 8003510 <HAL_SD_WriteBlocks_DMA+0x1b4>
}
}
else
{
return HAL_BUSY;
800350e: 2302 movs r3, #2
}
}
8003510: 4618 mov r0, r3
8003512: 3730 adds r7, #48 ; 0x30
8003514: 46bd mov sp, r7
8003516: bd80 pop {r7, pc}
8003518: 08003a51 .word 0x08003a51
800351c: 08003aed .word 0x08003aed
8003520: 004005ff .word 0x004005ff
8003524: 4225858c .word 0x4225858c
08003528 <HAL_SD_ErrorCallback>:
* @brief SD error callbacks
* @param hsd: Pointer SD handle
* @retval None
*/
__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
{
8003528: b480 push {r7}
800352a: b083 sub sp, #12
800352c: af00 add r7, sp, #0
800352e: 6078 str r0, [r7, #4]
UNUSED(hsd);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_SD_ErrorCallback can be implemented in the user file
*/
}
8003530: bf00 nop
8003532: 370c adds r7, #12
8003534: 46bd mov sp, r7
8003536: f85d 7b04 ldr.w r7, [sp], #4
800353a: 4770 bx lr
0800353c <HAL_SD_GetCardCSD>:
* @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
{
800353c: b480 push {r7}
800353e: b083 sub sp, #12
8003540: af00 add r7, sp, #0
8003542: 6078 str r0, [r7, #4]
8003544: 6039 str r1, [r7, #0]
pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U);
8003546: 687b ldr r3, [r7, #4]
8003548: 6e5b ldr r3, [r3, #100] ; 0x64
800354a: 0f9b lsrs r3, r3, #30
800354c: b2da uxtb r2, r3
800354e: 683b ldr r3, [r7, #0]
8003550: 701a strb r2, [r3, #0]
pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U);
8003552: 687b ldr r3, [r7, #4]
8003554: 6e5b ldr r3, [r3, #100] ; 0x64
8003556: 0e9b lsrs r3, r3, #26
8003558: b2db uxtb r3, r3
800355a: f003 030f and.w r3, r3, #15
800355e: b2da uxtb r2, r3
8003560: 683b ldr r3, [r7, #0]
8003562: 705a strb r2, [r3, #1]
pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U);
8003564: 687b ldr r3, [r7, #4]
8003566: 6e5b ldr r3, [r3, #100] ; 0x64
8003568: 0e1b lsrs r3, r3, #24
800356a: b2db uxtb r3, r3
800356c: f003 0303 and.w r3, r3, #3
8003570: b2da uxtb r2, r3
8003572: 683b ldr r3, [r7, #0]
8003574: 709a strb r2, [r3, #2]
pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U);
8003576: 687b ldr r3, [r7, #4]
8003578: 6e5b ldr r3, [r3, #100] ; 0x64
800357a: 0c1b lsrs r3, r3, #16
800357c: b2da uxtb r2, r3
800357e: 683b ldr r3, [r7, #0]
8003580: 70da strb r2, [r3, #3]
pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U);
8003582: 687b ldr r3, [r7, #4]
8003584: 6e5b ldr r3, [r3, #100] ; 0x64
8003586: 0a1b lsrs r3, r3, #8
8003588: b2da uxtb r2, r3
800358a: 683b ldr r3, [r7, #0]
800358c: 711a strb r2, [r3, #4]
pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU);
800358e: 687b ldr r3, [r7, #4]
8003590: 6e5b ldr r3, [r3, #100] ; 0x64
8003592: b2da uxtb r2, r3
8003594: 683b ldr r3, [r7, #0]
8003596: 715a strb r2, [r3, #5]
pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U);
8003598: 687b ldr r3, [r7, #4]
800359a: 6e9b ldr r3, [r3, #104] ; 0x68
800359c: 0d1b lsrs r3, r3, #20
800359e: b29a uxth r2, r3
80035a0: 683b ldr r3, [r7, #0]
80035a2: 80da strh r2, [r3, #6]
pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U);
80035a4: 687b ldr r3, [r7, #4]
80035a6: 6e9b ldr r3, [r3, #104] ; 0x68
80035a8: 0c1b lsrs r3, r3, #16
80035aa: b2db uxtb r3, r3
80035ac: f003 030f and.w r3, r3, #15
80035b0: b2da uxtb r2, r3
80035b2: 683b ldr r3, [r7, #0]
80035b4: 721a strb r2, [r3, #8]
pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U);
80035b6: 687b ldr r3, [r7, #4]
80035b8: 6e9b ldr r3, [r3, #104] ; 0x68
80035ba: 0bdb lsrs r3, r3, #15
80035bc: b2db uxtb r3, r3
80035be: f003 0301 and.w r3, r3, #1
80035c2: b2da uxtb r2, r3
80035c4: 683b ldr r3, [r7, #0]
80035c6: 725a strb r2, [r3, #9]
pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U);
80035c8: 687b ldr r3, [r7, #4]
80035ca: 6e9b ldr r3, [r3, #104] ; 0x68
80035cc: 0b9b lsrs r3, r3, #14
80035ce: b2db uxtb r3, r3
80035d0: f003 0301 and.w r3, r3, #1
80035d4: b2da uxtb r2, r3
80035d6: 683b ldr r3, [r7, #0]
80035d8: 729a strb r2, [r3, #10]
pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U);
80035da: 687b ldr r3, [r7, #4]
80035dc: 6e9b ldr r3, [r3, #104] ; 0x68
80035de: 0b5b lsrs r3, r3, #13
80035e0: b2db uxtb r3, r3
80035e2: f003 0301 and.w r3, r3, #1
80035e6: b2da uxtb r2, r3
80035e8: 683b ldr r3, [r7, #0]
80035ea: 72da strb r2, [r3, #11]
pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U);
80035ec: 687b ldr r3, [r7, #4]
80035ee: 6e9b ldr r3, [r3, #104] ; 0x68
80035f0: 0b1b lsrs r3, r3, #12
80035f2: b2db uxtb r3, r3
80035f4: f003 0301 and.w r3, r3, #1
80035f8: b2da uxtb r2, r3
80035fa: 683b ldr r3, [r7, #0]
80035fc: 731a strb r2, [r3, #12]
pCSD->Reserved2 = 0U; /*!< Reserved */
80035fe: 683b ldr r3, [r7, #0]
8003600: 2200 movs r2, #0
8003602: 735a strb r2, [r3, #13]
if(hsd->SdCard.CardType == CARD_SDSC)
8003604: 687b ldr r3, [r7, #4]
8003606: 6c5b ldr r3, [r3, #68] ; 0x44
8003608: 2b00 cmp r3, #0
800360a: d163 bne.n 80036d4 <HAL_SD_GetCardCSD+0x198>
{
pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U));
800360c: 687b ldr r3, [r7, #4]
800360e: 6e9b ldr r3, [r3, #104] ; 0x68
8003610: 009a lsls r2, r3, #2
8003612: f640 73fc movw r3, #4092 ; 0xffc
8003616: 4013 ands r3, r2
8003618: 687a ldr r2, [r7, #4]
800361a: 6ed2 ldr r2, [r2, #108] ; 0x6c
800361c: 0f92 lsrs r2, r2, #30
800361e: 431a orrs r2, r3
8003620: 683b ldr r3, [r7, #0]
8003622: 611a str r2, [r3, #16]
pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U);
8003624: 687b ldr r3, [r7, #4]
8003626: 6edb ldr r3, [r3, #108] ; 0x6c
8003628: 0edb lsrs r3, r3, #27
800362a: b2db uxtb r3, r3
800362c: f003 0307 and.w r3, r3, #7
8003630: b2da uxtb r2, r3
8003632: 683b ldr r3, [r7, #0]
8003634: 751a strb r2, [r3, #20]
pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U);
8003636: 687b ldr r3, [r7, #4]
8003638: 6edb ldr r3, [r3, #108] ; 0x6c
800363a: 0e1b lsrs r3, r3, #24
800363c: b2db uxtb r3, r3
800363e: f003 0307 and.w r3, r3, #7
8003642: b2da uxtb r2, r3
8003644: 683b ldr r3, [r7, #0]
8003646: 755a strb r2, [r3, #21]
pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U);
8003648: 687b ldr r3, [r7, #4]
800364a: 6edb ldr r3, [r3, #108] ; 0x6c
800364c: 0d5b lsrs r3, r3, #21
800364e: b2db uxtb r3, r3
8003650: f003 0307 and.w r3, r3, #7
8003654: b2da uxtb r2, r3
8003656: 683b ldr r3, [r7, #0]
8003658: 759a strb r2, [r3, #22]
pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U);
800365a: 687b ldr r3, [r7, #4]
800365c: 6edb ldr r3, [r3, #108] ; 0x6c
800365e: 0c9b lsrs r3, r3, #18
8003660: b2db uxtb r3, r3
8003662: f003 0307 and.w r3, r3, #7
8003666: b2da uxtb r2, r3
8003668: 683b ldr r3, [r7, #0]
800366a: 75da strb r2, [r3, #23]
pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U);
800366c: 687b ldr r3, [r7, #4]
800366e: 6edb ldr r3, [r3, #108] ; 0x6c
8003670: 0bdb lsrs r3, r3, #15
8003672: b2db uxtb r3, r3
8003674: f003 0307 and.w r3, r3, #7
8003678: b2da uxtb r2, r3
800367a: 683b ldr r3, [r7, #0]
800367c: 761a strb r2, [r3, #24]
hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
800367e: 683b ldr r3, [r7, #0]
8003680: 691b ldr r3, [r3, #16]
8003682: 1c5a adds r2, r3, #1
8003684: 687b ldr r3, [r7, #4]
8003686: 655a str r2, [r3, #84] ; 0x54
hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U));
8003688: 683b ldr r3, [r7, #0]
800368a: 7e1b ldrb r3, [r3, #24]
800368c: b2db uxtb r3, r3
800368e: f003 0307 and.w r3, r3, #7
8003692: 3302 adds r3, #2
8003694: 2201 movs r2, #1
8003696: fa02 f303 lsl.w r3, r2, r3
800369a: 687a ldr r2, [r7, #4]
800369c: 6d52 ldr r2, [r2, #84] ; 0x54
800369e: fb02 f203 mul.w r2, r2, r3
80036a2: 687b ldr r3, [r7, #4]
80036a4: 655a str r2, [r3, #84] ; 0x54
hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU));
80036a6: 683b ldr r3, [r7, #0]
80036a8: 7a1b ldrb r3, [r3, #8]
80036aa: b2db uxtb r3, r3
80036ac: f003 030f and.w r3, r3, #15
80036b0: 2201 movs r2, #1
80036b2: 409a lsls r2, r3
80036b4: 687b ldr r3, [r7, #4]
80036b6: 659a str r2, [r3, #88] ; 0x58
hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
80036b8: 687b ldr r3, [r7, #4]
80036ba: 6d5b ldr r3, [r3, #84] ; 0x54
80036bc: 687a ldr r2, [r7, #4]
80036be: 6d92 ldr r2, [r2, #88] ; 0x58
80036c0: 0a52 lsrs r2, r2, #9
80036c2: fb02 f203 mul.w r2, r2, r3
80036c6: 687b ldr r3, [r7, #4]
80036c8: 65da str r2, [r3, #92] ; 0x5c
hsd->SdCard.LogBlockSize = 512U;
80036ca: 687b ldr r3, [r7, #4]
80036cc: f44f 7200 mov.w r2, #512 ; 0x200
80036d0: 661a str r2, [r3, #96] ; 0x60
80036d2: e031 b.n 8003738 <HAL_SD_GetCardCSD+0x1fc>
}
else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
80036d4: 687b ldr r3, [r7, #4]
80036d6: 6c5b ldr r3, [r3, #68] ; 0x44
80036d8: 2b01 cmp r3, #1
80036da: d11d bne.n 8003718 <HAL_SD_GetCardCSD+0x1dc>
{
/* Byte 7 */
pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U));
80036dc: 687b ldr r3, [r7, #4]
80036de: 6e9b ldr r3, [r3, #104] ; 0x68
80036e0: 041b lsls r3, r3, #16
80036e2: f403 127c and.w r2, r3, #4128768 ; 0x3f0000
80036e6: 687b ldr r3, [r7, #4]
80036e8: 6edb ldr r3, [r3, #108] ; 0x6c
80036ea: 0c1b lsrs r3, r3, #16
80036ec: 431a orrs r2, r3
80036ee: 683b ldr r3, [r7, #0]
80036f0: 611a str r2, [r3, #16]
hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U);
80036f2: 683b ldr r3, [r7, #0]
80036f4: 691b ldr r3, [r3, #16]
80036f6: 3301 adds r3, #1
80036f8: 029a lsls r2, r3, #10
80036fa: 687b ldr r3, [r7, #4]
80036fc: 655a str r2, [r3, #84] ; 0x54
hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr;
80036fe: 687b ldr r3, [r7, #4]
8003700: 6d5a ldr r2, [r3, #84] ; 0x54
8003702: 687b ldr r3, [r7, #4]
8003704: 65da str r2, [r3, #92] ; 0x5c
hsd->SdCard.BlockSize = 512U;
8003706: 687b ldr r3, [r7, #4]
8003708: f44f 7200 mov.w r2, #512 ; 0x200
800370c: 659a str r2, [r3, #88] ; 0x58
hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize;
800370e: 687b ldr r3, [r7, #4]
8003710: 6d9a ldr r2, [r3, #88] ; 0x58
8003712: 687b ldr r3, [r7, #4]
8003714: 661a str r2, [r3, #96] ; 0x60
8003716: e00f b.n 8003738 <HAL_SD_GetCardCSD+0x1fc>
}
else
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
8003718: 687b ldr r3, [r7, #4]
800371a: 681b ldr r3, [r3, #0]
800371c: 4a58 ldr r2, [pc, #352] ; (8003880 <HAL_SD_GetCardCSD+0x344>)
800371e: 639a str r2, [r3, #56] ; 0x38
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
8003720: 687b ldr r3, [r7, #4]
8003722: 6b9b ldr r3, [r3, #56] ; 0x38
8003724: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000
8003728: 687b ldr r3, [r7, #4]
800372a: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
800372c: 687b ldr r3, [r7, #4]
800372e: 2201 movs r2, #1
8003730: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_ERROR;
8003734: 2301 movs r3, #1
8003736: e09d b.n 8003874 <HAL_SD_GetCardCSD+0x338>
}
pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U);
8003738: 687b ldr r3, [r7, #4]
800373a: 6edb ldr r3, [r3, #108] ; 0x6c
800373c: 0b9b lsrs r3, r3, #14
800373e: b2db uxtb r3, r3
8003740: f003 0301 and.w r3, r3, #1
8003744: b2da uxtb r2, r3
8003746: 683b ldr r3, [r7, #0]
8003748: 765a strb r2, [r3, #25]
pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U);
800374a: 687b ldr r3, [r7, #4]
800374c: 6edb ldr r3, [r3, #108] ; 0x6c
800374e: 09db lsrs r3, r3, #7
8003750: b2db uxtb r3, r3
8003752: f003 037f and.w r3, r3, #127 ; 0x7f
8003756: b2da uxtb r2, r3
8003758: 683b ldr r3, [r7, #0]
800375a: 769a strb r2, [r3, #26]
pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU);
800375c: 687b ldr r3, [r7, #4]
800375e: 6edb ldr r3, [r3, #108] ; 0x6c
8003760: b2db uxtb r3, r3
8003762: f003 037f and.w r3, r3, #127 ; 0x7f
8003766: b2da uxtb r2, r3
8003768: 683b ldr r3, [r7, #0]
800376a: 76da strb r2, [r3, #27]
pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U);
800376c: 687b ldr r3, [r7, #4]
800376e: 6f1b ldr r3, [r3, #112] ; 0x70
8003770: 0fdb lsrs r3, r3, #31
8003772: b2da uxtb r2, r3
8003774: 683b ldr r3, [r7, #0]
8003776: 771a strb r2, [r3, #28]
pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U);
8003778: 687b ldr r3, [r7, #4]
800377a: 6f1b ldr r3, [r3, #112] ; 0x70
800377c: 0f5b lsrs r3, r3, #29
800377e: b2db uxtb r3, r3
8003780: f003 0303 and.w r3, r3, #3
8003784: b2da uxtb r2, r3
8003786: 683b ldr r3, [r7, #0]
8003788: 775a strb r2, [r3, #29]
pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U);
800378a: 687b ldr r3, [r7, #4]
800378c: 6f1b ldr r3, [r3, #112] ; 0x70
800378e: 0e9b lsrs r3, r3, #26
8003790: b2db uxtb r3, r3
8003792: f003 0307 and.w r3, r3, #7
8003796: b2da uxtb r2, r3
8003798: 683b ldr r3, [r7, #0]
800379a: 779a strb r2, [r3, #30]
pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U);
800379c: 687b ldr r3, [r7, #4]
800379e: 6f1b ldr r3, [r3, #112] ; 0x70
80037a0: 0d9b lsrs r3, r3, #22
80037a2: b2db uxtb r3, r3
80037a4: f003 030f and.w r3, r3, #15
80037a8: b2da uxtb r2, r3
80037aa: 683b ldr r3, [r7, #0]
80037ac: 77da strb r2, [r3, #31]
pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U);
80037ae: 687b ldr r3, [r7, #4]
80037b0: 6f1b ldr r3, [r3, #112] ; 0x70
80037b2: 0d5b lsrs r3, r3, #21
80037b4: b2db uxtb r3, r3
80037b6: f003 0301 and.w r3, r3, #1
80037ba: b2da uxtb r2, r3
80037bc: 683b ldr r3, [r7, #0]
80037be: f883 2020 strb.w r2, [r3, #32]
pCSD->Reserved3 = 0;
80037c2: 683b ldr r3, [r7, #0]
80037c4: 2200 movs r2, #0
80037c6: f883 2021 strb.w r2, [r3, #33] ; 0x21
pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U);
80037ca: 687b ldr r3, [r7, #4]
80037cc: 6f1b ldr r3, [r3, #112] ; 0x70
80037ce: 0c1b lsrs r3, r3, #16
80037d0: b2db uxtb r3, r3
80037d2: f003 0301 and.w r3, r3, #1
80037d6: b2da uxtb r2, r3
80037d8: 683b ldr r3, [r7, #0]
80037da: f883 2022 strb.w r2, [r3, #34] ; 0x22
pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U);
80037de: 687b ldr r3, [r7, #4]
80037e0: 6f1b ldr r3, [r3, #112] ; 0x70
80037e2: 0bdb lsrs r3, r3, #15
80037e4: b2db uxtb r3, r3
80037e6: f003 0301 and.w r3, r3, #1
80037ea: b2da uxtb r2, r3
80037ec: 683b ldr r3, [r7, #0]
80037ee: f883 2023 strb.w r2, [r3, #35] ; 0x23
pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U);
80037f2: 687b ldr r3, [r7, #4]
80037f4: 6f1b ldr r3, [r3, #112] ; 0x70
80037f6: 0b9b lsrs r3, r3, #14
80037f8: b2db uxtb r3, r3
80037fa: f003 0301 and.w r3, r3, #1
80037fe: b2da uxtb r2, r3
8003800: 683b ldr r3, [r7, #0]
8003802: f883 2024 strb.w r2, [r3, #36] ; 0x24
pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U);
8003806: 687b ldr r3, [r7, #4]
8003808: 6f1b ldr r3, [r3, #112] ; 0x70
800380a: 0b5b lsrs r3, r3, #13
800380c: b2db uxtb r3, r3
800380e: f003 0301 and.w r3, r3, #1
8003812: b2da uxtb r2, r3
8003814: 683b ldr r3, [r7, #0]
8003816: f883 2025 strb.w r2, [r3, #37] ; 0x25
pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U);
800381a: 687b ldr r3, [r7, #4]
800381c: 6f1b ldr r3, [r3, #112] ; 0x70
800381e: 0b1b lsrs r3, r3, #12
8003820: b2db uxtb r3, r3
8003822: f003 0301 and.w r3, r3, #1
8003826: b2da uxtb r2, r3
8003828: 683b ldr r3, [r7, #0]
800382a: f883 2026 strb.w r2, [r3, #38] ; 0x26
pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U);
800382e: 687b ldr r3, [r7, #4]
8003830: 6f1b ldr r3, [r3, #112] ; 0x70
8003832: 0a9b lsrs r3, r3, #10
8003834: b2db uxtb r3, r3
8003836: f003 0303 and.w r3, r3, #3
800383a: b2da uxtb r2, r3
800383c: 683b ldr r3, [r7, #0]
800383e: f883 2027 strb.w r2, [r3, #39] ; 0x27
pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U);
8003842: 687b ldr r3, [r7, #4]
8003844: 6f1b ldr r3, [r3, #112] ; 0x70
8003846: 0a1b lsrs r3, r3, #8
8003848: b2db uxtb r3, r3
800384a: f003 0303 and.w r3, r3, #3
800384e: b2da uxtb r2, r3
8003850: 683b ldr r3, [r7, #0]
8003852: f883 2028 strb.w r2, [r3, #40] ; 0x28
pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U);
8003856: 687b ldr r3, [r7, #4]
8003858: 6f1b ldr r3, [r3, #112] ; 0x70
800385a: 085b lsrs r3, r3, #1
800385c: b2db uxtb r3, r3
800385e: f003 037f and.w r3, r3, #127 ; 0x7f
8003862: b2da uxtb r2, r3
8003864: 683b ldr r3, [r7, #0]
8003866: f883 2029 strb.w r2, [r3, #41] ; 0x29
pCSD->Reserved4 = 1;
800386a: 683b ldr r3, [r7, #0]
800386c: 2201 movs r2, #1
800386e: f883 202a strb.w r2, [r3, #42] ; 0x2a
return HAL_OK;
8003872: 2300 movs r3, #0
}
8003874: 4618 mov r0, r3
8003876: 370c adds r7, #12
8003878: 46bd mov sp, r7
800387a: f85d 7b04 ldr.w r7, [sp], #4
800387e: 4770 bx lr
8003880: 004005ff .word 0x004005ff
08003884 <HAL_SD_GetCardInfo>:
* @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
{
8003884: b480 push {r7}
8003886: b083 sub sp, #12
8003888: af00 add r7, sp, #0
800388a: 6078 str r0, [r7, #4]
800388c: 6039 str r1, [r7, #0]
pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType);
800388e: 687b ldr r3, [r7, #4]
8003890: 6c5a ldr r2, [r3, #68] ; 0x44
8003892: 683b ldr r3, [r7, #0]
8003894: 601a str r2, [r3, #0]
pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion);
8003896: 687b ldr r3, [r7, #4]
8003898: 6c9a ldr r2, [r3, #72] ; 0x48
800389a: 683b ldr r3, [r7, #0]
800389c: 605a str r2, [r3, #4]
pCardInfo->Class = (uint32_t)(hsd->SdCard.Class);
800389e: 687b ldr r3, [r7, #4]
80038a0: 6cda ldr r2, [r3, #76] ; 0x4c
80038a2: 683b ldr r3, [r7, #0]
80038a4: 609a str r2, [r3, #8]
pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd);
80038a6: 687b ldr r3, [r7, #4]
80038a8: 6d1a ldr r2, [r3, #80] ; 0x50
80038aa: 683b ldr r3, [r7, #0]
80038ac: 60da str r2, [r3, #12]
pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr);
80038ae: 687b ldr r3, [r7, #4]
80038b0: 6d5a ldr r2, [r3, #84] ; 0x54
80038b2: 683b ldr r3, [r7, #0]
80038b4: 611a str r2, [r3, #16]
pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
80038b6: 687b ldr r3, [r7, #4]
80038b8: 6d9a ldr r2, [r3, #88] ; 0x58
80038ba: 683b ldr r3, [r7, #0]
80038bc: 615a str r2, [r3, #20]
pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
80038be: 687b ldr r3, [r7, #4]
80038c0: 6dda ldr r2, [r3, #92] ; 0x5c
80038c2: 683b ldr r3, [r7, #0]
80038c4: 619a str r2, [r3, #24]
pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
80038c6: 687b ldr r3, [r7, #4]
80038c8: 6e1a ldr r2, [r3, #96] ; 0x60
80038ca: 683b ldr r3, [r7, #0]
80038cc: 61da str r2, [r3, #28]
return HAL_OK;
80038ce: 2300 movs r3, #0
}
80038d0: 4618 mov r0, r3
80038d2: 370c adds r7, #12
80038d4: 46bd mov sp, r7
80038d6: f85d 7b04 ldr.w r7, [sp], #4
80038da: 4770 bx lr
080038dc <HAL_SD_ConfigWideBusOperation>:
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
* @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
{
80038dc: b5b0 push {r4, r5, r7, lr}
80038de: b08e sub sp, #56 ; 0x38
80038e0: af04 add r7, sp, #16
80038e2: 6078 str r0, [r7, #4]
80038e4: 6039 str r1, [r7, #0]
SDIO_InitTypeDef Init;
uint32_t errorstate;
HAL_StatusTypeDef status = HAL_OK;
80038e6: 2300 movs r3, #0
80038e8: f887 3027 strb.w r3, [r7, #39] ; 0x27
/* Check the parameters */
assert_param(IS_SDIO_BUS_WIDE(WideMode));
/* Change State */
hsd->State = HAL_SD_STATE_BUSY;
80038ec: 687b ldr r3, [r7, #4]
80038ee: 2203 movs r2, #3
80038f0: f883 2034 strb.w r2, [r3, #52] ; 0x34
if(hsd->SdCard.CardType != CARD_SECURED)
80038f4: 687b ldr r3, [r7, #4]
80038f6: 6c5b ldr r3, [r3, #68] ; 0x44
80038f8: 2b03 cmp r3, #3
80038fa: d02e beq.n 800395a <HAL_SD_ConfigWideBusOperation+0x7e>
{
if(WideMode == SDIO_BUS_WIDE_8B)
80038fc: 683b ldr r3, [r7, #0]
80038fe: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003902: d106 bne.n 8003912 <HAL_SD_ConfigWideBusOperation+0x36>
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
8003904: 687b ldr r3, [r7, #4]
8003906: 6b9b ldr r3, [r3, #56] ; 0x38
8003908: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000
800390c: 687b ldr r3, [r7, #4]
800390e: 639a str r2, [r3, #56] ; 0x38
8003910: e029 b.n 8003966 <HAL_SD_ConfigWideBusOperation+0x8a>
}
else if(WideMode == SDIO_BUS_WIDE_4B)
8003912: 683b ldr r3, [r7, #0]
8003914: f5b3 6f00 cmp.w r3, #2048 ; 0x800
8003918: d10a bne.n 8003930 <HAL_SD_ConfigWideBusOperation+0x54>
{
errorstate = SD_WideBus_Enable(hsd);
800391a: 6878 ldr r0, [r7, #4]
800391c: f000 faba bl 8003e94 <SD_WideBus_Enable>
8003920: 6238 str r0, [r7, #32]
hsd->ErrorCode |= errorstate;
8003922: 687b ldr r3, [r7, #4]
8003924: 6b9a ldr r2, [r3, #56] ; 0x38
8003926: 6a3b ldr r3, [r7, #32]
8003928: 431a orrs r2, r3
800392a: 687b ldr r3, [r7, #4]
800392c: 639a str r2, [r3, #56] ; 0x38
800392e: e01a b.n 8003966 <HAL_SD_ConfigWideBusOperation+0x8a>
}
else if(WideMode == SDIO_BUS_WIDE_1B)
8003930: 683b ldr r3, [r7, #0]
8003932: 2b00 cmp r3, #0
8003934: d10a bne.n 800394c <HAL_SD_ConfigWideBusOperation+0x70>
{
errorstate = SD_WideBus_Disable(hsd);
8003936: 6878 ldr r0, [r7, #4]
8003938: f000 faf7 bl 8003f2a <SD_WideBus_Disable>
800393c: 6238 str r0, [r7, #32]
hsd->ErrorCode |= errorstate;
800393e: 687b ldr r3, [r7, #4]
8003940: 6b9a ldr r2, [r3, #56] ; 0x38
8003942: 6a3b ldr r3, [r7, #32]
8003944: 431a orrs r2, r3
8003946: 687b ldr r3, [r7, #4]
8003948: 639a str r2, [r3, #56] ; 0x38
800394a: e00c b.n 8003966 <HAL_SD_ConfigWideBusOperation+0x8a>
}
else
{
/* WideMode is not a valid argument*/
hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
800394c: 687b ldr r3, [r7, #4]
800394e: 6b9b ldr r3, [r3, #56] ; 0x38
8003950: f043 6200 orr.w r2, r3, #134217728 ; 0x8000000
8003954: 687b ldr r3, [r7, #4]
8003956: 639a str r2, [r3, #56] ; 0x38
8003958: e005 b.n 8003966 <HAL_SD_ConfigWideBusOperation+0x8a>
}
}
else
{
/* MMC Card does not support this feature */
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
800395a: 687b ldr r3, [r7, #4]
800395c: 6b9b ldr r3, [r3, #56] ; 0x38
800395e: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000
8003962: 687b ldr r3, [r7, #4]
8003964: 639a str r2, [r3, #56] ; 0x38
}
if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
8003966: 687b ldr r3, [r7, #4]
8003968: 6b9b ldr r3, [r3, #56] ; 0x38
800396a: 2b00 cmp r3, #0
800396c: d00b beq.n 8003986 <HAL_SD_ConfigWideBusOperation+0xaa>
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
800396e: 687b ldr r3, [r7, #4]
8003970: 681b ldr r3, [r3, #0]
8003972: 4a26 ldr r2, [pc, #152] ; (8003a0c <HAL_SD_ConfigWideBusOperation+0x130>)
8003974: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
8003976: 687b ldr r3, [r7, #4]
8003978: 2201 movs r2, #1
800397a: f883 2034 strb.w r2, [r3, #52] ; 0x34
status = HAL_ERROR;
800397e: 2301 movs r3, #1
8003980: f887 3027 strb.w r3, [r7, #39] ; 0x27
8003984: e01f b.n 80039c6 <HAL_SD_ConfigWideBusOperation+0xea>
}
else
{
/* Configure the SDIO peripheral */
Init.ClockEdge = hsd->Init.ClockEdge;
8003986: 687b ldr r3, [r7, #4]
8003988: 685b ldr r3, [r3, #4]
800398a: 60bb str r3, [r7, #8]
Init.ClockBypass = hsd->Init.ClockBypass;
800398c: 687b ldr r3, [r7, #4]
800398e: 689b ldr r3, [r3, #8]
8003990: 60fb str r3, [r7, #12]
Init.ClockPowerSave = hsd->Init.ClockPowerSave;
8003992: 687b ldr r3, [r7, #4]
8003994: 68db ldr r3, [r3, #12]
8003996: 613b str r3, [r7, #16]
Init.BusWide = WideMode;
8003998: 683b ldr r3, [r7, #0]
800399a: 617b str r3, [r7, #20]
Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
800399c: 687b ldr r3, [r7, #4]
800399e: 695b ldr r3, [r3, #20]
80039a0: 61bb str r3, [r7, #24]
Init.ClockDiv = hsd->Init.ClockDiv;
80039a2: 687b ldr r3, [r7, #4]
80039a4: 699b ldr r3, [r3, #24]
80039a6: 61fb str r3, [r7, #28]
(void)SDIO_Init(hsd->Instance, Init);
80039a8: 687b ldr r3, [r7, #4]
80039aa: 681d ldr r5, [r3, #0]
80039ac: 466c mov r4, sp
80039ae: f107 0314 add.w r3, r7, #20
80039b2: e893 0007 ldmia.w r3, {r0, r1, r2}
80039b6: e884 0007 stmia.w r4, {r0, r1, r2}
80039ba: f107 0308 add.w r3, r7, #8
80039be: cb0e ldmia r3, {r1, r2, r3}
80039c0: 4628 mov r0, r5
80039c2: f000 fe6f bl 80046a4 <SDIO_Init>
}
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
80039c6: 687b ldr r3, [r7, #4]
80039c8: 681b ldr r3, [r3, #0]
80039ca: f44f 7100 mov.w r1, #512 ; 0x200
80039ce: 4618 mov r0, r3
80039d0: f000 ff33 bl 800483a <SDMMC_CmdBlockLength>
80039d4: 6238 str r0, [r7, #32]
if(errorstate != HAL_SD_ERROR_NONE)
80039d6: 6a3b ldr r3, [r7, #32]
80039d8: 2b00 cmp r3, #0
80039da: d00c beq.n 80039f6 <HAL_SD_ConfigWideBusOperation+0x11a>
{
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
80039dc: 687b ldr r3, [r7, #4]
80039de: 681b ldr r3, [r3, #0]
80039e0: 4a0a ldr r2, [pc, #40] ; (8003a0c <HAL_SD_ConfigWideBusOperation+0x130>)
80039e2: 639a str r2, [r3, #56] ; 0x38
hsd->ErrorCode |= errorstate;
80039e4: 687b ldr r3, [r7, #4]
80039e6: 6b9a ldr r2, [r3, #56] ; 0x38
80039e8: 6a3b ldr r3, [r7, #32]
80039ea: 431a orrs r2, r3
80039ec: 687b ldr r3, [r7, #4]
80039ee: 639a str r2, [r3, #56] ; 0x38
status = HAL_ERROR;
80039f0: 2301 movs r3, #1
80039f2: f887 3027 strb.w r3, [r7, #39] ; 0x27
}
/* Change State */
hsd->State = HAL_SD_STATE_READY;
80039f6: 687b ldr r3, [r7, #4]
80039f8: 2201 movs r2, #1
80039fa: f883 2034 strb.w r2, [r3, #52] ; 0x34
return status;
80039fe: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
}
8003a02: 4618 mov r0, r3
8003a04: 3728 adds r7, #40 ; 0x28
8003a06: 46bd mov sp, r7
8003a08: bdb0 pop {r4, r5, r7, pc}
8003a0a: bf00 nop
8003a0c: 004005ff .word 0x004005ff
08003a10 <HAL_SD_GetCardState>:
* @brief Gets the current sd card data state.
* @param hsd: pointer to SD handle
* @retval Card state
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
{
8003a10: b580 push {r7, lr}
8003a12: b086 sub sp, #24
8003a14: af00 add r7, sp, #0
8003a16: 6078 str r0, [r7, #4]
uint32_t cardstate;
uint32_t errorstate;
uint32_t resp1 = 0;
8003a18: 2300 movs r3, #0
8003a1a: 60fb str r3, [r7, #12]
errorstate = SD_SendStatus(hsd, &resp1);
8003a1c: f107 030c add.w r3, r7, #12
8003a20: 4619 mov r1, r3
8003a22: 6878 ldr r0, [r7, #4]
8003a24: f000 fa0e bl 8003e44 <SD_SendStatus>
8003a28: 6178 str r0, [r7, #20]
if(errorstate != HAL_SD_ERROR_NONE)
8003a2a: 697b ldr r3, [r7, #20]
8003a2c: 2b00 cmp r3, #0
8003a2e: d005 beq.n 8003a3c <HAL_SD_GetCardState+0x2c>
{
hsd->ErrorCode |= errorstate;
8003a30: 687b ldr r3, [r7, #4]
8003a32: 6b9a ldr r2, [r3, #56] ; 0x38
8003a34: 697b ldr r3, [r7, #20]
8003a36: 431a orrs r2, r3
8003a38: 687b ldr r3, [r7, #4]
8003a3a: 639a str r2, [r3, #56] ; 0x38
}
cardstate = ((resp1 >> 9U) & 0x0FU);
8003a3c: 68fb ldr r3, [r7, #12]
8003a3e: 0a5b lsrs r3, r3, #9
8003a40: f003 030f and.w r3, r3, #15
8003a44: 613b str r3, [r7, #16]
return (HAL_SD_CardStateTypeDef)cardstate;
8003a46: 693b ldr r3, [r7, #16]
}
8003a48: 4618 mov r0, r3
8003a4a: 3718 adds r7, #24
8003a4c: 46bd mov sp, r7
8003a4e: bd80 pop {r7, pc}
08003a50 <SD_DMATransmitCplt>:
* @brief DMA SD transmit process complete callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
8003a50: b480 push {r7}
8003a52: b085 sub sp, #20
8003a54: af00 add r7, sp, #0
8003a56: 6078 str r0, [r7, #4]
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
8003a58: 687b ldr r3, [r7, #4]
8003a5a: 6b9b ldr r3, [r3, #56] ; 0x38
8003a5c: 60fb str r3, [r7, #12]
/* Enable DATAEND Interrupt */
__HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
8003a5e: 68fb ldr r3, [r7, #12]
8003a60: 681b ldr r3, [r3, #0]
8003a62: 6bda ldr r2, [r3, #60] ; 0x3c
8003a64: 68fb ldr r3, [r7, #12]
8003a66: 681b ldr r3, [r3, #0]
8003a68: f442 7280 orr.w r2, r2, #256 ; 0x100
8003a6c: 63da str r2, [r3, #60] ; 0x3c
}
8003a6e: bf00 nop
8003a70: 3714 adds r7, #20
8003a72: 46bd mov sp, r7
8003a74: f85d 7b04 ldr.w r7, [sp], #4
8003a78: 4770 bx lr
08003a7a <SD_DMAReceiveCplt>:
* @brief DMA SD receive process complete callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
8003a7a: b580 push {r7, lr}
8003a7c: b084 sub sp, #16
8003a7e: af00 add r7, sp, #0
8003a80: 6078 str r0, [r7, #4]
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
8003a82: 687b ldr r3, [r7, #4]
8003a84: 6b9b ldr r3, [r3, #56] ; 0x38
8003a86: 60fb str r3, [r7, #12]
uint32_t errorstate;
/* Send stop command in multiblock write */
if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
8003a88: 68fb ldr r3, [r7, #12]
8003a8a: 6b1b ldr r3, [r3, #48] ; 0x30
8003a8c: 2b82 cmp r3, #130 ; 0x82
8003a8e: d111 bne.n 8003ab4 <SD_DMAReceiveCplt+0x3a>
{
errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
8003a90: 68fb ldr r3, [r7, #12]
8003a92: 681b ldr r3, [r3, #0]
8003a94: 4618 mov r0, r3
8003a96: f000 ff7b bl 8004990 <SDMMC_CmdStopTransfer>
8003a9a: 60b8 str r0, [r7, #8]
if(errorstate != HAL_SD_ERROR_NONE)
8003a9c: 68bb ldr r3, [r7, #8]
8003a9e: 2b00 cmp r3, #0
8003aa0: d008 beq.n 8003ab4 <SD_DMAReceiveCplt+0x3a>
{
hsd->ErrorCode |= errorstate;
8003aa2: 68fb ldr r3, [r7, #12]
8003aa4: 6b9a ldr r2, [r3, #56] ; 0x38
8003aa6: 68bb ldr r3, [r7, #8]
8003aa8: 431a orrs r2, r3
8003aaa: 68fb ldr r3, [r7, #12]
8003aac: 639a str r2, [r3, #56] ; 0x38
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
8003aae: 68f8 ldr r0, [r7, #12]
8003ab0: f7ff fd3a bl 8003528 <HAL_SD_ErrorCallback>
}
}
/* Disable the DMA transfer for transmit request by setting the DMAEN bit
in the SD DCTRL register */
hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
8003ab4: 68fb ldr r3, [r7, #12]
8003ab6: 681b ldr r3, [r3, #0]
8003ab8: 6ada ldr r2, [r3, #44] ; 0x2c
8003aba: 68fb ldr r3, [r7, #12]
8003abc: 681b ldr r3, [r3, #0]
8003abe: f022 0208 bic.w r2, r2, #8
8003ac2: 62da str r2, [r3, #44] ; 0x2c
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
8003ac4: 68fb ldr r3, [r7, #12]
8003ac6: 681b ldr r3, [r3, #0]
8003ac8: f240 523a movw r2, #1338 ; 0x53a
8003acc: 639a str r2, [r3, #56] ; 0x38
hsd->State = HAL_SD_STATE_READY;
8003ace: 68fb ldr r3, [r7, #12]
8003ad0: 2201 movs r2, #1
8003ad2: f883 2034 strb.w r2, [r3, #52] ; 0x34
hsd->Context = SD_CONTEXT_NONE;
8003ad6: 68fb ldr r3, [r7, #12]
8003ad8: 2200 movs r2, #0
8003ada: 631a str r2, [r3, #48] ; 0x30
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->RxCpltCallback(hsd);
#else
HAL_SD_RxCpltCallback(hsd);
8003adc: 68f8 ldr r0, [r7, #12]
8003ade: f001 fddd bl 800569c <HAL_SD_RxCpltCallback>
#endif
}
8003ae2: bf00 nop
8003ae4: 3710 adds r7, #16
8003ae6: 46bd mov sp, r7
8003ae8: bd80 pop {r7, pc}
...
08003aec <SD_DMAError>:
* @brief DMA SD communication error callback
* @param hdma: DMA handle
* @retval None
*/
static void SD_DMAError(DMA_HandleTypeDef *hdma)
{
8003aec: b580 push {r7, lr}
8003aee: b086 sub sp, #24
8003af0: af00 add r7, sp, #0
8003af2: 6078 str r0, [r7, #4]
SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
8003af4: 687b ldr r3, [r7, #4]
8003af6: 6b9b ldr r3, [r3, #56] ; 0x38
8003af8: 617b str r3, [r7, #20]
HAL_SD_CardStateTypeDef CardState;
uint32_t RxErrorCode, TxErrorCode;
/* if DMA error is FIFO error ignore it */
if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
8003afa: 6878 ldr r0, [r7, #4]
8003afc: f7fd fe13 bl 8001726 <HAL_DMA_GetError>
8003b00: 4603 mov r3, r0
8003b02: 2b02 cmp r3, #2
8003b04: d03e beq.n 8003b84 <SD_DMAError+0x98>
{
RxErrorCode = hsd->hdmarx->ErrorCode;
8003b06: 697b ldr r3, [r7, #20]
8003b08: 6c1b ldr r3, [r3, #64] ; 0x40
8003b0a: 6d5b ldr r3, [r3, #84] ; 0x54
8003b0c: 613b str r3, [r7, #16]
TxErrorCode = hsd->hdmatx->ErrorCode;
8003b0e: 697b ldr r3, [r7, #20]
8003b10: 6bdb ldr r3, [r3, #60] ; 0x3c
8003b12: 6d5b ldr r3, [r3, #84] ; 0x54
8003b14: 60fb str r3, [r7, #12]
if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE))
8003b16: 693b ldr r3, [r7, #16]
8003b18: 2b01 cmp r3, #1
8003b1a: d002 beq.n 8003b22 <SD_DMAError+0x36>
8003b1c: 68fb ldr r3, [r7, #12]
8003b1e: 2b01 cmp r3, #1
8003b20: d12d bne.n 8003b7e <SD_DMAError+0x92>
{
/* Clear All flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
8003b22: 697b ldr r3, [r7, #20]
8003b24: 681b ldr r3, [r3, #0]
8003b26: 4a19 ldr r2, [pc, #100] ; (8003b8c <SD_DMAError+0xa0>)
8003b28: 639a str r2, [r3, #56] ; 0x38
/* Disable All interrupts */
__HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
8003b2a: 697b ldr r3, [r7, #20]
8003b2c: 681b ldr r3, [r3, #0]
8003b2e: 6bda ldr r2, [r3, #60] ; 0x3c
8003b30: 697b ldr r3, [r7, #20]
8003b32: 681b ldr r3, [r3, #0]
8003b34: f422 729d bic.w r2, r2, #314 ; 0x13a
8003b38: 63da str r2, [r3, #60] ; 0x3c
SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
hsd->ErrorCode |= HAL_SD_ERROR_DMA;
8003b3a: 697b ldr r3, [r7, #20]
8003b3c: 6b9b ldr r3, [r3, #56] ; 0x38
8003b3e: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000
8003b42: 697b ldr r3, [r7, #20]
8003b44: 639a str r2, [r3, #56] ; 0x38
CardState = HAL_SD_GetCardState(hsd);
8003b46: 6978 ldr r0, [r7, #20]
8003b48: f7ff ff62 bl 8003a10 <HAL_SD_GetCardState>
8003b4c: 60b8 str r0, [r7, #8]
if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
8003b4e: 68bb ldr r3, [r7, #8]
8003b50: 2b06 cmp r3, #6
8003b52: d002 beq.n 8003b5a <SD_DMAError+0x6e>
8003b54: 68bb ldr r3, [r7, #8]
8003b56: 2b05 cmp r3, #5
8003b58: d10a bne.n 8003b70 <SD_DMAError+0x84>
{
hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
8003b5a: 697b ldr r3, [r7, #20]
8003b5c: 681b ldr r3, [r3, #0]
8003b5e: 4618 mov r0, r3
8003b60: f000 ff16 bl 8004990 <SDMMC_CmdStopTransfer>
8003b64: 4602 mov r2, r0
8003b66: 697b ldr r3, [r7, #20]
8003b68: 6b9b ldr r3, [r3, #56] ; 0x38
8003b6a: 431a orrs r2, r3
8003b6c: 697b ldr r3, [r7, #20]
8003b6e: 639a str r2, [r3, #56] ; 0x38
}
hsd->State= HAL_SD_STATE_READY;
8003b70: 697b ldr r3, [r7, #20]
8003b72: 2201 movs r2, #1
8003b74: f883 2034 strb.w r2, [r3, #52] ; 0x34
hsd->Context = SD_CONTEXT_NONE;
8003b78: 697b ldr r3, [r7, #20]
8003b7a: 2200 movs r2, #0
8003b7c: 631a str r2, [r3, #48] ; 0x30
}
#if (USE_HAL_SD_REGISTER_CALLBACKS == 1)
hsd->ErrorCallback(hsd);
#else
HAL_SD_ErrorCallback(hsd);
8003b7e: 6978 ldr r0, [r7, #20]
8003b80: f7ff fcd2 bl 8003528 <HAL_SD_ErrorCallback>
#endif
}
}
8003b84: bf00 nop
8003b86: 3718 adds r7, #24
8003b88: 46bd mov sp, r7
8003b8a: bd80 pop {r7, pc}
8003b8c: 004005ff .word 0x004005ff
08003b90 <SD_InitCard>:
* @brief Initializes the sd card.
* @param hsd: Pointer to SD handle
* @retval SD Card error state
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
{
8003b90: b5b0 push {r4, r5, r7, lr}
8003b92: b094 sub sp, #80 ; 0x50
8003b94: af04 add r7, sp, #16
8003b96: 6078 str r0, [r7, #4]
HAL_SD_CardCSDTypeDef CSD;
uint32_t errorstate;
uint16_t sd_rca = 1U;
8003b98: 2301 movs r3, #1
8003b9a: 81fb strh r3, [r7, #14]
/* Check the power State */
if(SDIO_GetPowerState(hsd->Instance) == 0U)
8003b9c: 687b ldr r3, [r7, #4]
8003b9e: 681b ldr r3, [r3, #0]
8003ba0: 4618 mov r0, r3
8003ba2: f000 fdc6 bl 8004732 <SDIO_GetPowerState>
8003ba6: 4603 mov r3, r0
8003ba8: 2b00 cmp r3, #0
8003baa: d102 bne.n 8003bb2 <SD_InitCard+0x22>
{
/* Power off */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
8003bac: f04f 6380 mov.w r3, #67108864 ; 0x4000000
8003bb0: e0b6 b.n 8003d20 <SD_InitCard+0x190>
}
if(hsd->SdCard.CardType != CARD_SECURED)
8003bb2: 687b ldr r3, [r7, #4]
8003bb4: 6c5b ldr r3, [r3, #68] ; 0x44
8003bb6: 2b03 cmp r3, #3
8003bb8: d02f beq.n 8003c1a <SD_InitCard+0x8a>
{
/* Send CMD2 ALL_SEND_CID */
errorstate = SDMMC_CmdSendCID(hsd->Instance);
8003bba: 687b ldr r3, [r7, #4]
8003bbc: 681b ldr r3, [r3, #0]
8003bbe: 4618 mov r0, r3
8003bc0: f000 fff0 bl 8004ba4 <SDMMC_CmdSendCID>
8003bc4: 63f8 str r0, [r7, #60] ; 0x3c
if(errorstate != HAL_SD_ERROR_NONE)
8003bc6: 6bfb ldr r3, [r7, #60] ; 0x3c
8003bc8: 2b00 cmp r3, #0
8003bca: d001 beq.n 8003bd0 <SD_InitCard+0x40>
{
return errorstate;
8003bcc: 6bfb ldr r3, [r7, #60] ; 0x3c
8003bce: e0a7 b.n 8003d20 <SD_InitCard+0x190>
}
else
{
/* Get Card identification number data */
hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
8003bd0: 687b ldr r3, [r7, #4]
8003bd2: 681b ldr r3, [r3, #0]
8003bd4: 2100 movs r1, #0
8003bd6: 4618 mov r0, r3
8003bd8: f000 fdf0 bl 80047bc <SDIO_GetResponse>
8003bdc: 4602 mov r2, r0
8003bde: 687b ldr r3, [r7, #4]
8003be0: 675a str r2, [r3, #116] ; 0x74
hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
8003be2: 687b ldr r3, [r7, #4]
8003be4: 681b ldr r3, [r3, #0]
8003be6: 2104 movs r1, #4
8003be8: 4618 mov r0, r3
8003bea: f000 fde7 bl 80047bc <SDIO_GetResponse>
8003bee: 4602 mov r2, r0
8003bf0: 687b ldr r3, [r7, #4]
8003bf2: 679a str r2, [r3, #120] ; 0x78
hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
8003bf4: 687b ldr r3, [r7, #4]
8003bf6: 681b ldr r3, [r3, #0]
8003bf8: 2108 movs r1, #8
8003bfa: 4618 mov r0, r3
8003bfc: f000 fdde bl 80047bc <SDIO_GetResponse>
8003c00: 4602 mov r2, r0
8003c02: 687b ldr r3, [r7, #4]
8003c04: 67da str r2, [r3, #124] ; 0x7c
hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
8003c06: 687b ldr r3, [r7, #4]
8003c08: 681b ldr r3, [r3, #0]
8003c0a: 210c movs r1, #12
8003c0c: 4618 mov r0, r3
8003c0e: f000 fdd5 bl 80047bc <SDIO_GetResponse>
8003c12: 4602 mov r2, r0
8003c14: 687b ldr r3, [r7, #4]
8003c16: f8c3 2080 str.w r2, [r3, #128] ; 0x80
}
}
if(hsd->SdCard.CardType != CARD_SECURED)
8003c1a: 687b ldr r3, [r7, #4]
8003c1c: 6c5b ldr r3, [r3, #68] ; 0x44
8003c1e: 2b03 cmp r3, #3
8003c20: d00d beq.n 8003c3e <SD_InitCard+0xae>
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
8003c22: 687b ldr r3, [r7, #4]
8003c24: 681b ldr r3, [r3, #0]
8003c26: f107 020e add.w r2, r7, #14
8003c2a: 4611 mov r1, r2
8003c2c: 4618 mov r0, r3
8003c2e: f000 fff6 bl 8004c1e <SDMMC_CmdSetRelAdd>
8003c32: 63f8 str r0, [r7, #60] ; 0x3c
if(errorstate != HAL_SD_ERROR_NONE)
8003c34: 6bfb ldr r3, [r7, #60] ; 0x3c
8003c36: 2b00 cmp r3, #0
8003c38: d001 beq.n 8003c3e <SD_InitCard+0xae>
{
return errorstate;
8003c3a: 6bfb ldr r3, [r7, #60] ; 0x3c
8003c3c: e070 b.n 8003d20 <SD_InitCard+0x190>
}
}
if(hsd->SdCard.CardType != CARD_SECURED)
8003c3e: 687b ldr r3, [r7, #4]
8003c40: 6c5b ldr r3, [r3, #68] ; 0x44
8003c42: 2b03 cmp r3, #3
8003c44: d036 beq.n 8003cb4 <SD_InitCard+0x124>
{
/* Get the SD card RCA */
hsd->SdCard.RelCardAdd = sd_rca;
8003c46: 89fb ldrh r3, [r7, #14]
8003c48: 461a mov r2, r3
8003c4a: 687b ldr r3, [r7, #4]
8003c4c: 651a str r2, [r3, #80] ; 0x50
/* Send CMD9 SEND_CSD with argument as card's RCA */
errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
8003c4e: 687b ldr r3, [r7, #4]
8003c50: 681a ldr r2, [r3, #0]
8003c52: 687b ldr r3, [r7, #4]
8003c54: 6d1b ldr r3, [r3, #80] ; 0x50
8003c56: 041b lsls r3, r3, #16
8003c58: 4619 mov r1, r3
8003c5a: 4610 mov r0, r2
8003c5c: f000 ffc0 bl 8004be0 <SDMMC_CmdSendCSD>
8003c60: 63f8 str r0, [r7, #60] ; 0x3c
if(errorstate != HAL_SD_ERROR_NONE)
8003c62: 6bfb ldr r3, [r7, #60] ; 0x3c
8003c64: 2b00 cmp r3, #0
8003c66: d001 beq.n 8003c6c <SD_InitCard+0xdc>
{
return errorstate;
8003c68: 6bfb ldr r3, [r7, #60] ; 0x3c
8003c6a: e059 b.n 8003d20 <SD_InitCard+0x190>
}
else
{
/* Get Card Specific Data */
hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
8003c6c: 687b ldr r3, [r7, #4]
8003c6e: 681b ldr r3, [r3, #0]
8003c70: 2100 movs r1, #0
8003c72: 4618 mov r0, r3
8003c74: f000 fda2 bl 80047bc <SDIO_GetResponse>
8003c78: 4602 mov r2, r0
8003c7a: 687b ldr r3, [r7, #4]
8003c7c: 665a str r2, [r3, #100] ; 0x64
hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
8003c7e: 687b ldr r3, [r7, #4]
8003c80: 681b ldr r3, [r3, #0]
8003c82: 2104 movs r1, #4
8003c84: 4618 mov r0, r3
8003c86: f000 fd99 bl 80047bc <SDIO_GetResponse>
8003c8a: 4602 mov r2, r0
8003c8c: 687b ldr r3, [r7, #4]
8003c8e: 669a str r2, [r3, #104] ; 0x68
hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
8003c90: 687b ldr r3, [r7, #4]
8003c92: 681b ldr r3, [r3, #0]
8003c94: 2108 movs r1, #8
8003c96: 4618 mov r0, r3
8003c98: f000 fd90 bl 80047bc <SDIO_GetResponse>
8003c9c: 4602 mov r2, r0
8003c9e: 687b ldr r3, [r7, #4]
8003ca0: 66da str r2, [r3, #108] ; 0x6c
hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
8003ca2: 687b ldr r3, [r7, #4]
8003ca4: 681b ldr r3, [r3, #0]
8003ca6: 210c movs r1, #12
8003ca8: 4618 mov r0, r3
8003caa: f000 fd87 bl 80047bc <SDIO_GetResponse>
8003cae: 4602 mov r2, r0
8003cb0: 687b ldr r3, [r7, #4]
8003cb2: 671a str r2, [r3, #112] ; 0x70
}
}
/* Get the Card Class */
hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
8003cb4: 687b ldr r3, [r7, #4]
8003cb6: 681b ldr r3, [r3, #0]
8003cb8: 2104 movs r1, #4
8003cba: 4618 mov r0, r3
8003cbc: f000 fd7e bl 80047bc <SDIO_GetResponse>
8003cc0: 4603 mov r3, r0
8003cc2: 0d1a lsrs r2, r3, #20
8003cc4: 687b ldr r3, [r7, #4]
8003cc6: 64da str r2, [r3, #76] ; 0x4c
/* Get CSD parameters */
if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK)
8003cc8: f107 0310 add.w r3, r7, #16
8003ccc: 4619 mov r1, r3
8003cce: 6878 ldr r0, [r7, #4]
8003cd0: f7ff fc34 bl 800353c <HAL_SD_GetCardCSD>
8003cd4: 4603 mov r3, r0
8003cd6: 2b00 cmp r3, #0
8003cd8: d002 beq.n 8003ce0 <SD_InitCard+0x150>
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
8003cda: f04f 5380 mov.w r3, #268435456 ; 0x10000000
8003cde: e01f b.n 8003d20 <SD_InitCard+0x190>
}
/* Select the Card */
errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
8003ce0: 687b ldr r3, [r7, #4]
8003ce2: 6819 ldr r1, [r3, #0]
8003ce4: 687b ldr r3, [r7, #4]
8003ce6: 6d1b ldr r3, [r3, #80] ; 0x50
8003ce8: 041b lsls r3, r3, #16
8003cea: 461a mov r2, r3
8003cec: f04f 0300 mov.w r3, #0
8003cf0: 4608 mov r0, r1
8003cf2: f000 fe6f bl 80049d4 <SDMMC_CmdSelDesel>
8003cf6: 63f8 str r0, [r7, #60] ; 0x3c
if(errorstate != HAL_SD_ERROR_NONE)
8003cf8: 6bfb ldr r3, [r7, #60] ; 0x3c
8003cfa: 2b00 cmp r3, #0
8003cfc: d001 beq.n 8003d02 <SD_InitCard+0x172>
{
return errorstate;
8003cfe: 6bfb ldr r3, [r7, #60] ; 0x3c
8003d00: e00e b.n 8003d20 <SD_InitCard+0x190>
}
/* Configure SDIO peripheral interface */
(void)SDIO_Init(hsd->Instance, hsd->Init);
8003d02: 687b ldr r3, [r7, #4]
8003d04: 681d ldr r5, [r3, #0]
8003d06: 687b ldr r3, [r7, #4]
8003d08: 466c mov r4, sp
8003d0a: f103 0210 add.w r2, r3, #16
8003d0e: ca07 ldmia r2, {r0, r1, r2}
8003d10: e884 0007 stmia.w r4, {r0, r1, r2}
8003d14: 3304 adds r3, #4
8003d16: cb0e ldmia r3, {r1, r2, r3}
8003d18: 4628 mov r0, r5
8003d1a: f000 fcc3 bl 80046a4 <SDIO_Init>
/* All cards are initialized */
return HAL_SD_ERROR_NONE;
8003d1e: 2300 movs r3, #0
}
8003d20: 4618 mov r0, r3
8003d22: 3740 adds r7, #64 ; 0x40
8003d24: 46bd mov sp, r7
8003d26: bdb0 pop {r4, r5, r7, pc}
08003d28 <SD_PowerON>:
* in the SD handle.
* @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
8003d28: b580 push {r7, lr}
8003d2a: b086 sub sp, #24
8003d2c: af00 add r7, sp, #0
8003d2e: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8003d30: 2300 movs r3, #0
8003d32: 60bb str r3, [r7, #8]
uint32_t response = 0U, validvoltage = 0U;
8003d34: 2300 movs r3, #0
8003d36: 617b str r3, [r7, #20]
8003d38: 2300 movs r3, #0
8003d3a: 613b str r3, [r7, #16]
uint32_t errorstate;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
8003d3c: 687b ldr r3, [r7, #4]
8003d3e: 681b ldr r3, [r3, #0]
8003d40: 4618 mov r0, r3
8003d42: f000 fe6a bl 8004a1a <SDMMC_CmdGoIdleState>
8003d46: 60f8 str r0, [r7, #12]
if(errorstate != HAL_SD_ERROR_NONE)
8003d48: 68fb ldr r3, [r7, #12]
8003d4a: 2b00 cmp r3, #0
8003d4c: d001 beq.n 8003d52 <SD_PowerON+0x2a>
{
return errorstate;
8003d4e: 68fb ldr r3, [r7, #12]
8003d50: e072 b.n 8003e38 <SD_PowerON+0x110>
}
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
errorstate = SDMMC_CmdOperCond(hsd->Instance);
8003d52: 687b ldr r3, [r7, #4]
8003d54: 681b ldr r3, [r3, #0]
8003d56: 4618 mov r0, r3
8003d58: f000 fe7d bl 8004a56 <SDMMC_CmdOperCond>
8003d5c: 60f8 str r0, [r7, #12]
if(errorstate != HAL_SD_ERROR_NONE)
8003d5e: 68fb ldr r3, [r7, #12]
8003d60: 2b00 cmp r3, #0
8003d62: d00d beq.n 8003d80 <SD_PowerON+0x58>
{
hsd->SdCard.CardVersion = CARD_V1_X;
8003d64: 687b ldr r3, [r7, #4]
8003d66: 2200 movs r2, #0
8003d68: 649a str r2, [r3, #72] ; 0x48
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
8003d6a: 687b ldr r3, [r7, #4]
8003d6c: 681b ldr r3, [r3, #0]
8003d6e: 4618 mov r0, r3
8003d70: f000 fe53 bl 8004a1a <SDMMC_CmdGoIdleState>
8003d74: 60f8 str r0, [r7, #12]
if(errorstate != HAL_SD_ERROR_NONE)
8003d76: 68fb ldr r3, [r7, #12]
8003d78: 2b00 cmp r3, #0
8003d7a: d004 beq.n 8003d86 <SD_PowerON+0x5e>
{
return errorstate;
8003d7c: 68fb ldr r3, [r7, #12]
8003d7e: e05b b.n 8003e38 <SD_PowerON+0x110>
}
}
else
{
hsd->SdCard.CardVersion = CARD_V2_X;
8003d80: 687b ldr r3, [r7, #4]
8003d82: 2201 movs r2, #1
8003d84: 649a str r2, [r3, #72] ; 0x48
}
if( hsd->SdCard.CardVersion == CARD_V2_X)
8003d86: 687b ldr r3, [r7, #4]
8003d88: 6c9b ldr r3, [r3, #72] ; 0x48
8003d8a: 2b01 cmp r3, #1
8003d8c: d137 bne.n 8003dfe <SD_PowerON+0xd6>
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
8003d8e: 687b ldr r3, [r7, #4]
8003d90: 681b ldr r3, [r3, #0]
8003d92: 2100 movs r1, #0
8003d94: 4618 mov r0, r3
8003d96: f000 fe7d bl 8004a94 <SDMMC_CmdAppCommand>
8003d9a: 60f8 str r0, [r7, #12]
if(errorstate != HAL_SD_ERROR_NONE)
8003d9c: 68fb ldr r3, [r7, #12]
8003d9e: 2b00 cmp r3, #0
8003da0: d02d beq.n 8003dfe <SD_PowerON+0xd6>
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
8003da2: f04f 5380 mov.w r3, #268435456 ; 0x10000000
8003da6: e047 b.n 8003e38 <SD_PowerON+0x110>
/* SD CARD */
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
8003da8: 687b ldr r3, [r7, #4]
8003daa: 681b ldr r3, [r3, #0]
8003dac: 2100 movs r1, #0
8003dae: 4618 mov r0, r3
8003db0: f000 fe70 bl 8004a94 <SDMMC_CmdAppCommand>
8003db4: 60f8 str r0, [r7, #12]
if(errorstate != HAL_SD_ERROR_NONE)
8003db6: 68fb ldr r3, [r7, #12]
8003db8: 2b00 cmp r3, #0
8003dba: d001 beq.n 8003dc0 <SD_PowerON+0x98>
{
return errorstate;
8003dbc: 68fb ldr r3, [r7, #12]
8003dbe: e03b b.n 8003e38 <SD_PowerON+0x110>
}
/* Send CMD41 */
errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
8003dc0: 687b ldr r3, [r7, #4]
8003dc2: 681b ldr r3, [r3, #0]
8003dc4: 491e ldr r1, [pc, #120] ; (8003e40 <SD_PowerON+0x118>)
8003dc6: 4618 mov r0, r3
8003dc8: f000 fe86 bl 8004ad8 <SDMMC_CmdAppOperCommand>
8003dcc: 60f8 str r0, [r7, #12]
if(errorstate != HAL_SD_ERROR_NONE)
8003dce: 68fb ldr r3, [r7, #12]
8003dd0: 2b00 cmp r3, #0
8003dd2: d002 beq.n 8003dda <SD_PowerON+0xb2>
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
8003dd4: f04f 5380 mov.w r3, #268435456 ; 0x10000000
8003dd8: e02e b.n 8003e38 <SD_PowerON+0x110>
}
/* Get command response */
response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
8003dda: 687b ldr r3, [r7, #4]
8003ddc: 681b ldr r3, [r3, #0]
8003dde: 2100 movs r1, #0
8003de0: 4618 mov r0, r3
8003de2: f000 fceb bl 80047bc <SDIO_GetResponse>
8003de6: 6178 str r0, [r7, #20]
/* Get operating voltage*/
validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
8003de8: 697b ldr r3, [r7, #20]
8003dea: 0fdb lsrs r3, r3, #31
8003dec: 2b01 cmp r3, #1
8003dee: d101 bne.n 8003df4 <SD_PowerON+0xcc>
8003df0: 2301 movs r3, #1
8003df2: e000 b.n 8003df6 <SD_PowerON+0xce>
8003df4: 2300 movs r3, #0
8003df6: 613b str r3, [r7, #16]
count++;
8003df8: 68bb ldr r3, [r7, #8]
8003dfa: 3301 adds r3, #1
8003dfc: 60bb str r3, [r7, #8]
while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
8003dfe: 68bb ldr r3, [r7, #8]
8003e00: f64f 72fe movw r2, #65534 ; 0xfffe
8003e04: 4293 cmp r3, r2
8003e06: d802 bhi.n 8003e0e <SD_PowerON+0xe6>
8003e08: 693b ldr r3, [r7, #16]
8003e0a: 2b00 cmp r3, #0
8003e0c: d0cc beq.n 8003da8 <SD_PowerON+0x80>
}
if(count >= SDMMC_MAX_VOLT_TRIAL)
8003e0e: 68bb ldr r3, [r7, #8]
8003e10: f64f 72fe movw r2, #65534 ; 0xfffe
8003e14: 4293 cmp r3, r2
8003e16: d902 bls.n 8003e1e <SD_PowerON+0xf6>
{
return HAL_SD_ERROR_INVALID_VOLTRANGE;
8003e18: f04f 7380 mov.w r3, #16777216 ; 0x1000000
8003e1c: e00c b.n 8003e38 <SD_PowerON+0x110>
}
if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
8003e1e: 697b ldr r3, [r7, #20]
8003e20: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000
8003e24: 2b00 cmp r3, #0
8003e26: d003 beq.n 8003e30 <SD_PowerON+0x108>
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
8003e28: 687b ldr r3, [r7, #4]
8003e2a: 2201 movs r2, #1
8003e2c: 645a str r2, [r3, #68] ; 0x44
8003e2e: e002 b.n 8003e36 <SD_PowerON+0x10e>
}
else
{
hsd->SdCard.CardType = CARD_SDSC;
8003e30: 687b ldr r3, [r7, #4]
8003e32: 2200 movs r2, #0
8003e34: 645a str r2, [r3, #68] ; 0x44
}
return HAL_SD_ERROR_NONE;
8003e36: 2300 movs r3, #0
}
8003e38: 4618 mov r0, r3
8003e3a: 3718 adds r7, #24
8003e3c: 46bd mov sp, r7
8003e3e: bd80 pop {r7, pc}
8003e40: c1100000 .word 0xc1100000
08003e44 <SD_SendStatus>:
* @param pCardStatus: pointer to the buffer that will contain the SD card
* status (Card Status register)
* @retval error state
*/
static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
{
8003e44: b580 push {r7, lr}
8003e46: b084 sub sp, #16
8003e48: af00 add r7, sp, #0
8003e4a: 6078 str r0, [r7, #4]
8003e4c: 6039 str r1, [r7, #0]
uint32_t errorstate;
if(pCardStatus == NULL)
8003e4e: 683b ldr r3, [r7, #0]
8003e50: 2b00 cmp r3, #0
8003e52: d102 bne.n 8003e5a <SD_SendStatus+0x16>
{
return HAL_SD_ERROR_PARAM;
8003e54: f04f 6300 mov.w r3, #134217728 ; 0x8000000
8003e58: e018 b.n 8003e8c <SD_SendStatus+0x48>
}
/* Send Status command */
errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
8003e5a: 687b ldr r3, [r7, #4]
8003e5c: 681a ldr r2, [r3, #0]
8003e5e: 687b ldr r3, [r7, #4]
8003e60: 6d1b ldr r3, [r3, #80] ; 0x50
8003e62: 041b lsls r3, r3, #16
8003e64: 4619 mov r1, r3
8003e66: 4610 mov r0, r2
8003e68: f000 fefa bl 8004c60 <SDMMC_CmdSendStatus>
8003e6c: 60f8 str r0, [r7, #12]
if(errorstate != HAL_SD_ERROR_NONE)
8003e6e: 68fb ldr r3, [r7, #12]
8003e70: 2b00 cmp r3, #0
8003e72: d001 beq.n 8003e78 <SD_SendStatus+0x34>
{
return errorstate;
8003e74: 68fb ldr r3, [r7, #12]
8003e76: e009 b.n 8003e8c <SD_SendStatus+0x48>
}
/* Get SD card status */
*pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
8003e78: 687b ldr r3, [r7, #4]
8003e7a: 681b ldr r3, [r3, #0]
8003e7c: 2100 movs r1, #0
8003e7e: 4618 mov r0, r3
8003e80: f000 fc9c bl 80047bc <SDIO_GetResponse>
8003e84: 4602 mov r2, r0
8003e86: 683b ldr r3, [r7, #0]
8003e88: 601a str r2, [r3, #0]
return HAL_SD_ERROR_NONE;
8003e8a: 2300 movs r3, #0
}
8003e8c: 4618 mov r0, r3
8003e8e: 3710 adds r7, #16
8003e90: 46bd mov sp, r7
8003e92: bd80 pop {r7, pc}
08003e94 <SD_WideBus_Enable>:
* @brief Enables the SDIO wide bus mode.
* @param hsd: pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
8003e94: b580 push {r7, lr}
8003e96: b086 sub sp, #24
8003e98: af00 add r7, sp, #0
8003e9a: 6078 str r0, [r7, #4]
uint32_t scr[2U] = {0U, 0U};
8003e9c: 2300 movs r3, #0
8003e9e: 60fb str r3, [r7, #12]
8003ea0: 2300 movs r3, #0
8003ea2: 613b str r3, [r7, #16]
uint32_t errorstate;
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
8003ea4: 687b ldr r3, [r7, #4]
8003ea6: 681b ldr r3, [r3, #0]
8003ea8: 2100 movs r1, #0
8003eaa: 4618 mov r0, r3
8003eac: f000 fc86 bl 80047bc <SDIO_GetResponse>
8003eb0: 4603 mov r3, r0
8003eb2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8003eb6: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
8003eba: d102 bne.n 8003ec2 <SD_WideBus_Enable+0x2e>
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
8003ebc: f44f 6300 mov.w r3, #2048 ; 0x800
8003ec0: e02f b.n 8003f22 <SD_WideBus_Enable+0x8e>
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
8003ec2: f107 030c add.w r3, r7, #12
8003ec6: 4619 mov r1, r3
8003ec8: 6878 ldr r0, [r7, #4]
8003eca: f000 f879 bl 8003fc0 <SD_FindSCR>
8003ece: 6178 str r0, [r7, #20]
if(errorstate != HAL_SD_ERROR_NONE)
8003ed0: 697b ldr r3, [r7, #20]
8003ed2: 2b00 cmp r3, #0
8003ed4: d001 beq.n 8003eda <SD_WideBus_Enable+0x46>
{
return errorstate;
8003ed6: 697b ldr r3, [r7, #20]
8003ed8: e023 b.n 8003f22 <SD_WideBus_Enable+0x8e>
}
/* If requested card supports wide bus operation */
if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
8003eda: 693b ldr r3, [r7, #16]
8003edc: f403 2380 and.w r3, r3, #262144 ; 0x40000
8003ee0: 2b00 cmp r3, #0
8003ee2: d01c beq.n 8003f1e <SD_WideBus_Enable+0x8a>
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
8003ee4: 687b ldr r3, [r7, #4]
8003ee6: 681a ldr r2, [r3, #0]
8003ee8: 687b ldr r3, [r7, #4]
8003eea: 6d1b ldr r3, [r3, #80] ; 0x50
8003eec: 041b lsls r3, r3, #16
8003eee: 4619 mov r1, r3
8003ef0: 4610 mov r0, r2
8003ef2: f000 fdcf bl 8004a94 <SDMMC_CmdAppCommand>
8003ef6: 6178 str r0, [r7, #20]
if(errorstate != HAL_SD_ERROR_NONE)
8003ef8: 697b ldr r3, [r7, #20]
8003efa: 2b00 cmp r3, #0
8003efc: d001 beq.n 8003f02 <SD_WideBus_Enable+0x6e>
{
return errorstate;
8003efe: 697b ldr r3, [r7, #20]
8003f00: e00f b.n 8003f22 <SD_WideBus_Enable+0x8e>
}
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
8003f02: 687b ldr r3, [r7, #4]
8003f04: 681b ldr r3, [r3, #0]
8003f06: 2102 movs r1, #2
8003f08: 4618 mov r0, r3
8003f0a: f000 fe08 bl 8004b1e <SDMMC_CmdBusWidth>
8003f0e: 6178 str r0, [r7, #20]
if(errorstate != HAL_SD_ERROR_NONE)
8003f10: 697b ldr r3, [r7, #20]
8003f12: 2b00 cmp r3, #0
8003f14: d001 beq.n 8003f1a <SD_WideBus_Enable+0x86>
{
return errorstate;
8003f16: 697b ldr r3, [r7, #20]
8003f18: e003 b.n 8003f22 <SD_WideBus_Enable+0x8e>
}
return HAL_SD_ERROR_NONE;
8003f1a: 2300 movs r3, #0
8003f1c: e001 b.n 8003f22 <SD_WideBus_Enable+0x8e>
}
else
{
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
8003f1e: f04f 6380 mov.w r3, #67108864 ; 0x4000000
}
}
8003f22: 4618 mov r0, r3
8003f24: 3718 adds r7, #24
8003f26: 46bd mov sp, r7
8003f28: bd80 pop {r7, pc}
08003f2a <SD_WideBus_Disable>:
* @brief Disables the SDIO wide bus mode.
* @param hsd: Pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
8003f2a: b580 push {r7, lr}
8003f2c: b086 sub sp, #24
8003f2e: af00 add r7, sp, #0
8003f30: 6078 str r0, [r7, #4]
uint32_t scr[2U] = {0U, 0U};
8003f32: 2300 movs r3, #0
8003f34: 60fb str r3, [r7, #12]
8003f36: 2300 movs r3, #0
8003f38: 613b str r3, [r7, #16]
uint32_t errorstate;
if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
8003f3a: 687b ldr r3, [r7, #4]
8003f3c: 681b ldr r3, [r3, #0]
8003f3e: 2100 movs r1, #0
8003f40: 4618 mov r0, r3
8003f42: f000 fc3b bl 80047bc <SDIO_GetResponse>
8003f46: 4603 mov r3, r0
8003f48: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8003f4c: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000
8003f50: d102 bne.n 8003f58 <SD_WideBus_Disable+0x2e>
{
return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
8003f52: f44f 6300 mov.w r3, #2048 ; 0x800
8003f56: e02f b.n 8003fb8 <SD_WideBus_Disable+0x8e>
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
8003f58: f107 030c add.w r3, r7, #12
8003f5c: 4619 mov r1, r3
8003f5e: 6878 ldr r0, [r7, #4]
8003f60: f000 f82e bl 8003fc0 <SD_FindSCR>
8003f64: 6178 str r0, [r7, #20]
if(errorstate != HAL_SD_ERROR_NONE)
8003f66: 697b ldr r3, [r7, #20]
8003f68: 2b00 cmp r3, #0
8003f6a: d001 beq.n 8003f70 <SD_WideBus_Disable+0x46>
{
return errorstate;
8003f6c: 697b ldr r3, [r7, #20]
8003f6e: e023 b.n 8003fb8 <SD_WideBus_Disable+0x8e>
}
/* If requested card supports 1 bit mode operation */
if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
8003f70: 693b ldr r3, [r7, #16]
8003f72: f403 3380 and.w r3, r3, #65536 ; 0x10000
8003f76: 2b00 cmp r3, #0
8003f78: d01c beq.n 8003fb4 <SD_WideBus_Disable+0x8a>
{
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
8003f7a: 687b ldr r3, [r7, #4]
8003f7c: 681a ldr r2, [r3, #0]
8003f7e: 687b ldr r3, [r7, #4]
8003f80: 6d1b ldr r3, [r3, #80] ; 0x50
8003f82: 041b lsls r3, r3, #16
8003f84: 4619 mov r1, r3
8003f86: 4610 mov r0, r2
8003f88: f000 fd84 bl 8004a94 <SDMMC_CmdAppCommand>
8003f8c: 6178 str r0, [r7, #20]
if(errorstate != HAL_SD_ERROR_NONE)
8003f8e: 697b ldr r3, [r7, #20]
8003f90: 2b00 cmp r3, #0
8003f92: d001 beq.n 8003f98 <SD_WideBus_Disable+0x6e>
{
return errorstate;
8003f94: 697b ldr r3, [r7, #20]
8003f96: e00f b.n 8003fb8 <SD_WideBus_Disable+0x8e>
}
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
8003f98: 687b ldr r3, [r7, #4]
8003f9a: 681b ldr r3, [r3, #0]
8003f9c: 2100 movs r1, #0
8003f9e: 4618 mov r0, r3
8003fa0: f000 fdbd bl 8004b1e <SDMMC_CmdBusWidth>
8003fa4: 6178 str r0, [r7, #20]
if(errorstate != HAL_SD_ERROR_NONE)
8003fa6: 697b ldr r3, [r7, #20]
8003fa8: 2b00 cmp r3, #0
8003faa: d001 beq.n 8003fb0 <SD_WideBus_Disable+0x86>
{
return errorstate;
8003fac: 697b ldr r3, [r7, #20]
8003fae: e003 b.n 8003fb8 <SD_WideBus_Disable+0x8e>
}
return HAL_SD_ERROR_NONE;
8003fb0: 2300 movs r3, #0
8003fb2: e001 b.n 8003fb8 <SD_WideBus_Disable+0x8e>
}
else
{
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
8003fb4: f04f 6380 mov.w r3, #67108864 ; 0x4000000
}
}
8003fb8: 4618 mov r0, r3
8003fba: 3718 adds r7, #24
8003fbc: 46bd mov sp, r7
8003fbe: bd80 pop {r7, pc}
08003fc0 <SD_FindSCR>:
* @param hsd: Pointer to SD handle
* @param pSCR: pointer to the buffer that will contain the SCR value
* @retval error state
*/
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
8003fc0: b590 push {r4, r7, lr}
8003fc2: b08f sub sp, #60 ; 0x3c
8003fc4: af00 add r7, sp, #0
8003fc6: 6078 str r0, [r7, #4]
8003fc8: 6039 str r1, [r7, #0]
SDIO_DataInitTypeDef config;
uint32_t errorstate;
uint32_t tickstart = HAL_GetTick();
8003fca: f7fc ffcd bl 8000f68 <HAL_GetTick>
8003fce: 6338 str r0, [r7, #48] ; 0x30
uint32_t index = 0U;
8003fd0: 2300 movs r3, #0
8003fd2: 637b str r3, [r7, #52] ; 0x34
uint32_t tempscr[2U] = {0U, 0U};
8003fd4: 2300 movs r3, #0
8003fd6: 60bb str r3, [r7, #8]
8003fd8: 2300 movs r3, #0
8003fda: 60fb str r3, [r7, #12]
uint32_t *scr = pSCR;
8003fdc: 683b ldr r3, [r7, #0]
8003fde: 62fb str r3, [r7, #44] ; 0x2c
/* Set Block Size To 8 Bytes */
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
8003fe0: 687b ldr r3, [r7, #4]
8003fe2: 681b ldr r3, [r3, #0]
8003fe4: 2108 movs r1, #8
8003fe6: 4618 mov r0, r3
8003fe8: f000 fc27 bl 800483a <SDMMC_CmdBlockLength>
8003fec: 62b8 str r0, [r7, #40] ; 0x28
if(errorstate != HAL_SD_ERROR_NONE)
8003fee: 6abb ldr r3, [r7, #40] ; 0x28
8003ff0: 2b00 cmp r3, #0
8003ff2: d001 beq.n 8003ff8 <SD_FindSCR+0x38>
{
return errorstate;
8003ff4: 6abb ldr r3, [r7, #40] ; 0x28
8003ff6: e0b2 b.n 800415e <SD_FindSCR+0x19e>
}
/* Send CMD55 APP_CMD with argument as card's RCA */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
8003ff8: 687b ldr r3, [r7, #4]
8003ffa: 681a ldr r2, [r3, #0]
8003ffc: 687b ldr r3, [r7, #4]
8003ffe: 6d1b ldr r3, [r3, #80] ; 0x50
8004000: 041b lsls r3, r3, #16
8004002: 4619 mov r1, r3
8004004: 4610 mov r0, r2
8004006: f000 fd45 bl 8004a94 <SDMMC_CmdAppCommand>
800400a: 62b8 str r0, [r7, #40] ; 0x28
if(errorstate != HAL_SD_ERROR_NONE)
800400c: 6abb ldr r3, [r7, #40] ; 0x28
800400e: 2b00 cmp r3, #0
8004010: d001 beq.n 8004016 <SD_FindSCR+0x56>
{
return errorstate;
8004012: 6abb ldr r3, [r7, #40] ; 0x28
8004014: e0a3 b.n 800415e <SD_FindSCR+0x19e>
}
config.DataTimeOut = SDMMC_DATATIMEOUT;
8004016: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800401a: 613b str r3, [r7, #16]
config.DataLength = 8U;
800401c: 2308 movs r3, #8
800401e: 617b str r3, [r7, #20]
config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
8004020: 2330 movs r3, #48 ; 0x30
8004022: 61bb str r3, [r7, #24]
config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
8004024: 2302 movs r3, #2
8004026: 61fb str r3, [r7, #28]
config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
8004028: 2300 movs r3, #0
800402a: 623b str r3, [r7, #32]
config.DPSM = SDIO_DPSM_ENABLE;
800402c: 2301 movs r3, #1
800402e: 627b str r3, [r7, #36] ; 0x24
(void)SDIO_ConfigData(hsd->Instance, &config);
8004030: 687b ldr r3, [r7, #4]
8004032: 681b ldr r3, [r3, #0]
8004034: f107 0210 add.w r2, r7, #16
8004038: 4611 mov r1, r2
800403a: 4618 mov r0, r3
800403c: f000 fbd1 bl 80047e2 <SDIO_ConfigData>
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
errorstate = SDMMC_CmdSendSCR(hsd->Instance);
8004040: 687b ldr r3, [r7, #4]
8004042: 681b ldr r3, [r3, #0]
8004044: 4618 mov r0, r3
8004046: f000 fd8c bl 8004b62 <SDMMC_CmdSendSCR>
800404a: 62b8 str r0, [r7, #40] ; 0x28
if(errorstate != HAL_SD_ERROR_NONE)
800404c: 6abb ldr r3, [r7, #40] ; 0x28
800404e: 2b00 cmp r3, #0
8004050: d02a beq.n 80040a8 <SD_FindSCR+0xe8>
{
return errorstate;
8004052: 6abb ldr r3, [r7, #40] ; 0x28
8004054: e083 b.n 800415e <SD_FindSCR+0x19e>
}
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT))
{
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
8004056: 687b ldr r3, [r7, #4]
8004058: 681b ldr r3, [r3, #0]
800405a: 6b5b ldr r3, [r3, #52] ; 0x34
800405c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8004060: 2b00 cmp r3, #0
8004062: d00f beq.n 8004084 <SD_FindSCR+0xc4>
{
*(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
8004064: 687b ldr r3, [r7, #4]
8004066: 6819 ldr r1, [r3, #0]
8004068: 6b7b ldr r3, [r7, #52] ; 0x34
800406a: 009b lsls r3, r3, #2
800406c: f107 0208 add.w r2, r7, #8
8004070: 18d4 adds r4, r2, r3
8004072: 4608 mov r0, r1
8004074: f000 fb41 bl 80046fa <SDIO_ReadFIFO>
8004078: 4603 mov r3, r0
800407a: 6023 str r3, [r4, #0]
index++;
800407c: 6b7b ldr r3, [r7, #52] ; 0x34
800407e: 3301 adds r3, #1
8004080: 637b str r3, [r7, #52] ; 0x34
8004082: e006 b.n 8004092 <SD_FindSCR+0xd2>
}
else if(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXACT))
8004084: 687b ldr r3, [r7, #4]
8004086: 681b ldr r3, [r3, #0]
8004088: 6b5b ldr r3, [r3, #52] ; 0x34
800408a: f403 5300 and.w r3, r3, #8192 ; 0x2000
800408e: 2b00 cmp r3, #0
8004090: d012 beq.n 80040b8 <SD_FindSCR+0xf8>
{
break;
}
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
8004092: f7fc ff69 bl 8000f68 <HAL_GetTick>
8004096: 4602 mov r2, r0
8004098: 6b3b ldr r3, [r7, #48] ; 0x30
800409a: 1ad3 subs r3, r2, r3
800409c: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
80040a0: d102 bne.n 80040a8 <SD_FindSCR+0xe8>
{
return HAL_SD_ERROR_TIMEOUT;
80040a2: f04f 4300 mov.w r3, #2147483648 ; 0x80000000
80040a6: e05a b.n 800415e <SD_FindSCR+0x19e>
while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT))
80040a8: 687b ldr r3, [r7, #4]
80040aa: 681b ldr r3, [r3, #0]
80040ac: 6b5b ldr r3, [r3, #52] ; 0x34
80040ae: f003 032a and.w r3, r3, #42 ; 0x2a
80040b2: 2b00 cmp r3, #0
80040b4: d0cf beq.n 8004056 <SD_FindSCR+0x96>
80040b6: e000 b.n 80040ba <SD_FindSCR+0xfa>
break;
80040b8: bf00 nop
}
}
if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
80040ba: 687b ldr r3, [r7, #4]
80040bc: 681b ldr r3, [r3, #0]
80040be: 6b5b ldr r3, [r3, #52] ; 0x34
80040c0: f003 0308 and.w r3, r3, #8
80040c4: 2b00 cmp r3, #0
80040c6: d005 beq.n 80040d4 <SD_FindSCR+0x114>
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
80040c8: 687b ldr r3, [r7, #4]
80040ca: 681b ldr r3, [r3, #0]
80040cc: 2208 movs r2, #8
80040ce: 639a str r2, [r3, #56] ; 0x38
return HAL_SD_ERROR_DATA_TIMEOUT;
80040d0: 2308 movs r3, #8
80040d2: e044 b.n 800415e <SD_FindSCR+0x19e>
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
80040d4: 687b ldr r3, [r7, #4]
80040d6: 681b ldr r3, [r3, #0]
80040d8: 6b5b ldr r3, [r3, #52] ; 0x34
80040da: f003 0302 and.w r3, r3, #2
80040de: 2b00 cmp r3, #0
80040e0: d005 beq.n 80040ee <SD_FindSCR+0x12e>
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
80040e2: 687b ldr r3, [r7, #4]
80040e4: 681b ldr r3, [r3, #0]
80040e6: 2202 movs r2, #2
80040e8: 639a str r2, [r3, #56] ; 0x38
return HAL_SD_ERROR_DATA_CRC_FAIL;
80040ea: 2302 movs r3, #2
80040ec: e037 b.n 800415e <SD_FindSCR+0x19e>
}
else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
80040ee: 687b ldr r3, [r7, #4]
80040f0: 681b ldr r3, [r3, #0]
80040f2: 6b5b ldr r3, [r3, #52] ; 0x34
80040f4: f003 0320 and.w r3, r3, #32
80040f8: 2b00 cmp r3, #0
80040fa: d005 beq.n 8004108 <SD_FindSCR+0x148>
{
__HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
80040fc: 687b ldr r3, [r7, #4]
80040fe: 681b ldr r3, [r3, #0]
8004100: 2220 movs r2, #32
8004102: 639a str r2, [r3, #56] ; 0x38
return HAL_SD_ERROR_RX_OVERRUN;
8004104: 2320 movs r3, #32
8004106: e02a b.n 800415e <SD_FindSCR+0x19e>
}
else
{
/* No error flag set */
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_DATA_FLAGS);
8004108: 687b ldr r3, [r7, #4]
800410a: 681b ldr r3, [r3, #0]
800410c: f240 523a movw r2, #1338 ; 0x53a
8004110: 639a str r2, [r3, #56] ; 0x38
*scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
8004112: 68fb ldr r3, [r7, #12]
8004114: 061a lsls r2, r3, #24
8004116: 68fb ldr r3, [r7, #12]
8004118: 021b lsls r3, r3, #8
800411a: f403 037f and.w r3, r3, #16711680 ; 0xff0000
800411e: 431a orrs r2, r3
((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
8004120: 68fb ldr r3, [r7, #12]
8004122: 0a1b lsrs r3, r3, #8
8004124: f403 437f and.w r3, r3, #65280 ; 0xff00
*scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
8004128: 431a orrs r2, r3
((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24));
800412a: 68fb ldr r3, [r7, #12]
800412c: 0e1b lsrs r3, r3, #24
800412e: 431a orrs r2, r3
*scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\
8004130: 6afb ldr r3, [r7, #44] ; 0x2c
8004132: 601a str r2, [r3, #0]
scr++;
8004134: 6afb ldr r3, [r7, #44] ; 0x2c
8004136: 3304 adds r3, #4
8004138: 62fb str r3, [r7, #44] ; 0x2c
*scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
800413a: 68bb ldr r3, [r7, #8]
800413c: 061a lsls r2, r3, #24
800413e: 68bb ldr r3, [r7, #8]
8004140: 021b lsls r3, r3, #8
8004142: f403 037f and.w r3, r3, #16711680 ; 0xff0000
8004146: 431a orrs r2, r3
((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
8004148: 68bb ldr r3, [r7, #8]
800414a: 0a1b lsrs r3, r3, #8
800414c: f403 437f and.w r3, r3, #65280 ; 0xff00
*scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
8004150: 431a orrs r2, r3
((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24));
8004152: 68bb ldr r3, [r7, #8]
8004154: 0e1b lsrs r3, r3, #24
8004156: 431a orrs r2, r3
*scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\
8004158: 6afb ldr r3, [r7, #44] ; 0x2c
800415a: 601a str r2, [r3, #0]
}
return HAL_SD_ERROR_NONE;
800415c: 2300 movs r3, #0
}
800415e: 4618 mov r0, r3
8004160: 373c adds r7, #60 ; 0x3c
8004162: 46bd mov sp, r7
8004164: bd90 pop {r4, r7, pc}
08004166 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
8004166: b580 push {r7, lr}
8004168: b082 sub sp, #8
800416a: af00 add r7, sp, #0
800416c: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
800416e: 687b ldr r3, [r7, #4]
8004170: 2b00 cmp r3, #0
8004172: d101 bne.n 8004178 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
8004174: 2301 movs r3, #1
8004176: e07b b.n 8004270 <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
8004178: 687b ldr r3, [r7, #4]
800417a: 6a5b ldr r3, [r3, #36] ; 0x24
800417c: 2b00 cmp r3, #0
800417e: d108 bne.n 8004192 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
8004180: 687b ldr r3, [r7, #4]
8004182: 685b ldr r3, [r3, #4]
8004184: f5b3 7f82 cmp.w r3, #260 ; 0x104
8004188: d009 beq.n 800419e <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
800418a: 687b ldr r3, [r7, #4]
800418c: 2200 movs r2, #0
800418e: 61da str r2, [r3, #28]
8004190: e005 b.n 800419e <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
8004192: 687b ldr r3, [r7, #4]
8004194: 2200 movs r2, #0
8004196: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8004198: 687b ldr r3, [r7, #4]
800419a: 2200 movs r2, #0
800419c: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
800419e: 687b ldr r3, [r7, #4]
80041a0: 2200 movs r2, #0
80041a2: 629a str r2, [r3, #40] ; 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
80041a4: 687b ldr r3, [r7, #4]
80041a6: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
80041aa: b2db uxtb r3, r3
80041ac: 2b00 cmp r3, #0
80041ae: d106 bne.n 80041be <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
80041b0: 687b ldr r3, [r7, #4]
80041b2: 2200 movs r2, #0
80041b4: f883 2050 strb.w r2, [r3, #80] ; 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
80041b8: 6878 ldr r0, [r7, #4]
80041ba: f7fc fced bl 8000b98 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
80041be: 687b ldr r3, [r7, #4]
80041c0: 2202 movs r2, #2
80041c2: f883 2051 strb.w r2, [r3, #81] ; 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80041c6: 687b ldr r3, [r7, #4]
80041c8: 681b ldr r3, [r3, #0]
80041ca: 681a ldr r2, [r3, #0]
80041cc: 687b ldr r3, [r7, #4]
80041ce: 681b ldr r3, [r3, #0]
80041d0: f022 0240 bic.w r2, r2, #64 ; 0x40
80041d4: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
80041d6: 687b ldr r3, [r7, #4]
80041d8: 685b ldr r3, [r3, #4]
80041da: f403 7282 and.w r2, r3, #260 ; 0x104
80041de: 687b ldr r3, [r7, #4]
80041e0: 689b ldr r3, [r3, #8]
80041e2: f403 4304 and.w r3, r3, #33792 ; 0x8400
80041e6: 431a orrs r2, r3
80041e8: 687b ldr r3, [r7, #4]
80041ea: 68db ldr r3, [r3, #12]
80041ec: f403 6300 and.w r3, r3, #2048 ; 0x800
80041f0: 431a orrs r2, r3
80041f2: 687b ldr r3, [r7, #4]
80041f4: 691b ldr r3, [r3, #16]
80041f6: f003 0302 and.w r3, r3, #2
80041fa: 431a orrs r2, r3
80041fc: 687b ldr r3, [r7, #4]
80041fe: 695b ldr r3, [r3, #20]
8004200: f003 0301 and.w r3, r3, #1
8004204: 431a orrs r2, r3
8004206: 687b ldr r3, [r7, #4]
8004208: 699b ldr r3, [r3, #24]
800420a: f403 7300 and.w r3, r3, #512 ; 0x200
800420e: 431a orrs r2, r3
8004210: 687b ldr r3, [r7, #4]
8004212: 69db ldr r3, [r3, #28]
8004214: f003 0338 and.w r3, r3, #56 ; 0x38
8004218: 431a orrs r2, r3
800421a: 687b ldr r3, [r7, #4]
800421c: 6a1b ldr r3, [r3, #32]
800421e: f003 0380 and.w r3, r3, #128 ; 0x80
8004222: ea42 0103 orr.w r1, r2, r3
8004226: 687b ldr r3, [r7, #4]
8004228: 6a9b ldr r3, [r3, #40] ; 0x28
800422a: f403 5200 and.w r2, r3, #8192 ; 0x2000
800422e: 687b ldr r3, [r7, #4]
8004230: 681b ldr r3, [r3, #0]
8004232: 430a orrs r2, r1
8004234: 601a str r2, [r3, #0]
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
8004236: 687b ldr r3, [r7, #4]
8004238: 699b ldr r3, [r3, #24]
800423a: 0c1b lsrs r3, r3, #16
800423c: f003 0104 and.w r1, r3, #4
8004240: 687b ldr r3, [r7, #4]
8004242: 6a5b ldr r3, [r3, #36] ; 0x24
8004244: f003 0210 and.w r2, r3, #16
8004248: 687b ldr r3, [r7, #4]
800424a: 681b ldr r3, [r3, #0]
800424c: 430a orrs r2, r1
800424e: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8004250: 687b ldr r3, [r7, #4]
8004252: 681b ldr r3, [r3, #0]
8004254: 69da ldr r2, [r3, #28]
8004256: 687b ldr r3, [r7, #4]
8004258: 681b ldr r3, [r3, #0]
800425a: f422 6200 bic.w r2, r2, #2048 ; 0x800
800425e: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8004260: 687b ldr r3, [r7, #4]
8004262: 2200 movs r2, #0
8004264: 655a str r2, [r3, #84] ; 0x54
hspi->State = HAL_SPI_STATE_READY;
8004266: 687b ldr r3, [r7, #4]
8004268: 2201 movs r2, #1
800426a: f883 2051 strb.w r2, [r3, #81] ; 0x51
return HAL_OK;
800426e: 2300 movs r3, #0
}
8004270: 4618 mov r0, r3
8004272: 3708 adds r7, #8
8004274: 46bd mov sp, r7
8004276: bd80 pop {r7, pc}
08004278 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8004278: b580 push {r7, lr}
800427a: b082 sub sp, #8
800427c: af00 add r7, sp, #0
800427e: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8004280: 687b ldr r3, [r7, #4]
8004282: 2b00 cmp r3, #0
8004284: d101 bne.n 800428a <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8004286: 2301 movs r3, #1
8004288: e03f b.n 800430a <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
800428a: 687b ldr r3, [r7, #4]
800428c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8004290: b2db uxtb r3, r3
8004292: 2b00 cmp r3, #0
8004294: d106 bne.n 80042a4 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8004296: 687b ldr r3, [r7, #4]
8004298: 2200 movs r2, #0
800429a: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
800429e: 6878 ldr r0, [r7, #4]
80042a0: f7fc fce2 bl 8000c68 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80042a4: 687b ldr r3, [r7, #4]
80042a6: 2224 movs r2, #36 ; 0x24
80042a8: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
80042ac: 687b ldr r3, [r7, #4]
80042ae: 681b ldr r3, [r3, #0]
80042b0: 68da ldr r2, [r3, #12]
80042b2: 687b ldr r3, [r7, #4]
80042b4: 681b ldr r3, [r3, #0]
80042b6: f422 5200 bic.w r2, r2, #8192 ; 0x2000
80042ba: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
80042bc: 6878 ldr r0, [r7, #4]
80042be: f000 f829 bl 8004314 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80042c2: 687b ldr r3, [r7, #4]
80042c4: 681b ldr r3, [r3, #0]
80042c6: 691a ldr r2, [r3, #16]
80042c8: 687b ldr r3, [r7, #4]
80042ca: 681b ldr r3, [r3, #0]
80042cc: f422 4290 bic.w r2, r2, #18432 ; 0x4800
80042d0: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80042d2: 687b ldr r3, [r7, #4]
80042d4: 681b ldr r3, [r3, #0]
80042d6: 695a ldr r2, [r3, #20]
80042d8: 687b ldr r3, [r7, #4]
80042da: 681b ldr r3, [r3, #0]
80042dc: f022 022a bic.w r2, r2, #42 ; 0x2a
80042e0: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
80042e2: 687b ldr r3, [r7, #4]
80042e4: 681b ldr r3, [r3, #0]
80042e6: 68da ldr r2, [r3, #12]
80042e8: 687b ldr r3, [r7, #4]
80042ea: 681b ldr r3, [r3, #0]
80042ec: f442 5200 orr.w r2, r2, #8192 ; 0x2000
80042f0: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80042f2: 687b ldr r3, [r7, #4]
80042f4: 2200 movs r2, #0
80042f6: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
80042f8: 687b ldr r3, [r7, #4]
80042fa: 2220 movs r2, #32
80042fc: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
8004300: 687b ldr r3, [r7, #4]
8004302: 2220 movs r2, #32
8004304: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8004308: 2300 movs r3, #0
}
800430a: 4618 mov r0, r3
800430c: 3708 adds r7, #8
800430e: 46bd mov sp, r7
8004310: bd80 pop {r7, pc}
...
08004314 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8004314: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004318: b09f sub sp, #124 ; 0x7c
800431a: af00 add r7, sp, #0
800431c: 66f8 str r0, [r7, #108] ; 0x6c
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
800431e: 6efb ldr r3, [r7, #108] ; 0x6c
8004320: 681b ldr r3, [r3, #0]
8004322: 691b ldr r3, [r3, #16]
8004324: f423 5040 bic.w r0, r3, #12288 ; 0x3000
8004328: 6efb ldr r3, [r7, #108] ; 0x6c
800432a: 68d9 ldr r1, [r3, #12]
800432c: 6efb ldr r3, [r7, #108] ; 0x6c
800432e: 681a ldr r2, [r3, #0]
8004330: ea40 0301 orr.w r3, r0, r1
8004334: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8004336: 6efb ldr r3, [r7, #108] ; 0x6c
8004338: 689a ldr r2, [r3, #8]
800433a: 6efb ldr r3, [r7, #108] ; 0x6c
800433c: 691b ldr r3, [r3, #16]
800433e: 431a orrs r2, r3
8004340: 6efb ldr r3, [r7, #108] ; 0x6c
8004342: 695b ldr r3, [r3, #20]
8004344: 431a orrs r2, r3
8004346: 6efb ldr r3, [r7, #108] ; 0x6c
8004348: 69db ldr r3, [r3, #28]
800434a: 4313 orrs r3, r2
800434c: 673b str r3, [r7, #112] ; 0x70
MODIFY_REG(huart->Instance->CR1,
800434e: 6efb ldr r3, [r7, #108] ; 0x6c
8004350: 681b ldr r3, [r3, #0]
8004352: 68db ldr r3, [r3, #12]
8004354: f423 4116 bic.w r1, r3, #38400 ; 0x9600
8004358: f021 010c bic.w r1, r1, #12
800435c: 6efb ldr r3, [r7, #108] ; 0x6c
800435e: 681a ldr r2, [r3, #0]
8004360: 6f3b ldr r3, [r7, #112] ; 0x70
8004362: 430b orrs r3, r1
8004364: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8004366: 6efb ldr r3, [r7, #108] ; 0x6c
8004368: 681b ldr r3, [r3, #0]
800436a: 695b ldr r3, [r3, #20]
800436c: f423 7040 bic.w r0, r3, #768 ; 0x300
8004370: 6efb ldr r3, [r7, #108] ; 0x6c
8004372: 6999 ldr r1, [r3, #24]
8004374: 6efb ldr r3, [r7, #108] ; 0x6c
8004376: 681a ldr r2, [r3, #0]
8004378: ea40 0301 orr.w r3, r0, r1
800437c: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
800437e: 6efb ldr r3, [r7, #108] ; 0x6c
8004380: 681a ldr r2, [r3, #0]
8004382: 4bc5 ldr r3, [pc, #788] ; (8004698 <UART_SetConfig+0x384>)
8004384: 429a cmp r2, r3
8004386: d004 beq.n 8004392 <UART_SetConfig+0x7e>
8004388: 6efb ldr r3, [r7, #108] ; 0x6c
800438a: 681a ldr r2, [r3, #0]
800438c: 4bc3 ldr r3, [pc, #780] ; (800469c <UART_SetConfig+0x388>)
800438e: 429a cmp r2, r3
8004390: d103 bne.n 800439a <UART_SetConfig+0x86>
{
pclk = HAL_RCC_GetPCLK2Freq();
8004392: f7fe fcef bl 8002d74 <HAL_RCC_GetPCLK2Freq>
8004396: 6778 str r0, [r7, #116] ; 0x74
8004398: e002 b.n 80043a0 <UART_SetConfig+0x8c>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
800439a: f7fe fcd7 bl 8002d4c <HAL_RCC_GetPCLK1Freq>
800439e: 6778 str r0, [r7, #116] ; 0x74
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80043a0: 6efb ldr r3, [r7, #108] ; 0x6c
80043a2: 69db ldr r3, [r3, #28]
80043a4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80043a8: f040 80b6 bne.w 8004518 <UART_SetConfig+0x204>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
80043ac: 6f7b ldr r3, [r7, #116] ; 0x74
80043ae: 461c mov r4, r3
80043b0: f04f 0500 mov.w r5, #0
80043b4: 4622 mov r2, r4
80043b6: 462b mov r3, r5
80043b8: 1891 adds r1, r2, r2
80043ba: 6439 str r1, [r7, #64] ; 0x40
80043bc: 415b adcs r3, r3
80043be: 647b str r3, [r7, #68] ; 0x44
80043c0: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
80043c4: 1912 adds r2, r2, r4
80043c6: eb45 0303 adc.w r3, r5, r3
80043ca: f04f 0000 mov.w r0, #0
80043ce: f04f 0100 mov.w r1, #0
80043d2: 00d9 lsls r1, r3, #3
80043d4: ea41 7152 orr.w r1, r1, r2, lsr #29
80043d8: 00d0 lsls r0, r2, #3
80043da: 4602 mov r2, r0
80043dc: 460b mov r3, r1
80043de: 1911 adds r1, r2, r4
80043e0: 6639 str r1, [r7, #96] ; 0x60
80043e2: 416b adcs r3, r5
80043e4: 667b str r3, [r7, #100] ; 0x64
80043e6: 6efb ldr r3, [r7, #108] ; 0x6c
80043e8: 685b ldr r3, [r3, #4]
80043ea: 461a mov r2, r3
80043ec: f04f 0300 mov.w r3, #0
80043f0: 1891 adds r1, r2, r2
80043f2: 63b9 str r1, [r7, #56] ; 0x38
80043f4: 415b adcs r3, r3
80043f6: 63fb str r3, [r7, #60] ; 0x3c
80043f8: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
80043fc: e9d7 0118 ldrd r0, r1, [r7, #96] ; 0x60
8004400: f7fb feea bl 80001d8 <__aeabi_uldivmod>
8004404: 4602 mov r2, r0
8004406: 460b mov r3, r1
8004408: 4ba5 ldr r3, [pc, #660] ; (80046a0 <UART_SetConfig+0x38c>)
800440a: fba3 2302 umull r2, r3, r3, r2
800440e: 095b lsrs r3, r3, #5
8004410: 011e lsls r6, r3, #4
8004412: 6f7b ldr r3, [r7, #116] ; 0x74
8004414: 461c mov r4, r3
8004416: f04f 0500 mov.w r5, #0
800441a: 4622 mov r2, r4
800441c: 462b mov r3, r5
800441e: 1891 adds r1, r2, r2
8004420: 6339 str r1, [r7, #48] ; 0x30
8004422: 415b adcs r3, r3
8004424: 637b str r3, [r7, #52] ; 0x34
8004426: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30
800442a: 1912 adds r2, r2, r4
800442c: eb45 0303 adc.w r3, r5, r3
8004430: f04f 0000 mov.w r0, #0
8004434: f04f 0100 mov.w r1, #0
8004438: 00d9 lsls r1, r3, #3
800443a: ea41 7152 orr.w r1, r1, r2, lsr #29
800443e: 00d0 lsls r0, r2, #3
8004440: 4602 mov r2, r0
8004442: 460b mov r3, r1
8004444: 1911 adds r1, r2, r4
8004446: 65b9 str r1, [r7, #88] ; 0x58
8004448: 416b adcs r3, r5
800444a: 65fb str r3, [r7, #92] ; 0x5c
800444c: 6efb ldr r3, [r7, #108] ; 0x6c
800444e: 685b ldr r3, [r3, #4]
8004450: 461a mov r2, r3
8004452: f04f 0300 mov.w r3, #0
8004456: 1891 adds r1, r2, r2
8004458: 62b9 str r1, [r7, #40] ; 0x28
800445a: 415b adcs r3, r3
800445c: 62fb str r3, [r7, #44] ; 0x2c
800445e: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
8004462: e9d7 0116 ldrd r0, r1, [r7, #88] ; 0x58
8004466: f7fb feb7 bl 80001d8 <__aeabi_uldivmod>
800446a: 4602 mov r2, r0
800446c: 460b mov r3, r1
800446e: 4b8c ldr r3, [pc, #560] ; (80046a0 <UART_SetConfig+0x38c>)
8004470: fba3 1302 umull r1, r3, r3, r2
8004474: 095b lsrs r3, r3, #5
8004476: 2164 movs r1, #100 ; 0x64
8004478: fb01 f303 mul.w r3, r1, r3
800447c: 1ad3 subs r3, r2, r3
800447e: 00db lsls r3, r3, #3
8004480: 3332 adds r3, #50 ; 0x32
8004482: 4a87 ldr r2, [pc, #540] ; (80046a0 <UART_SetConfig+0x38c>)
8004484: fba2 2303 umull r2, r3, r2, r3
8004488: 095b lsrs r3, r3, #5
800448a: 005b lsls r3, r3, #1
800448c: f403 73f8 and.w r3, r3, #496 ; 0x1f0
8004490: 441e add r6, r3
8004492: 6f7b ldr r3, [r7, #116] ; 0x74
8004494: 4618 mov r0, r3
8004496: f04f 0100 mov.w r1, #0
800449a: 4602 mov r2, r0
800449c: 460b mov r3, r1
800449e: 1894 adds r4, r2, r2
80044a0: 623c str r4, [r7, #32]
80044a2: 415b adcs r3, r3
80044a4: 627b str r3, [r7, #36] ; 0x24
80044a6: e9d7 2308 ldrd r2, r3, [r7, #32]
80044aa: 1812 adds r2, r2, r0
80044ac: eb41 0303 adc.w r3, r1, r3
80044b0: f04f 0400 mov.w r4, #0
80044b4: f04f 0500 mov.w r5, #0
80044b8: 00dd lsls r5, r3, #3
80044ba: ea45 7552 orr.w r5, r5, r2, lsr #29
80044be: 00d4 lsls r4, r2, #3
80044c0: 4622 mov r2, r4
80044c2: 462b mov r3, r5
80044c4: 1814 adds r4, r2, r0
80044c6: 653c str r4, [r7, #80] ; 0x50
80044c8: 414b adcs r3, r1
80044ca: 657b str r3, [r7, #84] ; 0x54
80044cc: 6efb ldr r3, [r7, #108] ; 0x6c
80044ce: 685b ldr r3, [r3, #4]
80044d0: 461a mov r2, r3
80044d2: f04f 0300 mov.w r3, #0
80044d6: 1891 adds r1, r2, r2
80044d8: 61b9 str r1, [r7, #24]
80044da: 415b adcs r3, r3
80044dc: 61fb str r3, [r7, #28]
80044de: e9d7 2306 ldrd r2, r3, [r7, #24]
80044e2: e9d7 0114 ldrd r0, r1, [r7, #80] ; 0x50
80044e6: f7fb fe77 bl 80001d8 <__aeabi_uldivmod>
80044ea: 4602 mov r2, r0
80044ec: 460b mov r3, r1
80044ee: 4b6c ldr r3, [pc, #432] ; (80046a0 <UART_SetConfig+0x38c>)
80044f0: fba3 1302 umull r1, r3, r3, r2
80044f4: 095b lsrs r3, r3, #5
80044f6: 2164 movs r1, #100 ; 0x64
80044f8: fb01 f303 mul.w r3, r1, r3
80044fc: 1ad3 subs r3, r2, r3
80044fe: 00db lsls r3, r3, #3
8004500: 3332 adds r3, #50 ; 0x32
8004502: 4a67 ldr r2, [pc, #412] ; (80046a0 <UART_SetConfig+0x38c>)
8004504: fba2 2303 umull r2, r3, r2, r3
8004508: 095b lsrs r3, r3, #5
800450a: f003 0207 and.w r2, r3, #7
800450e: 6efb ldr r3, [r7, #108] ; 0x6c
8004510: 681b ldr r3, [r3, #0]
8004512: 4432 add r2, r6
8004514: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8004516: e0b9 b.n 800468c <UART_SetConfig+0x378>
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8004518: 6f7b ldr r3, [r7, #116] ; 0x74
800451a: 461c mov r4, r3
800451c: f04f 0500 mov.w r5, #0
8004520: 4622 mov r2, r4
8004522: 462b mov r3, r5
8004524: 1891 adds r1, r2, r2
8004526: 6139 str r1, [r7, #16]
8004528: 415b adcs r3, r3
800452a: 617b str r3, [r7, #20]
800452c: e9d7 2304 ldrd r2, r3, [r7, #16]
8004530: 1912 adds r2, r2, r4
8004532: eb45 0303 adc.w r3, r5, r3
8004536: f04f 0000 mov.w r0, #0
800453a: f04f 0100 mov.w r1, #0
800453e: 00d9 lsls r1, r3, #3
8004540: ea41 7152 orr.w r1, r1, r2, lsr #29
8004544: 00d0 lsls r0, r2, #3
8004546: 4602 mov r2, r0
8004548: 460b mov r3, r1
800454a: eb12 0804 adds.w r8, r2, r4
800454e: eb43 0905 adc.w r9, r3, r5
8004552: 6efb ldr r3, [r7, #108] ; 0x6c
8004554: 685b ldr r3, [r3, #4]
8004556: 4618 mov r0, r3
8004558: f04f 0100 mov.w r1, #0
800455c: f04f 0200 mov.w r2, #0
8004560: f04f 0300 mov.w r3, #0
8004564: 008b lsls r3, r1, #2
8004566: ea43 7390 orr.w r3, r3, r0, lsr #30
800456a: 0082 lsls r2, r0, #2
800456c: 4640 mov r0, r8
800456e: 4649 mov r1, r9
8004570: f7fb fe32 bl 80001d8 <__aeabi_uldivmod>
8004574: 4602 mov r2, r0
8004576: 460b mov r3, r1
8004578: 4b49 ldr r3, [pc, #292] ; (80046a0 <UART_SetConfig+0x38c>)
800457a: fba3 2302 umull r2, r3, r3, r2
800457e: 095b lsrs r3, r3, #5
8004580: 011e lsls r6, r3, #4
8004582: 6f7b ldr r3, [r7, #116] ; 0x74
8004584: 4618 mov r0, r3
8004586: f04f 0100 mov.w r1, #0
800458a: 4602 mov r2, r0
800458c: 460b mov r3, r1
800458e: 1894 adds r4, r2, r2
8004590: 60bc str r4, [r7, #8]
8004592: 415b adcs r3, r3
8004594: 60fb str r3, [r7, #12]
8004596: e9d7 2302 ldrd r2, r3, [r7, #8]
800459a: 1812 adds r2, r2, r0
800459c: eb41 0303 adc.w r3, r1, r3
80045a0: f04f 0400 mov.w r4, #0
80045a4: f04f 0500 mov.w r5, #0
80045a8: 00dd lsls r5, r3, #3
80045aa: ea45 7552 orr.w r5, r5, r2, lsr #29
80045ae: 00d4 lsls r4, r2, #3
80045b0: 4622 mov r2, r4
80045b2: 462b mov r3, r5
80045b4: 1814 adds r4, r2, r0
80045b6: 64bc str r4, [r7, #72] ; 0x48
80045b8: 414b adcs r3, r1
80045ba: 64fb str r3, [r7, #76] ; 0x4c
80045bc: 6efb ldr r3, [r7, #108] ; 0x6c
80045be: 685b ldr r3, [r3, #4]
80045c0: 4618 mov r0, r3
80045c2: f04f 0100 mov.w r1, #0
80045c6: f04f 0200 mov.w r2, #0
80045ca: f04f 0300 mov.w r3, #0
80045ce: 008b lsls r3, r1, #2
80045d0: ea43 7390 orr.w r3, r3, r0, lsr #30
80045d4: 0082 lsls r2, r0, #2
80045d6: e9d7 0112 ldrd r0, r1, [r7, #72] ; 0x48
80045da: f7fb fdfd bl 80001d8 <__aeabi_uldivmod>
80045de: 4602 mov r2, r0
80045e0: 460b mov r3, r1
80045e2: 4b2f ldr r3, [pc, #188] ; (80046a0 <UART_SetConfig+0x38c>)
80045e4: fba3 1302 umull r1, r3, r3, r2
80045e8: 095b lsrs r3, r3, #5
80045ea: 2164 movs r1, #100 ; 0x64
80045ec: fb01 f303 mul.w r3, r1, r3
80045f0: 1ad3 subs r3, r2, r3
80045f2: 011b lsls r3, r3, #4
80045f4: 3332 adds r3, #50 ; 0x32
80045f6: 4a2a ldr r2, [pc, #168] ; (80046a0 <UART_SetConfig+0x38c>)
80045f8: fba2 2303 umull r2, r3, r2, r3
80045fc: 095b lsrs r3, r3, #5
80045fe: f003 03f0 and.w r3, r3, #240 ; 0xf0
8004602: 441e add r6, r3
8004604: 6f7b ldr r3, [r7, #116] ; 0x74
8004606: 4618 mov r0, r3
8004608: f04f 0100 mov.w r1, #0
800460c: 4602 mov r2, r0
800460e: 460b mov r3, r1
8004610: 1894 adds r4, r2, r2
8004612: 603c str r4, [r7, #0]
8004614: 415b adcs r3, r3
8004616: 607b str r3, [r7, #4]
8004618: e9d7 2300 ldrd r2, r3, [r7]
800461c: 1812 adds r2, r2, r0
800461e: eb41 0303 adc.w r3, r1, r3
8004622: f04f 0400 mov.w r4, #0
8004626: f04f 0500 mov.w r5, #0
800462a: 00dd lsls r5, r3, #3
800462c: ea45 7552 orr.w r5, r5, r2, lsr #29
8004630: 00d4 lsls r4, r2, #3
8004632: 4622 mov r2, r4
8004634: 462b mov r3, r5
8004636: eb12 0a00 adds.w sl, r2, r0
800463a: eb43 0b01 adc.w fp, r3, r1
800463e: 6efb ldr r3, [r7, #108] ; 0x6c
8004640: 685b ldr r3, [r3, #4]
8004642: 4618 mov r0, r3
8004644: f04f 0100 mov.w r1, #0
8004648: f04f 0200 mov.w r2, #0
800464c: f04f 0300 mov.w r3, #0
8004650: 008b lsls r3, r1, #2
8004652: ea43 7390 orr.w r3, r3, r0, lsr #30
8004656: 0082 lsls r2, r0, #2
8004658: 4650 mov r0, sl
800465a: 4659 mov r1, fp
800465c: f7fb fdbc bl 80001d8 <__aeabi_uldivmod>
8004660: 4602 mov r2, r0
8004662: 460b mov r3, r1
8004664: 4b0e ldr r3, [pc, #56] ; (80046a0 <UART_SetConfig+0x38c>)
8004666: fba3 1302 umull r1, r3, r3, r2
800466a: 095b lsrs r3, r3, #5
800466c: 2164 movs r1, #100 ; 0x64
800466e: fb01 f303 mul.w r3, r1, r3
8004672: 1ad3 subs r3, r2, r3
8004674: 011b lsls r3, r3, #4
8004676: 3332 adds r3, #50 ; 0x32
8004678: 4a09 ldr r2, [pc, #36] ; (80046a0 <UART_SetConfig+0x38c>)
800467a: fba2 2303 umull r2, r3, r2, r3
800467e: 095b lsrs r3, r3, #5
8004680: f003 020f and.w r2, r3, #15
8004684: 6efb ldr r3, [r7, #108] ; 0x6c
8004686: 681b ldr r3, [r3, #0]
8004688: 4432 add r2, r6
800468a: 609a str r2, [r3, #8]
}
800468c: bf00 nop
800468e: 377c adds r7, #124 ; 0x7c
8004690: 46bd mov sp, r7
8004692: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8004696: bf00 nop
8004698: 40011000 .word 0x40011000
800469c: 40011400 .word 0x40011400
80046a0: 51eb851f .word 0x51eb851f
080046a4 <SDIO_Init>:
* @param SDIOx: Pointer to SDMMC register base
* @param Init: SDMMC initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
{
80046a4: b084 sub sp, #16
80046a6: b480 push {r7}
80046a8: b085 sub sp, #20
80046aa: af00 add r7, sp, #0
80046ac: 6078 str r0, [r7, #4]
80046ae: f107 001c add.w r0, r7, #28
80046b2: e880 000e stmia.w r0, {r1, r2, r3}
uint32_t tmpreg = 0;
80046b6: 2300 movs r3, #0
80046b8: 60fb str r3, [r7, #12]
assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
/* Set SDMMC configuration parameters */
tmpreg |= (Init.ClockEdge |\
80046ba: 69fa ldr r2, [r7, #28]
Init.ClockBypass |\
80046bc: 6a3b ldr r3, [r7, #32]
tmpreg |= (Init.ClockEdge |\
80046be: 431a orrs r2, r3
Init.ClockPowerSave |\
80046c0: 6a7b ldr r3, [r7, #36] ; 0x24
Init.ClockBypass |\
80046c2: 431a orrs r2, r3
Init.BusWide |\
80046c4: 6abb ldr r3, [r7, #40] ; 0x28
Init.ClockPowerSave |\
80046c6: 431a orrs r2, r3
Init.HardwareFlowControl |\
80046c8: 6afb ldr r3, [r7, #44] ; 0x2c
Init.BusWide |\
80046ca: 431a orrs r2, r3
Init.ClockDiv
80046cc: 6b3b ldr r3, [r7, #48] ; 0x30
Init.HardwareFlowControl |\
80046ce: 4313 orrs r3, r2
tmpreg |= (Init.ClockEdge |\
80046d0: 68fa ldr r2, [r7, #12]
80046d2: 4313 orrs r3, r2
80046d4: 60fb str r3, [r7, #12]
);
/* Write to SDMMC CLKCR */
MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
80046d6: 687b ldr r3, [r7, #4]
80046d8: 685b ldr r3, [r3, #4]
80046da: f423 43fd bic.w r3, r3, #32384 ; 0x7e80
80046de: f023 037f bic.w r3, r3, #127 ; 0x7f
80046e2: 68fa ldr r2, [r7, #12]
80046e4: 431a orrs r2, r3
80046e6: 687b ldr r3, [r7, #4]
80046e8: 605a str r2, [r3, #4]
return HAL_OK;
80046ea: 2300 movs r3, #0
}
80046ec: 4618 mov r0, r3
80046ee: 3714 adds r7, #20
80046f0: 46bd mov sp, r7
80046f2: f85d 7b04 ldr.w r7, [sp], #4
80046f6: b004 add sp, #16
80046f8: 4770 bx lr
080046fa <SDIO_ReadFIFO>:
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
* @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
{
80046fa: b480 push {r7}
80046fc: b083 sub sp, #12
80046fe: af00 add r7, sp, #0
8004700: 6078 str r0, [r7, #4]
/* Read data from Rx FIFO */
return (SDIOx->FIFO);
8004702: 687b ldr r3, [r7, #4]
8004704: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
}
8004708: 4618 mov r0, r3
800470a: 370c adds r7, #12
800470c: 46bd mov sp, r7
800470e: f85d 7b04 ldr.w r7, [sp], #4
8004712: 4770 bx lr
08004714 <SDIO_PowerState_ON>:
* @brief Set SDMMC Power state to ON.
* @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
{
8004714: b580 push {r7, lr}
8004716: b082 sub sp, #8
8004718: af00 add r7, sp, #0
800471a: 6078 str r0, [r7, #4]
/* Set power state to ON */
SDIOx->POWER = SDIO_POWER_PWRCTRL;
800471c: 687b ldr r3, [r7, #4]
800471e: 2203 movs r2, #3
8004720: 601a str r2, [r3, #0]
/* 1ms: required power up waiting time before starting the SD initialization
sequence */
HAL_Delay(2);
8004722: 2002 movs r0, #2
8004724: f7fc fc2c bl 8000f80 <HAL_Delay>
return HAL_OK;
8004728: 2300 movs r3, #0
}
800472a: 4618 mov r0, r3
800472c: 3708 adds r7, #8
800472e: 46bd mov sp, r7
8004730: bd80 pop {r7, pc}
08004732 <SDIO_GetPowerState>:
* - 0x00: Power OFF
* - 0x02: Power UP
* - 0x03: Power ON
*/
uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
{
8004732: b480 push {r7}
8004734: b083 sub sp, #12
8004736: af00 add r7, sp, #0
8004738: 6078 str r0, [r7, #4]
return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
800473a: 687b ldr r3, [r7, #4]
800473c: 681b ldr r3, [r3, #0]
800473e: f003 0303 and.w r3, r3, #3
}
8004742: 4618 mov r0, r3
8004744: 370c adds r7, #12
8004746: 46bd mov sp, r7
8004748: f85d 7b04 ldr.w r7, [sp], #4
800474c: 4770 bx lr
0800474e <SDIO_SendCommand>:
* @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains
* the configuration information for the SDMMC command
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
{
800474e: b480 push {r7}
8004750: b085 sub sp, #20
8004752: af00 add r7, sp, #0
8004754: 6078 str r0, [r7, #4]
8004756: 6039 str r1, [r7, #0]
uint32_t tmpreg = 0;
8004758: 2300 movs r3, #0
800475a: 60fb str r3, [r7, #12]
assert_param(IS_SDIO_RESPONSE(Command->Response));
assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
assert_param(IS_SDIO_CPSM(Command->CPSM));
/* Set the SDMMC Argument value */
SDIOx->ARG = Command->Argument;
800475c: 683b ldr r3, [r7, #0]
800475e: 681a ldr r2, [r3, #0]
8004760: 687b ldr r3, [r7, #4]
8004762: 609a str r2, [r3, #8]
/* Set SDMMC command parameters */
tmpreg |= (uint32_t)(Command->CmdIndex |\
8004764: 683b ldr r3, [r7, #0]
8004766: 685a ldr r2, [r3, #4]
Command->Response |\
8004768: 683b ldr r3, [r7, #0]
800476a: 689b ldr r3, [r3, #8]
tmpreg |= (uint32_t)(Command->CmdIndex |\
800476c: 431a orrs r2, r3
Command->WaitForInterrupt |\
800476e: 683b ldr r3, [r7, #0]
8004770: 68db ldr r3, [r3, #12]
Command->Response |\
8004772: 431a orrs r2, r3
Command->CPSM);
8004774: 683b ldr r3, [r7, #0]
8004776: 691b ldr r3, [r3, #16]
Command->WaitForInterrupt |\
8004778: 4313 orrs r3, r2
tmpreg |= (uint32_t)(Command->CmdIndex |\
800477a: 68fa ldr r2, [r7, #12]
800477c: 4313 orrs r3, r2
800477e: 60fb str r3, [r7, #12]
/* Write to SDMMC CMD register */
MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
8004780: 687b ldr r3, [r7, #4]
8004782: 68db ldr r3, [r3, #12]
8004784: f423 637f bic.w r3, r3, #4080 ; 0xff0
8004788: f023 030f bic.w r3, r3, #15
800478c: 68fa ldr r2, [r7, #12]
800478e: 431a orrs r2, r3
8004790: 687b ldr r3, [r7, #4]
8004792: 60da str r2, [r3, #12]
return HAL_OK;
8004794: 2300 movs r3, #0
}
8004796: 4618 mov r0, r3
8004798: 3714 adds r7, #20
800479a: 46bd mov sp, r7
800479c: f85d 7b04 ldr.w r7, [sp], #4
80047a0: 4770 bx lr
080047a2 <SDIO_GetCommandResponse>:
* @brief Return the command index of last command for which response received
* @param SDIOx: Pointer to SDMMC register base
* @retval Command index of the last command response received
*/
uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
{
80047a2: b480 push {r7}
80047a4: b083 sub sp, #12
80047a6: af00 add r7, sp, #0
80047a8: 6078 str r0, [r7, #4]
return (uint8_t)(SDIOx->RESPCMD);
80047aa: 687b ldr r3, [r7, #4]
80047ac: 691b ldr r3, [r3, #16]
80047ae: b2db uxtb r3, r3
}
80047b0: 4618 mov r0, r3
80047b2: 370c adds r7, #12
80047b4: 46bd mov sp, r7
80047b6: f85d 7b04 ldr.w r7, [sp], #4
80047ba: 4770 bx lr
080047bc <SDIO_GetResponse>:
* @arg SDIO_RESP3: Response Register 3
* @arg SDIO_RESP4: Response Register 4
* @retval The Corresponding response register value
*/
uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
{
80047bc: b480 push {r7}
80047be: b085 sub sp, #20
80047c0: af00 add r7, sp, #0
80047c2: 6078 str r0, [r7, #4]
80047c4: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_SDIO_RESP(Response));
/* Get the response */
tmp = (uint32_t)(&(SDIOx->RESP1)) + Response;
80047c6: 687b ldr r3, [r7, #4]
80047c8: 3314 adds r3, #20
80047ca: 461a mov r2, r3
80047cc: 683b ldr r3, [r7, #0]
80047ce: 4413 add r3, r2
80047d0: 60fb str r3, [r7, #12]
return (*(__IO uint32_t *) tmp);
80047d2: 68fb ldr r3, [r7, #12]
80047d4: 681b ldr r3, [r3, #0]
}
80047d6: 4618 mov r0, r3
80047d8: 3714 adds r7, #20
80047da: 46bd mov sp, r7
80047dc: f85d 7b04 ldr.w r7, [sp], #4
80047e0: 4770 bx lr
080047e2 <SDIO_ConfigData>:
* @param Data : pointer to a SDIO_DataInitTypeDef structure
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
{
80047e2: b480 push {r7}
80047e4: b085 sub sp, #20
80047e6: af00 add r7, sp, #0
80047e8: 6078 str r0, [r7, #4]
80047ea: 6039 str r1, [r7, #0]
uint32_t tmpreg = 0;
80047ec: 2300 movs r3, #0
80047ee: 60fb str r3, [r7, #12]
assert_param(IS_SDIO_TRANSFER_DIR(Data->TransferDir));
assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
assert_param(IS_SDIO_DPSM(Data->DPSM));
/* Set the SDMMC Data TimeOut value */
SDIOx->DTIMER = Data->DataTimeOut;
80047f0: 683b ldr r3, [r7, #0]
80047f2: 681a ldr r2, [r3, #0]
80047f4: 687b ldr r3, [r7, #4]
80047f6: 625a str r2, [r3, #36] ; 0x24
/* Set the SDMMC DataLength value */
SDIOx->DLEN = Data->DataLength;
80047f8: 683b ldr r3, [r7, #0]
80047fa: 685a ldr r2, [r3, #4]
80047fc: 687b ldr r3, [r7, #4]
80047fe: 629a str r2, [r3, #40] ; 0x28
/* Set the SDMMC data configuration parameters */
tmpreg |= (uint32_t)(Data->DataBlockSize |\
8004800: 683b ldr r3, [r7, #0]
8004802: 689a ldr r2, [r3, #8]
Data->TransferDir |\
8004804: 683b ldr r3, [r7, #0]
8004806: 68db ldr r3, [r3, #12]
tmpreg |= (uint32_t)(Data->DataBlockSize |\
8004808: 431a orrs r2, r3
Data->TransferMode |\
800480a: 683b ldr r3, [r7, #0]
800480c: 691b ldr r3, [r3, #16]
Data->TransferDir |\
800480e: 431a orrs r2, r3
Data->DPSM);
8004810: 683b ldr r3, [r7, #0]
8004812: 695b ldr r3, [r3, #20]
Data->TransferMode |\
8004814: 4313 orrs r3, r2
tmpreg |= (uint32_t)(Data->DataBlockSize |\
8004816: 68fa ldr r2, [r7, #12]
8004818: 4313 orrs r3, r2
800481a: 60fb str r3, [r7, #12]
/* Write to SDMMC DCTRL */
MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
800481c: 687b ldr r3, [r7, #4]
800481e: 6adb ldr r3, [r3, #44] ; 0x2c
8004820: f023 02f7 bic.w r2, r3, #247 ; 0xf7
8004824: 68fb ldr r3, [r7, #12]
8004826: 431a orrs r2, r3
8004828: 687b ldr r3, [r7, #4]
800482a: 62da str r2, [r3, #44] ; 0x2c
return HAL_OK;
800482c: 2300 movs r3, #0
}
800482e: 4618 mov r0, r3
8004830: 3714 adds r7, #20
8004832: 46bd mov sp, r7
8004834: f85d 7b04 ldr.w r7, [sp], #4
8004838: 4770 bx lr
0800483a <SDMMC_CmdBlockLength>:
* @brief Send the Data Block Length command and check the response
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
{
800483a: b580 push {r7, lr}
800483c: b088 sub sp, #32
800483e: af00 add r7, sp, #0
8004840: 6078 str r0, [r7, #4]
8004842: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
8004844: 683b ldr r3, [r7, #0]
8004846: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
8004848: 2310 movs r3, #16
800484a: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
800484c: 2340 movs r3, #64 ; 0x40
800484e: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004850: 2300 movs r3, #0
8004852: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004854: f44f 6380 mov.w r3, #1024 ; 0x400
8004858: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
800485a: f107 0308 add.w r3, r7, #8
800485e: 4619 mov r1, r3
8004860: 6878 ldr r0, [r7, #4]
8004862: f7ff ff74 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
8004866: f241 3288 movw r2, #5000 ; 0x1388
800486a: 2110 movs r1, #16
800486c: 6878 ldr r0, [r7, #4]
800486e: f000 fa45 bl 8004cfc <SDMMC_GetCmdResp1>
8004872: 61f8 str r0, [r7, #28]
return errorstate;
8004874: 69fb ldr r3, [r7, #28]
}
8004876: 4618 mov r0, r3
8004878: 3720 adds r7, #32
800487a: 46bd mov sp, r7
800487c: bd80 pop {r7, pc}
0800487e <SDMMC_CmdReadSingleBlock>:
* @brief Send the Read Single Block command and check the response
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
{
800487e: b580 push {r7, lr}
8004880: b088 sub sp, #32
8004882: af00 add r7, sp, #0
8004884: 6078 str r0, [r7, #4]
8004886: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
8004888: 683b ldr r3, [r7, #0]
800488a: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
800488c: 2311 movs r3, #17
800488e: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004890: 2340 movs r3, #64 ; 0x40
8004892: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004894: 2300 movs r3, #0
8004896: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004898: f44f 6380 mov.w r3, #1024 ; 0x400
800489c: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
800489e: f107 0308 add.w r3, r7, #8
80048a2: 4619 mov r1, r3
80048a4: 6878 ldr r0, [r7, #4]
80048a6: f7ff ff52 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
80048aa: f241 3288 movw r2, #5000 ; 0x1388
80048ae: 2111 movs r1, #17
80048b0: 6878 ldr r0, [r7, #4]
80048b2: f000 fa23 bl 8004cfc <SDMMC_GetCmdResp1>
80048b6: 61f8 str r0, [r7, #28]
return errorstate;
80048b8: 69fb ldr r3, [r7, #28]
}
80048ba: 4618 mov r0, r3
80048bc: 3720 adds r7, #32
80048be: 46bd mov sp, r7
80048c0: bd80 pop {r7, pc}
080048c2 <SDMMC_CmdReadMultiBlock>:
* @brief Send the Read Multi Block command and check the response
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
{
80048c2: b580 push {r7, lr}
80048c4: b088 sub sp, #32
80048c6: af00 add r7, sp, #0
80048c8: 6078 str r0, [r7, #4]
80048ca: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
80048cc: 683b ldr r3, [r7, #0]
80048ce: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
80048d0: 2312 movs r3, #18
80048d2: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
80048d4: 2340 movs r3, #64 ; 0x40
80048d6: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
80048d8: 2300 movs r3, #0
80048da: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
80048dc: f44f 6380 mov.w r3, #1024 ; 0x400
80048e0: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
80048e2: f107 0308 add.w r3, r7, #8
80048e6: 4619 mov r1, r3
80048e8: 6878 ldr r0, [r7, #4]
80048ea: f7ff ff30 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
80048ee: f241 3288 movw r2, #5000 ; 0x1388
80048f2: 2112 movs r1, #18
80048f4: 6878 ldr r0, [r7, #4]
80048f6: f000 fa01 bl 8004cfc <SDMMC_GetCmdResp1>
80048fa: 61f8 str r0, [r7, #28]
return errorstate;
80048fc: 69fb ldr r3, [r7, #28]
}
80048fe: 4618 mov r0, r3
8004900: 3720 adds r7, #32
8004902: 46bd mov sp, r7
8004904: bd80 pop {r7, pc}
08004906 <SDMMC_CmdWriteSingleBlock>:
* @brief Send the Write Single Block command and check the response
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
{
8004906: b580 push {r7, lr}
8004908: b088 sub sp, #32
800490a: af00 add r7, sp, #0
800490c: 6078 str r0, [r7, #4]
800490e: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
8004910: 683b ldr r3, [r7, #0]
8004912: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
8004914: 2318 movs r3, #24
8004916: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004918: 2340 movs r3, #64 ; 0x40
800491a: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
800491c: 2300 movs r3, #0
800491e: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004920: f44f 6380 mov.w r3, #1024 ; 0x400
8004924: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004926: f107 0308 add.w r3, r7, #8
800492a: 4619 mov r1, r3
800492c: 6878 ldr r0, [r7, #4]
800492e: f7ff ff0e bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
8004932: f241 3288 movw r2, #5000 ; 0x1388
8004936: 2118 movs r1, #24
8004938: 6878 ldr r0, [r7, #4]
800493a: f000 f9df bl 8004cfc <SDMMC_GetCmdResp1>
800493e: 61f8 str r0, [r7, #28]
return errorstate;
8004940: 69fb ldr r3, [r7, #28]
}
8004942: 4618 mov r0, r3
8004944: 3720 adds r7, #32
8004946: 46bd mov sp, r7
8004948: bd80 pop {r7, pc}
0800494a <SDMMC_CmdWriteMultiBlock>:
* @brief Send the Write Multi Block command and check the response
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
{
800494a: b580 push {r7, lr}
800494c: b088 sub sp, #32
800494e: af00 add r7, sp, #0
8004950: 6078 str r0, [r7, #4]
8004952: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Set Block Size for Card */
sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
8004954: 683b ldr r3, [r7, #0]
8004956: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
8004958: 2319 movs r3, #25
800495a: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
800495c: 2340 movs r3, #64 ; 0x40
800495e: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004960: 2300 movs r3, #0
8004962: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004964: f44f 6380 mov.w r3, #1024 ; 0x400
8004968: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
800496a: f107 0308 add.w r3, r7, #8
800496e: 4619 mov r1, r3
8004970: 6878 ldr r0, [r7, #4]
8004972: f7ff feec bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
8004976: f241 3288 movw r2, #5000 ; 0x1388
800497a: 2119 movs r1, #25
800497c: 6878 ldr r0, [r7, #4]
800497e: f000 f9bd bl 8004cfc <SDMMC_GetCmdResp1>
8004982: 61f8 str r0, [r7, #28]
return errorstate;
8004984: 69fb ldr r3, [r7, #28]
}
8004986: 4618 mov r0, r3
8004988: 3720 adds r7, #32
800498a: 46bd mov sp, r7
800498c: bd80 pop {r7, pc}
...
08004990 <SDMMC_CmdStopTransfer>:
* @brief Send the Stop Transfer command and check the response.
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
{
8004990: b580 push {r7, lr}
8004992: b088 sub sp, #32
8004994: af00 add r7, sp, #0
8004996: 6078 str r0, [r7, #4]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Send CMD12 STOP_TRANSMISSION */
sdmmc_cmdinit.Argument = 0U;
8004998: 2300 movs r3, #0
800499a: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
800499c: 230c movs r3, #12
800499e: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
80049a0: 2340 movs r3, #64 ; 0x40
80049a2: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
80049a4: 2300 movs r3, #0
80049a6: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
80049a8: f44f 6380 mov.w r3, #1024 ; 0x400
80049ac: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
80049ae: f107 0308 add.w r3, r7, #8
80049b2: 4619 mov r1, r3
80049b4: 6878 ldr r0, [r7, #4]
80049b6: f7ff feca bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, SDIO_STOPTRANSFERTIMEOUT);
80049ba: 4a05 ldr r2, [pc, #20] ; (80049d0 <SDMMC_CmdStopTransfer+0x40>)
80049bc: 210c movs r1, #12
80049be: 6878 ldr r0, [r7, #4]
80049c0: f000 f99c bl 8004cfc <SDMMC_GetCmdResp1>
80049c4: 61f8 str r0, [r7, #28]
return errorstate;
80049c6: 69fb ldr r3, [r7, #28]
}
80049c8: 4618 mov r0, r3
80049ca: 3720 adds r7, #32
80049cc: 46bd mov sp, r7
80049ce: bd80 pop {r7, pc}
80049d0: 05f5e100 .word 0x05f5e100
080049d4 <SDMMC_CmdSelDesel>:
* @param SDIOx: Pointer to SDIO register base
* @param addr: Address of the card to be selected
* @retval HAL status
*/
uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
{
80049d4: b580 push {r7, lr}
80049d6: b08a sub sp, #40 ; 0x28
80049d8: af00 add r7, sp, #0
80049da: 60f8 str r0, [r7, #12]
80049dc: e9c7 2300 strd r2, r3, [r7]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Send CMD7 SDMMC_SEL_DESEL_CARD */
sdmmc_cmdinit.Argument = (uint32_t)Addr;
80049e0: 683b ldr r3, [r7, #0]
80049e2: 613b str r3, [r7, #16]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
80049e4: 2307 movs r3, #7
80049e6: 617b str r3, [r7, #20]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
80049e8: 2340 movs r3, #64 ; 0x40
80049ea: 61bb str r3, [r7, #24]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
80049ec: 2300 movs r3, #0
80049ee: 61fb str r3, [r7, #28]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
80049f0: f44f 6380 mov.w r3, #1024 ; 0x400
80049f4: 623b str r3, [r7, #32]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
80049f6: f107 0310 add.w r3, r7, #16
80049fa: 4619 mov r1, r3
80049fc: 68f8 ldr r0, [r7, #12]
80049fe: f7ff fea6 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
8004a02: f241 3288 movw r2, #5000 ; 0x1388
8004a06: 2107 movs r1, #7
8004a08: 68f8 ldr r0, [r7, #12]
8004a0a: f000 f977 bl 8004cfc <SDMMC_GetCmdResp1>
8004a0e: 6278 str r0, [r7, #36] ; 0x24
return errorstate;
8004a10: 6a7b ldr r3, [r7, #36] ; 0x24
}
8004a12: 4618 mov r0, r3
8004a14: 3728 adds r7, #40 ; 0x28
8004a16: 46bd mov sp, r7
8004a18: bd80 pop {r7, pc}
08004a1a <SDMMC_CmdGoIdleState>:
* @brief Send the Go Idle State command and check the response.
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
{
8004a1a: b580 push {r7, lr}
8004a1c: b088 sub sp, #32
8004a1e: af00 add r7, sp, #0
8004a20: 6078 str r0, [r7, #4]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
sdmmc_cmdinit.Argument = 0U;
8004a22: 2300 movs r3, #0
8004a24: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
8004a26: 2300 movs r3, #0
8004a28: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_NO;
8004a2a: 2300 movs r3, #0
8004a2c: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004a2e: 2300 movs r3, #0
8004a30: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004a32: f44f 6380 mov.w r3, #1024 ; 0x400
8004a36: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004a38: f107 0308 add.w r3, r7, #8
8004a3c: 4619 mov r1, r3
8004a3e: 6878 ldr r0, [r7, #4]
8004a40: f7ff fe85 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdError(SDIOx);
8004a44: 6878 ldr r0, [r7, #4]
8004a46: f000 f92d bl 8004ca4 <SDMMC_GetCmdError>
8004a4a: 61f8 str r0, [r7, #28]
return errorstate;
8004a4c: 69fb ldr r3, [r7, #28]
}
8004a4e: 4618 mov r0, r3
8004a50: 3720 adds r7, #32
8004a52: 46bd mov sp, r7
8004a54: bd80 pop {r7, pc}
08004a56 <SDMMC_CmdOperCond>:
* @brief Send the Operating Condition command and check the response.
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
{
8004a56: b580 push {r7, lr}
8004a58: b088 sub sp, #32
8004a5a: af00 add r7, sp, #0
8004a5c: 6078 str r0, [r7, #4]
/* Send CMD8 to verify SD card interface operating condition */
/* Argument: - [31:12]: Reserved (shall be set to '0')
- [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
- [7:0]: Check Pattern (recommended 0xAA) */
/* CMD Response: R7 */
sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN;
8004a5e: f44f 73d5 mov.w r3, #426 ; 0x1aa
8004a62: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
8004a64: 2308 movs r3, #8
8004a66: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004a68: 2340 movs r3, #64 ; 0x40
8004a6a: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004a6c: 2300 movs r3, #0
8004a6e: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004a70: f44f 6380 mov.w r3, #1024 ; 0x400
8004a74: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004a76: f107 0308 add.w r3, r7, #8
8004a7a: 4619 mov r1, r3
8004a7c: 6878 ldr r0, [r7, #4]
8004a7e: f7ff fe66 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp7(SDIOx);
8004a82: 6878 ldr r0, [r7, #4]
8004a84: f000 fb24 bl 80050d0 <SDMMC_GetCmdResp7>
8004a88: 61f8 str r0, [r7, #28]
return errorstate;
8004a8a: 69fb ldr r3, [r7, #28]
}
8004a8c: 4618 mov r0, r3
8004a8e: 3720 adds r7, #32
8004a90: 46bd mov sp, r7
8004a92: bd80 pop {r7, pc}
08004a94 <SDMMC_CmdAppCommand>:
* @param SDIOx: Pointer to SDIO register base
* @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
8004a94: b580 push {r7, lr}
8004a96: b088 sub sp, #32
8004a98: af00 add r7, sp, #0
8004a9a: 6078 str r0, [r7, #4]
8004a9c: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
sdmmc_cmdinit.Argument = (uint32_t)Argument;
8004a9e: 683b ldr r3, [r7, #0]
8004aa0: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
8004aa2: 2337 movs r3, #55 ; 0x37
8004aa4: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004aa6: 2340 movs r3, #64 ; 0x40
8004aa8: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004aaa: 2300 movs r3, #0
8004aac: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004aae: f44f 6380 mov.w r3, #1024 ; 0x400
8004ab2: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004ab4: f107 0308 add.w r3, r7, #8
8004ab8: 4619 mov r1, r3
8004aba: 6878 ldr r0, [r7, #4]
8004abc: f7ff fe47 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
/* If there is a HAL_ERROR, it is a MMC card, else
it is a SD card: SD card 2.0 (voltage range mismatch)
or SD card 1.x */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
8004ac0: f241 3288 movw r2, #5000 ; 0x1388
8004ac4: 2137 movs r1, #55 ; 0x37
8004ac6: 6878 ldr r0, [r7, #4]
8004ac8: f000 f918 bl 8004cfc <SDMMC_GetCmdResp1>
8004acc: 61f8 str r0, [r7, #28]
return errorstate;
8004ace: 69fb ldr r3, [r7, #28]
}
8004ad0: 4618 mov r0, r3
8004ad2: 3720 adds r7, #32
8004ad4: 46bd mov sp, r7
8004ad6: bd80 pop {r7, pc}
08004ad8 <SDMMC_CmdAppOperCommand>:
* @param SDIOx: Pointer to SDIO register base
* @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
8004ad8: b580 push {r7, lr}
8004ada: b088 sub sp, #32
8004adc: af00 add r7, sp, #0
8004ade: 6078 str r0, [r7, #4]
8004ae0: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument;
8004ae2: 683b ldr r3, [r7, #0]
8004ae4: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
8004ae8: f443 1380 orr.w r3, r3, #1048576 ; 0x100000
8004aec: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
8004aee: 2329 movs r3, #41 ; 0x29
8004af0: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004af2: 2340 movs r3, #64 ; 0x40
8004af4: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004af6: 2300 movs r3, #0
8004af8: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004afa: f44f 6380 mov.w r3, #1024 ; 0x400
8004afe: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004b00: f107 0308 add.w r3, r7, #8
8004b04: 4619 mov r1, r3
8004b06: 6878 ldr r0, [r7, #4]
8004b08: f7ff fe21 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp3(SDIOx);
8004b0c: 6878 ldr r0, [r7, #4]
8004b0e: f000 fa2b bl 8004f68 <SDMMC_GetCmdResp3>
8004b12: 61f8 str r0, [r7, #28]
return errorstate;
8004b14: 69fb ldr r3, [r7, #28]
}
8004b16: 4618 mov r0, r3
8004b18: 3720 adds r7, #32
8004b1a: 46bd mov sp, r7
8004b1c: bd80 pop {r7, pc}
08004b1e <SDMMC_CmdBusWidth>:
* @param SDIOx: Pointer to SDIO register base
* @param BusWidth: BusWidth
* @retval HAL status
*/
uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
{
8004b1e: b580 push {r7, lr}
8004b20: b088 sub sp, #32
8004b22: af00 add r7, sp, #0
8004b24: 6078 str r0, [r7, #4]
8004b26: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
8004b28: 683b ldr r3, [r7, #0]
8004b2a: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
8004b2c: 2306 movs r3, #6
8004b2e: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004b30: 2340 movs r3, #64 ; 0x40
8004b32: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004b34: 2300 movs r3, #0
8004b36: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004b38: f44f 6380 mov.w r3, #1024 ; 0x400
8004b3c: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004b3e: f107 0308 add.w r3, r7, #8
8004b42: 4619 mov r1, r3
8004b44: 6878 ldr r0, [r7, #4]
8004b46: f7ff fe02 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
8004b4a: f241 3288 movw r2, #5000 ; 0x1388
8004b4e: 2106 movs r1, #6
8004b50: 6878 ldr r0, [r7, #4]
8004b52: f000 f8d3 bl 8004cfc <SDMMC_GetCmdResp1>
8004b56: 61f8 str r0, [r7, #28]
return errorstate;
8004b58: 69fb ldr r3, [r7, #28]
}
8004b5a: 4618 mov r0, r3
8004b5c: 3720 adds r7, #32
8004b5e: 46bd mov sp, r7
8004b60: bd80 pop {r7, pc}
08004b62 <SDMMC_CmdSendSCR>:
* @brief Send the Send SCR command and check the response.
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
{
8004b62: b580 push {r7, lr}
8004b64: b088 sub sp, #32
8004b66: af00 add r7, sp, #0
8004b68: 6078 str r0, [r7, #4]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Send CMD51 SD_APP_SEND_SCR */
sdmmc_cmdinit.Argument = 0U;
8004b6a: 2300 movs r3, #0
8004b6c: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
8004b6e: 2333 movs r3, #51 ; 0x33
8004b70: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004b72: 2340 movs r3, #64 ; 0x40
8004b74: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004b76: 2300 movs r3, #0
8004b78: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004b7a: f44f 6380 mov.w r3, #1024 ; 0x400
8004b7e: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004b80: f107 0308 add.w r3, r7, #8
8004b84: 4619 mov r1, r3
8004b86: 6878 ldr r0, [r7, #4]
8004b88: f7ff fde1 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
8004b8c: f241 3288 movw r2, #5000 ; 0x1388
8004b90: 2133 movs r1, #51 ; 0x33
8004b92: 6878 ldr r0, [r7, #4]
8004b94: f000 f8b2 bl 8004cfc <SDMMC_GetCmdResp1>
8004b98: 61f8 str r0, [r7, #28]
return errorstate;
8004b9a: 69fb ldr r3, [r7, #28]
}
8004b9c: 4618 mov r0, r3
8004b9e: 3720 adds r7, #32
8004ba0: 46bd mov sp, r7
8004ba2: bd80 pop {r7, pc}
08004ba4 <SDMMC_CmdSendCID>:
* @brief Send the Send CID command and check the response.
* @param SDIOx: Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
{
8004ba4: b580 push {r7, lr}
8004ba6: b088 sub sp, #32
8004ba8: af00 add r7, sp, #0
8004baa: 6078 str r0, [r7, #4]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Send CMD2 ALL_SEND_CID */
sdmmc_cmdinit.Argument = 0U;
8004bac: 2300 movs r3, #0
8004bae: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
8004bb0: 2302 movs r3, #2
8004bb2: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
8004bb4: 23c0 movs r3, #192 ; 0xc0
8004bb6: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004bb8: 2300 movs r3, #0
8004bba: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004bbc: f44f 6380 mov.w r3, #1024 ; 0x400
8004bc0: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004bc2: f107 0308 add.w r3, r7, #8
8004bc6: 4619 mov r1, r3
8004bc8: 6878 ldr r0, [r7, #4]
8004bca: f7ff fdc0 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDIOx);
8004bce: 6878 ldr r0, [r7, #4]
8004bd0: f000 f982 bl 8004ed8 <SDMMC_GetCmdResp2>
8004bd4: 61f8 str r0, [r7, #28]
return errorstate;
8004bd6: 69fb ldr r3, [r7, #28]
}
8004bd8: 4618 mov r0, r3
8004bda: 3720 adds r7, #32
8004bdc: 46bd mov sp, r7
8004bde: bd80 pop {r7, pc}
08004be0 <SDMMC_CmdSendCSD>:
* @param SDIOx: Pointer to SDIO register base
* @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
8004be0: b580 push {r7, lr}
8004be2: b088 sub sp, #32
8004be4: af00 add r7, sp, #0
8004be6: 6078 str r0, [r7, #4]
8004be8: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Send CMD9 SEND_CSD */
sdmmc_cmdinit.Argument = Argument;
8004bea: 683b ldr r3, [r7, #0]
8004bec: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
8004bee: 2309 movs r3, #9
8004bf0: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
8004bf2: 23c0 movs r3, #192 ; 0xc0
8004bf4: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004bf6: 2300 movs r3, #0
8004bf8: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004bfa: f44f 6380 mov.w r3, #1024 ; 0x400
8004bfe: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004c00: f107 0308 add.w r3, r7, #8
8004c04: 4619 mov r1, r3
8004c06: 6878 ldr r0, [r7, #4]
8004c08: f7ff fda1 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp2(SDIOx);
8004c0c: 6878 ldr r0, [r7, #4]
8004c0e: f000 f963 bl 8004ed8 <SDMMC_GetCmdResp2>
8004c12: 61f8 str r0, [r7, #28]
return errorstate;
8004c14: 69fb ldr r3, [r7, #28]
}
8004c16: 4618 mov r0, r3
8004c18: 3720 adds r7, #32
8004c1a: 46bd mov sp, r7
8004c1c: bd80 pop {r7, pc}
08004c1e <SDMMC_CmdSetRelAdd>:
* @param SDIOx: Pointer to SDIO register base
* @param pRCA: Card RCA
* @retval HAL status
*/
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
{
8004c1e: b580 push {r7, lr}
8004c20: b088 sub sp, #32
8004c22: af00 add r7, sp, #0
8004c24: 6078 str r0, [r7, #4]
8004c26: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
/* Send CMD3 SD_CMD_SET_REL_ADDR */
sdmmc_cmdinit.Argument = 0U;
8004c28: 2300 movs r3, #0
8004c2a: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
8004c2c: 2303 movs r3, #3
8004c2e: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004c30: 2340 movs r3, #64 ; 0x40
8004c32: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004c34: 2300 movs r3, #0
8004c36: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004c38: f44f 6380 mov.w r3, #1024 ; 0x400
8004c3c: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004c3e: f107 0308 add.w r3, r7, #8
8004c42: 4619 mov r1, r3
8004c44: 6878 ldr r0, [r7, #4]
8004c46: f7ff fd82 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
8004c4a: 683a ldr r2, [r7, #0]
8004c4c: 2103 movs r1, #3
8004c4e: 6878 ldr r0, [r7, #4]
8004c50: f000 f9c8 bl 8004fe4 <SDMMC_GetCmdResp6>
8004c54: 61f8 str r0, [r7, #28]
return errorstate;
8004c56: 69fb ldr r3, [r7, #28]
}
8004c58: 4618 mov r0, r3
8004c5a: 3720 adds r7, #32
8004c5c: 46bd mov sp, r7
8004c5e: bd80 pop {r7, pc}
08004c60 <SDMMC_CmdSendStatus>:
* @param SDIOx: Pointer to SDIO register base
* @param Argument: Command Argument
* @retval HAL status
*/
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
{
8004c60: b580 push {r7, lr}
8004c62: b088 sub sp, #32
8004c64: af00 add r7, sp, #0
8004c66: 6078 str r0, [r7, #4]
8004c68: 6039 str r1, [r7, #0]
SDIO_CmdInitTypeDef sdmmc_cmdinit;
uint32_t errorstate;
sdmmc_cmdinit.Argument = Argument;
8004c6a: 683b ldr r3, [r7, #0]
8004c6c: 60bb str r3, [r7, #8]
sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
8004c6e: 230d movs r3, #13
8004c70: 60fb str r3, [r7, #12]
sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
8004c72: 2340 movs r3, #64 ; 0x40
8004c74: 613b str r3, [r7, #16]
sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
8004c76: 2300 movs r3, #0
8004c78: 617b str r3, [r7, #20]
sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
8004c7a: f44f 6380 mov.w r3, #1024 ; 0x400
8004c7e: 61bb str r3, [r7, #24]
(void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
8004c80: f107 0308 add.w r3, r7, #8
8004c84: 4619 mov r1, r3
8004c86: 6878 ldr r0, [r7, #4]
8004c88: f7ff fd61 bl 800474e <SDIO_SendCommand>
/* Check for error conditions */
errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
8004c8c: f241 3288 movw r2, #5000 ; 0x1388
8004c90: 210d movs r1, #13
8004c92: 6878 ldr r0, [r7, #4]
8004c94: f000 f832 bl 8004cfc <SDMMC_GetCmdResp1>
8004c98: 61f8 str r0, [r7, #28]
return errorstate;
8004c9a: 69fb ldr r3, [r7, #28]
}
8004c9c: 4618 mov r0, r3
8004c9e: 3720 adds r7, #32
8004ca0: 46bd mov sp, r7
8004ca2: bd80 pop {r7, pc}
08004ca4 <SDMMC_GetCmdError>:
* @brief Checks for error conditions for CMD0.
* @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
{
8004ca4: b480 push {r7}
8004ca6: b085 sub sp, #20
8004ca8: af00 add r7, sp, #0
8004caa: 6078 str r0, [r7, #4]
/* 8 is the number of required instructions cycles for the below loop statement.
The SDIO_CMDTIMEOUT is expressed in ms */
uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
8004cac: 4b11 ldr r3, [pc, #68] ; (8004cf4 <SDMMC_GetCmdError+0x50>)
8004cae: 681b ldr r3, [r3, #0]
8004cb0: 4a11 ldr r2, [pc, #68] ; (8004cf8 <SDMMC_GetCmdError+0x54>)
8004cb2: fba2 2303 umull r2, r3, r2, r3
8004cb6: 0a5b lsrs r3, r3, #9
8004cb8: f241 3288 movw r2, #5000 ; 0x1388
8004cbc: fb02 f303 mul.w r3, r2, r3
8004cc0: 60fb str r3, [r7, #12]
do
{
if (count-- == 0U)
8004cc2: 68fb ldr r3, [r7, #12]
8004cc4: 1e5a subs r2, r3, #1
8004cc6: 60fa str r2, [r7, #12]
8004cc8: 2b00 cmp r3, #0
8004cca: d102 bne.n 8004cd2 <SDMMC_GetCmdError+0x2e>
{
return SDMMC_ERROR_TIMEOUT;
8004ccc: f04f 4300 mov.w r3, #2147483648 ; 0x80000000
8004cd0: e009 b.n 8004ce6 <SDMMC_GetCmdError+0x42>
}
}while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
8004cd2: 687b ldr r3, [r7, #4]
8004cd4: 6b5b ldr r3, [r3, #52] ; 0x34
8004cd6: f003 0380 and.w r3, r3, #128 ; 0x80
8004cda: 2b00 cmp r3, #0
8004cdc: d0f1 beq.n 8004cc2 <SDMMC_GetCmdError+0x1e>
/* Clear all the static flags */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
8004cde: 687b ldr r3, [r7, #4]
8004ce0: 22c5 movs r2, #197 ; 0xc5
8004ce2: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_NONE;
8004ce4: 2300 movs r3, #0
}
8004ce6: 4618 mov r0, r3
8004ce8: 3714 adds r7, #20
8004cea: 46bd mov sp, r7
8004cec: f85d 7b04 ldr.w r7, [sp], #4
8004cf0: 4770 bx lr
8004cf2: bf00 nop
8004cf4: 20000000 .word 0x20000000
8004cf8: 10624dd3 .word 0x10624dd3
08004cfc <SDMMC_GetCmdResp1>:
* @param hsd: SD handle
* @param SD_CMD: The sent command index
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
{
8004cfc: b580 push {r7, lr}
8004cfe: b088 sub sp, #32
8004d00: af00 add r7, sp, #0
8004d02: 60f8 str r0, [r7, #12]
8004d04: 460b mov r3, r1
8004d06: 607a str r2, [r7, #4]
8004d08: 72fb strb r3, [r7, #11]
uint32_t response_r1;
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
8004d0a: 4b70 ldr r3, [pc, #448] ; (8004ecc <SDMMC_GetCmdResp1+0x1d0>)
8004d0c: 681b ldr r3, [r3, #0]
8004d0e: 4a70 ldr r2, [pc, #448] ; (8004ed0 <SDMMC_GetCmdResp1+0x1d4>)
8004d10: fba2 2303 umull r2, r3, r2, r3
8004d14: 0a5a lsrs r2, r3, #9
8004d16: 687b ldr r3, [r7, #4]
8004d18: fb02 f303 mul.w r3, r2, r3
8004d1c: 61fb str r3, [r7, #28]
do
{
if (count-- == 0U)
8004d1e: 69fb ldr r3, [r7, #28]
8004d20: 1e5a subs r2, r3, #1
8004d22: 61fa str r2, [r7, #28]
8004d24: 2b00 cmp r3, #0
8004d26: d102 bne.n 8004d2e <SDMMC_GetCmdResp1+0x32>
{
return SDMMC_ERROR_TIMEOUT;
8004d28: f04f 4300 mov.w r3, #2147483648 ; 0x80000000
8004d2c: e0c9 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
sta_reg = SDIOx->STA;
8004d2e: 68fb ldr r3, [r7, #12]
8004d30: 6b5b ldr r3, [r3, #52] ; 0x34
8004d32: 61bb str r3, [r7, #24]
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8004d34: 69bb ldr r3, [r7, #24]
8004d36: f003 0345 and.w r3, r3, #69 ; 0x45
((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
8004d3a: 2b00 cmp r3, #0
8004d3c: d0ef beq.n 8004d1e <SDMMC_GetCmdResp1+0x22>
8004d3e: 69bb ldr r3, [r7, #24]
8004d40: f403 6300 and.w r3, r3, #2048 ; 0x800
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8004d44: 2b00 cmp r3, #0
8004d46: d1ea bne.n 8004d1e <SDMMC_GetCmdResp1+0x22>
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
8004d48: 68fb ldr r3, [r7, #12]
8004d4a: 6b5b ldr r3, [r3, #52] ; 0x34
8004d4c: f003 0304 and.w r3, r3, #4
8004d50: 2b00 cmp r3, #0
8004d52: d004 beq.n 8004d5e <SDMMC_GetCmdResp1+0x62>
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
8004d54: 68fb ldr r3, [r7, #12]
8004d56: 2204 movs r2, #4
8004d58: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
8004d5a: 2304 movs r3, #4
8004d5c: e0b1 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
8004d5e: 68fb ldr r3, [r7, #12]
8004d60: 6b5b ldr r3, [r3, #52] ; 0x34
8004d62: f003 0301 and.w r3, r3, #1
8004d66: 2b00 cmp r3, #0
8004d68: d004 beq.n 8004d74 <SDMMC_GetCmdResp1+0x78>
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
8004d6a: 68fb ldr r3, [r7, #12]
8004d6c: 2201 movs r2, #1
8004d6e: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_CRC_FAIL;
8004d70: 2301 movs r3, #1
8004d72: e0a6 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
{
/* Nothing to do */
}
/* Clear all the static flags */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
8004d74: 68fb ldr r3, [r7, #12]
8004d76: 22c5 movs r2, #197 ; 0xc5
8004d78: 639a str r2, [r3, #56] ; 0x38
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
8004d7a: 68f8 ldr r0, [r7, #12]
8004d7c: f7ff fd11 bl 80047a2 <SDIO_GetCommandResponse>
8004d80: 4603 mov r3, r0
8004d82: 461a mov r2, r3
8004d84: 7afb ldrb r3, [r7, #11]
8004d86: 4293 cmp r3, r2
8004d88: d001 beq.n 8004d8e <SDMMC_GetCmdResp1+0x92>
{
return SDMMC_ERROR_CMD_CRC_FAIL;
8004d8a: 2301 movs r3, #1
8004d8c: e099 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
/* We have received response, retrieve it for analysis */
response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
8004d8e: 2100 movs r1, #0
8004d90: 68f8 ldr r0, [r7, #12]
8004d92: f7ff fd13 bl 80047bc <SDIO_GetResponse>
8004d96: 6178 str r0, [r7, #20]
if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
8004d98: 697a ldr r2, [r7, #20]
8004d9a: 4b4e ldr r3, [pc, #312] ; (8004ed4 <SDMMC_GetCmdResp1+0x1d8>)
8004d9c: 4013 ands r3, r2
8004d9e: 2b00 cmp r3, #0
8004da0: d101 bne.n 8004da6 <SDMMC_GetCmdResp1+0xaa>
{
return SDMMC_ERROR_NONE;
8004da2: 2300 movs r3, #0
8004da4: e08d b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
8004da6: 697b ldr r3, [r7, #20]
8004da8: 2b00 cmp r3, #0
8004daa: da02 bge.n 8004db2 <SDMMC_GetCmdResp1+0xb6>
{
return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
8004dac: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8004db0: e087 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
8004db2: 697b ldr r3, [r7, #20]
8004db4: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000
8004db8: 2b00 cmp r3, #0
8004dba: d001 beq.n 8004dc0 <SDMMC_GetCmdResp1+0xc4>
{
return SDMMC_ERROR_ADDR_MISALIGNED;
8004dbc: 2340 movs r3, #64 ; 0x40
8004dbe: e080 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
8004dc0: 697b ldr r3, [r7, #20]
8004dc2: f003 5300 and.w r3, r3, #536870912 ; 0x20000000
8004dc6: 2b00 cmp r3, #0
8004dc8: d001 beq.n 8004dce <SDMMC_GetCmdResp1+0xd2>
{
return SDMMC_ERROR_BLOCK_LEN_ERR;
8004dca: 2380 movs r3, #128 ; 0x80
8004dcc: e079 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
8004dce: 697b ldr r3, [r7, #20]
8004dd0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8004dd4: 2b00 cmp r3, #0
8004dd6: d002 beq.n 8004dde <SDMMC_GetCmdResp1+0xe2>
{
return SDMMC_ERROR_ERASE_SEQ_ERR;
8004dd8: f44f 7380 mov.w r3, #256 ; 0x100
8004ddc: e071 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
8004dde: 697b ldr r3, [r7, #20]
8004de0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
8004de4: 2b00 cmp r3, #0
8004de6: d002 beq.n 8004dee <SDMMC_GetCmdResp1+0xf2>
{
return SDMMC_ERROR_BAD_ERASE_PARAM;
8004de8: f44f 7300 mov.w r3, #512 ; 0x200
8004dec: e069 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
8004dee: 697b ldr r3, [r7, #20]
8004df0: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8004df4: 2b00 cmp r3, #0
8004df6: d002 beq.n 8004dfe <SDMMC_GetCmdResp1+0x102>
{
return SDMMC_ERROR_WRITE_PROT_VIOLATION;
8004df8: f44f 6380 mov.w r3, #1024 ; 0x400
8004dfc: e061 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
8004dfe: 697b ldr r3, [r7, #20]
8004e00: f003 7380 and.w r3, r3, #16777216 ; 0x1000000
8004e04: 2b00 cmp r3, #0
8004e06: d002 beq.n 8004e0e <SDMMC_GetCmdResp1+0x112>
{
return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
8004e08: f44f 6300 mov.w r3, #2048 ; 0x800
8004e0c: e059 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
8004e0e: 697b ldr r3, [r7, #20]
8004e10: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8004e14: 2b00 cmp r3, #0
8004e16: d002 beq.n 8004e1e <SDMMC_GetCmdResp1+0x122>
{
return SDMMC_ERROR_COM_CRC_FAILED;
8004e18: f44f 5380 mov.w r3, #4096 ; 0x1000
8004e1c: e051 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
8004e1e: 697b ldr r3, [r7, #20]
8004e20: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8004e24: 2b00 cmp r3, #0
8004e26: d002 beq.n 8004e2e <SDMMC_GetCmdResp1+0x132>
{
return SDMMC_ERROR_ILLEGAL_CMD;
8004e28: f44f 5300 mov.w r3, #8192 ; 0x2000
8004e2c: e049 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
8004e2e: 697b ldr r3, [r7, #20]
8004e30: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8004e34: 2b00 cmp r3, #0
8004e36: d002 beq.n 8004e3e <SDMMC_GetCmdResp1+0x142>
{
return SDMMC_ERROR_CARD_ECC_FAILED;
8004e38: f44f 4380 mov.w r3, #16384 ; 0x4000
8004e3c: e041 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
8004e3e: 697b ldr r3, [r7, #20]
8004e40: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8004e44: 2b00 cmp r3, #0
8004e46: d002 beq.n 8004e4e <SDMMC_GetCmdResp1+0x152>
{
return SDMMC_ERROR_CC_ERR;
8004e48: f44f 4300 mov.w r3, #32768 ; 0x8000
8004e4c: e039 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
8004e4e: 697b ldr r3, [r7, #20]
8004e50: f403 2380 and.w r3, r3, #262144 ; 0x40000
8004e54: 2b00 cmp r3, #0
8004e56: d002 beq.n 8004e5e <SDMMC_GetCmdResp1+0x162>
{
return SDMMC_ERROR_STREAM_READ_UNDERRUN;
8004e58: f44f 3300 mov.w r3, #131072 ; 0x20000
8004e5c: e031 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
8004e5e: 697b ldr r3, [r7, #20]
8004e60: f403 3300 and.w r3, r3, #131072 ; 0x20000
8004e64: 2b00 cmp r3, #0
8004e66: d002 beq.n 8004e6e <SDMMC_GetCmdResp1+0x172>
{
return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
8004e68: f44f 2380 mov.w r3, #262144 ; 0x40000
8004e6c: e029 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
8004e6e: 697b ldr r3, [r7, #20]
8004e70: f403 3380 and.w r3, r3, #65536 ; 0x10000
8004e74: 2b00 cmp r3, #0
8004e76: d002 beq.n 8004e7e <SDMMC_GetCmdResp1+0x182>
{
return SDMMC_ERROR_CID_CSD_OVERWRITE;
8004e78: f44f 2300 mov.w r3, #524288 ; 0x80000
8004e7c: e021 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
8004e7e: 697b ldr r3, [r7, #20]
8004e80: f403 4300 and.w r3, r3, #32768 ; 0x8000
8004e84: 2b00 cmp r3, #0
8004e86: d002 beq.n 8004e8e <SDMMC_GetCmdResp1+0x192>
{
return SDMMC_ERROR_WP_ERASE_SKIP;
8004e88: f44f 1380 mov.w r3, #1048576 ; 0x100000
8004e8c: e019 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
8004e8e: 697b ldr r3, [r7, #20]
8004e90: f403 4380 and.w r3, r3, #16384 ; 0x4000
8004e94: 2b00 cmp r3, #0
8004e96: d002 beq.n 8004e9e <SDMMC_GetCmdResp1+0x1a2>
{
return SDMMC_ERROR_CARD_ECC_DISABLED;
8004e98: f44f 1300 mov.w r3, #2097152 ; 0x200000
8004e9c: e011 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
8004e9e: 697b ldr r3, [r7, #20]
8004ea0: f403 5300 and.w r3, r3, #8192 ; 0x2000
8004ea4: 2b00 cmp r3, #0
8004ea6: d002 beq.n 8004eae <SDMMC_GetCmdResp1+0x1b2>
{
return SDMMC_ERROR_ERASE_RESET;
8004ea8: f44f 0380 mov.w r3, #4194304 ; 0x400000
8004eac: e009 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
8004eae: 697b ldr r3, [r7, #20]
8004eb0: f003 0308 and.w r3, r3, #8
8004eb4: 2b00 cmp r3, #0
8004eb6: d002 beq.n 8004ebe <SDMMC_GetCmdResp1+0x1c2>
{
return SDMMC_ERROR_AKE_SEQ_ERR;
8004eb8: f44f 0300 mov.w r3, #8388608 ; 0x800000
8004ebc: e001 b.n 8004ec2 <SDMMC_GetCmdResp1+0x1c6>
}
else
{
return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
8004ebe: f44f 3380 mov.w r3, #65536 ; 0x10000
}
}
8004ec2: 4618 mov r0, r3
8004ec4: 3720 adds r7, #32
8004ec6: 46bd mov sp, r7
8004ec8: bd80 pop {r7, pc}
8004eca: bf00 nop
8004ecc: 20000000 .word 0x20000000
8004ed0: 10624dd3 .word 0x10624dd3
8004ed4: fdffe008 .word 0xfdffe008
08004ed8 <SDMMC_GetCmdResp2>:
* @brief Checks for error conditions for R2 (CID or CSD) response.
* @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
{
8004ed8: b480 push {r7}
8004eda: b085 sub sp, #20
8004edc: af00 add r7, sp, #0
8004ede: 6078 str r0, [r7, #4]
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDIO_CMDTIMEOUT is expressed in ms */
uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
8004ee0: 4b1f ldr r3, [pc, #124] ; (8004f60 <SDMMC_GetCmdResp2+0x88>)
8004ee2: 681b ldr r3, [r3, #0]
8004ee4: 4a1f ldr r2, [pc, #124] ; (8004f64 <SDMMC_GetCmdResp2+0x8c>)
8004ee6: fba2 2303 umull r2, r3, r2, r3
8004eea: 0a5b lsrs r3, r3, #9
8004eec: f241 3288 movw r2, #5000 ; 0x1388
8004ef0: fb02 f303 mul.w r3, r2, r3
8004ef4: 60fb str r3, [r7, #12]
do
{
if (count-- == 0U)
8004ef6: 68fb ldr r3, [r7, #12]
8004ef8: 1e5a subs r2, r3, #1
8004efa: 60fa str r2, [r7, #12]
8004efc: 2b00 cmp r3, #0
8004efe: d102 bne.n 8004f06 <SDMMC_GetCmdResp2+0x2e>
{
return SDMMC_ERROR_TIMEOUT;
8004f00: f04f 4300 mov.w r3, #2147483648 ; 0x80000000
8004f04: e026 b.n 8004f54 <SDMMC_GetCmdResp2+0x7c>
}
sta_reg = SDIOx->STA;
8004f06: 687b ldr r3, [r7, #4]
8004f08: 6b5b ldr r3, [r3, #52] ; 0x34
8004f0a: 60bb str r3, [r7, #8]
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8004f0c: 68bb ldr r3, [r7, #8]
8004f0e: f003 0345 and.w r3, r3, #69 ; 0x45
((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
8004f12: 2b00 cmp r3, #0
8004f14: d0ef beq.n 8004ef6 <SDMMC_GetCmdResp2+0x1e>
8004f16: 68bb ldr r3, [r7, #8]
8004f18: f403 6300 and.w r3, r3, #2048 ; 0x800
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8004f1c: 2b00 cmp r3, #0
8004f1e: d1ea bne.n 8004ef6 <SDMMC_GetCmdResp2+0x1e>
if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
8004f20: 687b ldr r3, [r7, #4]
8004f22: 6b5b ldr r3, [r3, #52] ; 0x34
8004f24: f003 0304 and.w r3, r3, #4
8004f28: 2b00 cmp r3, #0
8004f2a: d004 beq.n 8004f36 <SDMMC_GetCmdResp2+0x5e>
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
8004f2c: 687b ldr r3, [r7, #4]
8004f2e: 2204 movs r2, #4
8004f30: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
8004f32: 2304 movs r3, #4
8004f34: e00e b.n 8004f54 <SDMMC_GetCmdResp2+0x7c>
}
else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
8004f36: 687b ldr r3, [r7, #4]
8004f38: 6b5b ldr r3, [r3, #52] ; 0x34
8004f3a: f003 0301 and.w r3, r3, #1
8004f3e: 2b00 cmp r3, #0
8004f40: d004 beq.n 8004f4c <SDMMC_GetCmdResp2+0x74>
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
8004f42: 687b ldr r3, [r7, #4]
8004f44: 2201 movs r2, #1
8004f46: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_CRC_FAIL;
8004f48: 2301 movs r3, #1
8004f4a: e003 b.n 8004f54 <SDMMC_GetCmdResp2+0x7c>
}
else
{
/* No error flag set */
/* Clear all the static flags */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
8004f4c: 687b ldr r3, [r7, #4]
8004f4e: 22c5 movs r2, #197 ; 0xc5
8004f50: 639a str r2, [r3, #56] ; 0x38
}
return SDMMC_ERROR_NONE;
8004f52: 2300 movs r3, #0
}
8004f54: 4618 mov r0, r3
8004f56: 3714 adds r7, #20
8004f58: 46bd mov sp, r7
8004f5a: f85d 7b04 ldr.w r7, [sp], #4
8004f5e: 4770 bx lr
8004f60: 20000000 .word 0x20000000
8004f64: 10624dd3 .word 0x10624dd3
08004f68 <SDMMC_GetCmdResp3>:
* @brief Checks for error conditions for R3 (OCR) response.
* @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
{
8004f68: b480 push {r7}
8004f6a: b085 sub sp, #20
8004f6c: af00 add r7, sp, #0
8004f6e: 6078 str r0, [r7, #4]
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDIO_CMDTIMEOUT is expressed in ms */
uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
8004f70: 4b1a ldr r3, [pc, #104] ; (8004fdc <SDMMC_GetCmdResp3+0x74>)
8004f72: 681b ldr r3, [r3, #0]
8004f74: 4a1a ldr r2, [pc, #104] ; (8004fe0 <SDMMC_GetCmdResp3+0x78>)
8004f76: fba2 2303 umull r2, r3, r2, r3
8004f7a: 0a5b lsrs r3, r3, #9
8004f7c: f241 3288 movw r2, #5000 ; 0x1388
8004f80: fb02 f303 mul.w r3, r2, r3
8004f84: 60fb str r3, [r7, #12]
do
{
if (count-- == 0U)
8004f86: 68fb ldr r3, [r7, #12]
8004f88: 1e5a subs r2, r3, #1
8004f8a: 60fa str r2, [r7, #12]
8004f8c: 2b00 cmp r3, #0
8004f8e: d102 bne.n 8004f96 <SDMMC_GetCmdResp3+0x2e>
{
return SDMMC_ERROR_TIMEOUT;
8004f90: f04f 4300 mov.w r3, #2147483648 ; 0x80000000
8004f94: e01b b.n 8004fce <SDMMC_GetCmdResp3+0x66>
}
sta_reg = SDIOx->STA;
8004f96: 687b ldr r3, [r7, #4]
8004f98: 6b5b ldr r3, [r3, #52] ; 0x34
8004f9a: 60bb str r3, [r7, #8]
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8004f9c: 68bb ldr r3, [r7, #8]
8004f9e: f003 0345 and.w r3, r3, #69 ; 0x45
((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
8004fa2: 2b00 cmp r3, #0
8004fa4: d0ef beq.n 8004f86 <SDMMC_GetCmdResp3+0x1e>
8004fa6: 68bb ldr r3, [r7, #8]
8004fa8: f403 6300 and.w r3, r3, #2048 ; 0x800
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8004fac: 2b00 cmp r3, #0
8004fae: d1ea bne.n 8004f86 <SDMMC_GetCmdResp3+0x1e>
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
8004fb0: 687b ldr r3, [r7, #4]
8004fb2: 6b5b ldr r3, [r3, #52] ; 0x34
8004fb4: f003 0304 and.w r3, r3, #4
8004fb8: 2b00 cmp r3, #0
8004fba: d004 beq.n 8004fc6 <SDMMC_GetCmdResp3+0x5e>
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
8004fbc: 687b ldr r3, [r7, #4]
8004fbe: 2204 movs r2, #4
8004fc0: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
8004fc2: 2304 movs r3, #4
8004fc4: e003 b.n 8004fce <SDMMC_GetCmdResp3+0x66>
}
else
{
/* Clear all the static flags */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
8004fc6: 687b ldr r3, [r7, #4]
8004fc8: 22c5 movs r2, #197 ; 0xc5
8004fca: 639a str r2, [r3, #56] ; 0x38
}
return SDMMC_ERROR_NONE;
8004fcc: 2300 movs r3, #0
}
8004fce: 4618 mov r0, r3
8004fd0: 3714 adds r7, #20
8004fd2: 46bd mov sp, r7
8004fd4: f85d 7b04 ldr.w r7, [sp], #4
8004fd8: 4770 bx lr
8004fda: bf00 nop
8004fdc: 20000000 .word 0x20000000
8004fe0: 10624dd3 .word 0x10624dd3
08004fe4 <SDMMC_GetCmdResp6>:
* @param pRCA: Pointer to the variable that will contain the SD card relative
* address RCA
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
{
8004fe4: b580 push {r7, lr}
8004fe6: b088 sub sp, #32
8004fe8: af00 add r7, sp, #0
8004fea: 60f8 str r0, [r7, #12]
8004fec: 460b mov r3, r1
8004fee: 607a str r2, [r7, #4]
8004ff0: 72fb strb r3, [r7, #11]
uint32_t response_r1;
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDIO_CMDTIMEOUT is expressed in ms */
uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
8004ff2: 4b35 ldr r3, [pc, #212] ; (80050c8 <SDMMC_GetCmdResp6+0xe4>)
8004ff4: 681b ldr r3, [r3, #0]
8004ff6: 4a35 ldr r2, [pc, #212] ; (80050cc <SDMMC_GetCmdResp6+0xe8>)
8004ff8: fba2 2303 umull r2, r3, r2, r3
8004ffc: 0a5b lsrs r3, r3, #9
8004ffe: f241 3288 movw r2, #5000 ; 0x1388
8005002: fb02 f303 mul.w r3, r2, r3
8005006: 61fb str r3, [r7, #28]
do
{
if (count-- == 0U)
8005008: 69fb ldr r3, [r7, #28]
800500a: 1e5a subs r2, r3, #1
800500c: 61fa str r2, [r7, #28]
800500e: 2b00 cmp r3, #0
8005010: d102 bne.n 8005018 <SDMMC_GetCmdResp6+0x34>
{
return SDMMC_ERROR_TIMEOUT;
8005012: f04f 4300 mov.w r3, #2147483648 ; 0x80000000
8005016: e052 b.n 80050be <SDMMC_GetCmdResp6+0xda>
}
sta_reg = SDIOx->STA;
8005018: 68fb ldr r3, [r7, #12]
800501a: 6b5b ldr r3, [r3, #52] ; 0x34
800501c: 61bb str r3, [r7, #24]
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
800501e: 69bb ldr r3, [r7, #24]
8005020: f003 0345 and.w r3, r3, #69 ; 0x45
((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
8005024: 2b00 cmp r3, #0
8005026: d0ef beq.n 8005008 <SDMMC_GetCmdResp6+0x24>
8005028: 69bb ldr r3, [r7, #24]
800502a: f403 6300 and.w r3, r3, #2048 ; 0x800
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
800502e: 2b00 cmp r3, #0
8005030: d1ea bne.n 8005008 <SDMMC_GetCmdResp6+0x24>
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
8005032: 68fb ldr r3, [r7, #12]
8005034: 6b5b ldr r3, [r3, #52] ; 0x34
8005036: f003 0304 and.w r3, r3, #4
800503a: 2b00 cmp r3, #0
800503c: d004 beq.n 8005048 <SDMMC_GetCmdResp6+0x64>
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
800503e: 68fb ldr r3, [r7, #12]
8005040: 2204 movs r2, #4
8005042: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
8005044: 2304 movs r3, #4
8005046: e03a b.n 80050be <SDMMC_GetCmdResp6+0xda>
}
else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
8005048: 68fb ldr r3, [r7, #12]
800504a: 6b5b ldr r3, [r3, #52] ; 0x34
800504c: f003 0301 and.w r3, r3, #1
8005050: 2b00 cmp r3, #0
8005052: d004 beq.n 800505e <SDMMC_GetCmdResp6+0x7a>
{
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
8005054: 68fb ldr r3, [r7, #12]
8005056: 2201 movs r2, #1
8005058: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_CRC_FAIL;
800505a: 2301 movs r3, #1
800505c: e02f b.n 80050be <SDMMC_GetCmdResp6+0xda>
{
/* Nothing to do */
}
/* Check response received is of desired command */
if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
800505e: 68f8 ldr r0, [r7, #12]
8005060: f7ff fb9f bl 80047a2 <SDIO_GetCommandResponse>
8005064: 4603 mov r3, r0
8005066: 461a mov r2, r3
8005068: 7afb ldrb r3, [r7, #11]
800506a: 4293 cmp r3, r2
800506c: d001 beq.n 8005072 <SDMMC_GetCmdResp6+0x8e>
{
return SDMMC_ERROR_CMD_CRC_FAIL;
800506e: 2301 movs r3, #1
8005070: e025 b.n 80050be <SDMMC_GetCmdResp6+0xda>
}
/* Clear all the static flags */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS);
8005072: 68fb ldr r3, [r7, #12]
8005074: 22c5 movs r2, #197 ; 0xc5
8005076: 639a str r2, [r3, #56] ; 0x38
/* We have received response, retrieve it. */
response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
8005078: 2100 movs r1, #0
800507a: 68f8 ldr r0, [r7, #12]
800507c: f7ff fb9e bl 80047bc <SDIO_GetResponse>
8005080: 6178 str r0, [r7, #20]
if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
8005082: 697b ldr r3, [r7, #20]
8005084: f403 4360 and.w r3, r3, #57344 ; 0xe000
8005088: 2b00 cmp r3, #0
800508a: d106 bne.n 800509a <SDMMC_GetCmdResp6+0xb6>
{
*pRCA = (uint16_t) (response_r1 >> 16);
800508c: 697b ldr r3, [r7, #20]
800508e: 0c1b lsrs r3, r3, #16
8005090: b29a uxth r2, r3
8005092: 687b ldr r3, [r7, #4]
8005094: 801a strh r2, [r3, #0]
return SDMMC_ERROR_NONE;
8005096: 2300 movs r3, #0
8005098: e011 b.n 80050be <SDMMC_GetCmdResp6+0xda>
}
else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
800509a: 697b ldr r3, [r7, #20]
800509c: f403 4380 and.w r3, r3, #16384 ; 0x4000
80050a0: 2b00 cmp r3, #0
80050a2: d002 beq.n 80050aa <SDMMC_GetCmdResp6+0xc6>
{
return SDMMC_ERROR_ILLEGAL_CMD;
80050a4: f44f 5300 mov.w r3, #8192 ; 0x2000
80050a8: e009 b.n 80050be <SDMMC_GetCmdResp6+0xda>
}
else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
80050aa: 697b ldr r3, [r7, #20]
80050ac: f403 4300 and.w r3, r3, #32768 ; 0x8000
80050b0: 2b00 cmp r3, #0
80050b2: d002 beq.n 80050ba <SDMMC_GetCmdResp6+0xd6>
{
return SDMMC_ERROR_COM_CRC_FAILED;
80050b4: f44f 5380 mov.w r3, #4096 ; 0x1000
80050b8: e001 b.n 80050be <SDMMC_GetCmdResp6+0xda>
}
else
{
return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
80050ba: f44f 3380 mov.w r3, #65536 ; 0x10000
}
}
80050be: 4618 mov r0, r3
80050c0: 3720 adds r7, #32
80050c2: 46bd mov sp, r7
80050c4: bd80 pop {r7, pc}
80050c6: bf00 nop
80050c8: 20000000 .word 0x20000000
80050cc: 10624dd3 .word 0x10624dd3
080050d0 <SDMMC_GetCmdResp7>:
* @brief Checks for error conditions for R7 response.
* @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
{
80050d0: b480 push {r7}
80050d2: b085 sub sp, #20
80050d4: af00 add r7, sp, #0
80050d6: 6078 str r0, [r7, #4]
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDIO_CMDTIMEOUT is expressed in ms */
uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
80050d8: 4b22 ldr r3, [pc, #136] ; (8005164 <SDMMC_GetCmdResp7+0x94>)
80050da: 681b ldr r3, [r3, #0]
80050dc: 4a22 ldr r2, [pc, #136] ; (8005168 <SDMMC_GetCmdResp7+0x98>)
80050de: fba2 2303 umull r2, r3, r2, r3
80050e2: 0a5b lsrs r3, r3, #9
80050e4: f241 3288 movw r2, #5000 ; 0x1388
80050e8: fb02 f303 mul.w r3, r2, r3
80050ec: 60fb str r3, [r7, #12]
do
{
if (count-- == 0U)
80050ee: 68fb ldr r3, [r7, #12]
80050f0: 1e5a subs r2, r3, #1
80050f2: 60fa str r2, [r7, #12]
80050f4: 2b00 cmp r3, #0
80050f6: d102 bne.n 80050fe <SDMMC_GetCmdResp7+0x2e>
{
return SDMMC_ERROR_TIMEOUT;
80050f8: f04f 4300 mov.w r3, #2147483648 ; 0x80000000
80050fc: e02c b.n 8005158 <SDMMC_GetCmdResp7+0x88>
}
sta_reg = SDIOx->STA;
80050fe: 687b ldr r3, [r7, #4]
8005100: 6b5b ldr r3, [r3, #52] ; 0x34
8005102: 60bb str r3, [r7, #8]
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8005104: 68bb ldr r3, [r7, #8]
8005106: f003 0345 and.w r3, r3, #69 ; 0x45
((sta_reg & SDIO_FLAG_CMDACT) != 0U ));
800510a: 2b00 cmp r3, #0
800510c: d0ef beq.n 80050ee <SDMMC_GetCmdResp7+0x1e>
800510e: 68bb ldr r3, [r7, #8]
8005110: f403 6300 and.w r3, r3, #2048 ; 0x800
}while(((sta_reg & (SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) == 0U) ||
8005114: 2b00 cmp r3, #0
8005116: d1ea bne.n 80050ee <SDMMC_GetCmdResp7+0x1e>
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
8005118: 687b ldr r3, [r7, #4]
800511a: 6b5b ldr r3, [r3, #52] ; 0x34
800511c: f003 0304 and.w r3, r3, #4
8005120: 2b00 cmp r3, #0
8005122: d004 beq.n 800512e <SDMMC_GetCmdResp7+0x5e>
{
/* Card is SD V2.0 compliant */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
8005124: 687b ldr r3, [r7, #4]
8005126: 2204 movs r2, #4
8005128: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_RSP_TIMEOUT;
800512a: 2304 movs r3, #4
800512c: e014 b.n 8005158 <SDMMC_GetCmdResp7+0x88>
}
else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
800512e: 687b ldr r3, [r7, #4]
8005130: 6b5b ldr r3, [r3, #52] ; 0x34
8005132: f003 0301 and.w r3, r3, #1
8005136: 2b00 cmp r3, #0
8005138: d004 beq.n 8005144 <SDMMC_GetCmdResp7+0x74>
{
/* Card is SD V2.0 compliant */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
800513a: 687b ldr r3, [r7, #4]
800513c: 2201 movs r2, #1
800513e: 639a str r2, [r3, #56] ; 0x38
return SDMMC_ERROR_CMD_CRC_FAIL;
8005140: 2301 movs r3, #1
8005142: e009 b.n 8005158 <SDMMC_GetCmdResp7+0x88>
else
{
/* Nothing to do */
}
if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
8005144: 687b ldr r3, [r7, #4]
8005146: 6b5b ldr r3, [r3, #52] ; 0x34
8005148: f003 0340 and.w r3, r3, #64 ; 0x40
800514c: 2b00 cmp r3, #0
800514e: d002 beq.n 8005156 <SDMMC_GetCmdResp7+0x86>
{
/* Card is SD V2.0 compliant */
__SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
8005150: 687b ldr r3, [r7, #4]
8005152: 2240 movs r2, #64 ; 0x40
8005154: 639a str r2, [r3, #56] ; 0x38
}
return SDMMC_ERROR_NONE;
8005156: 2300 movs r3, #0
}
8005158: 4618 mov r0, r3
800515a: 3714 adds r7, #20
800515c: 46bd mov sp, r7
800515e: f85d 7b04 ldr.w r7, [sp], #4
8005162: 4770 bx lr
8005164: 20000000 .word 0x20000000
8005168: 10624dd3 .word 0x10624dd3
0800516c <USB_CoreInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
800516c: b084 sub sp, #16
800516e: b580 push {r7, lr}
8005170: b084 sub sp, #16
8005172: af00 add r7, sp, #0
8005174: 6078 str r0, [r7, #4]
8005176: f107 001c add.w r0, r7, #28
800517a: e880 000e stmia.w r0, {r1, r2, r3}
HAL_StatusTypeDef ret;
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
800517e: 6b3b ldr r3, [r7, #48] ; 0x30
8005180: 2b01 cmp r3, #1
8005182: d122 bne.n 80051ca <USB_CoreInit+0x5e>
{
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
8005184: 687b ldr r3, [r7, #4]
8005186: 6b9b ldr r3, [r3, #56] ; 0x38
8005188: f423 3280 bic.w r2, r3, #65536 ; 0x10000
800518c: 687b ldr r3, [r7, #4]
800518e: 639a str r2, [r3, #56] ; 0x38
/* Init The ULPI Interface */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
8005190: 687b ldr r3, [r7, #4]
8005192: 68db ldr r3, [r3, #12]
8005194: f423 0384 bic.w r3, r3, #4325376 ; 0x420000
8005198: f023 0340 bic.w r3, r3, #64 ; 0x40
800519c: 687a ldr r2, [r7, #4]
800519e: 60d3 str r3, [r2, #12]
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
80051a0: 687b ldr r3, [r7, #4]
80051a2: 68db ldr r3, [r3, #12]
80051a4: f423 1240 bic.w r2, r3, #3145728 ; 0x300000
80051a8: 687b ldr r3, [r7, #4]
80051aa: 60da str r2, [r3, #12]
if (cfg.use_external_vbus == 1U)
80051ac: 6cfb ldr r3, [r7, #76] ; 0x4c
80051ae: 2b01 cmp r3, #1
80051b0: d105 bne.n 80051be <USB_CoreInit+0x52>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
80051b2: 687b ldr r3, [r7, #4]
80051b4: 68db ldr r3, [r3, #12]
80051b6: f443 1280 orr.w r2, r3, #1048576 ; 0x100000
80051ba: 687b ldr r3, [r7, #4]
80051bc: 60da str r2, [r3, #12]
}
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
80051be: 6878 ldr r0, [r7, #4]
80051c0: f000 f8b8 bl 8005334 <USB_CoreReset>
80051c4: 4603 mov r3, r0
80051c6: 73fb strb r3, [r7, #15]
80051c8: e01a b.n 8005200 <USB_CoreInit+0x94>
}
else /* FS interface (embedded Phy) */
{
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
80051ca: 687b ldr r3, [r7, #4]
80051cc: 68db ldr r3, [r3, #12]
80051ce: f043 0240 orr.w r2, r3, #64 ; 0x40
80051d2: 687b ldr r3, [r7, #4]
80051d4: 60da str r2, [r3, #12]
/* Reset after a PHY select */
ret = USB_CoreReset(USBx);
80051d6: 6878 ldr r0, [r7, #4]
80051d8: f000 f8ac bl 8005334 <USB_CoreReset>
80051dc: 4603 mov r3, r0
80051de: 73fb strb r3, [r7, #15]
if (cfg.battery_charging_enable == 0U)
80051e0: 6c3b ldr r3, [r7, #64] ; 0x40
80051e2: 2b00 cmp r3, #0
80051e4: d106 bne.n 80051f4 <USB_CoreInit+0x88>
{
/* Activate the USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
80051e6: 687b ldr r3, [r7, #4]
80051e8: 6b9b ldr r3, [r3, #56] ; 0x38
80051ea: f443 3280 orr.w r2, r3, #65536 ; 0x10000
80051ee: 687b ldr r3, [r7, #4]
80051f0: 639a str r2, [r3, #56] ; 0x38
80051f2: e005 b.n 8005200 <USB_CoreInit+0x94>
}
else
{
/* Deactivate the USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
80051f4: 687b ldr r3, [r7, #4]
80051f6: 6b9b ldr r3, [r3, #56] ; 0x38
80051f8: f423 3280 bic.w r2, r3, #65536 ; 0x10000
80051fc: 687b ldr r3, [r7, #4]
80051fe: 639a str r2, [r3, #56] ; 0x38
}
}
if (cfg.dma_enable == 1U)
8005200: 6abb ldr r3, [r7, #40] ; 0x28
8005202: 2b01 cmp r3, #1
8005204: d10b bne.n 800521e <USB_CoreInit+0xb2>
{
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
8005206: 687b ldr r3, [r7, #4]
8005208: 689b ldr r3, [r3, #8]
800520a: f043 0206 orr.w r2, r3, #6
800520e: 687b ldr r3, [r7, #4]
8005210: 609a str r2, [r3, #8]
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
8005212: 687b ldr r3, [r7, #4]
8005214: 689b ldr r3, [r3, #8]
8005216: f043 0220 orr.w r2, r3, #32
800521a: 687b ldr r3, [r7, #4]
800521c: 609a str r2, [r3, #8]
}
return ret;
800521e: 7bfb ldrb r3, [r7, #15]
}
8005220: 4618 mov r0, r3
8005222: 3710 adds r7, #16
8005224: 46bd mov sp, r7
8005226: e8bd 4080 ldmia.w sp!, {r7, lr}
800522a: b004 add sp, #16
800522c: 4770 bx lr
0800522e <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
800522e: b480 push {r7}
8005230: b083 sub sp, #12
8005232: af00 add r7, sp, #0
8005234: 6078 str r0, [r7, #4]
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
8005236: 687b ldr r3, [r7, #4]
8005238: 689b ldr r3, [r3, #8]
800523a: f023 0201 bic.w r2, r3, #1
800523e: 687b ldr r3, [r7, #4]
8005240: 609a str r2, [r3, #8]
return HAL_OK;
8005242: 2300 movs r3, #0
}
8005244: 4618 mov r0, r3
8005246: 370c adds r7, #12
8005248: 46bd mov sp, r7
800524a: f85d 7b04 ldr.w r7, [sp], #4
800524e: 4770 bx lr
08005250 <USB_SetCurrentMode>:
* @arg USB_DEVICE_MODE Peripheral mode
* @arg USB_HOST_MODE Host mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
{
8005250: b580 push {r7, lr}
8005252: b082 sub sp, #8
8005254: af00 add r7, sp, #0
8005256: 6078 str r0, [r7, #4]
8005258: 460b mov r3, r1
800525a: 70fb strb r3, [r7, #3]
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
800525c: 687b ldr r3, [r7, #4]
800525e: 68db ldr r3, [r3, #12]
8005260: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000
8005264: 687b ldr r3, [r7, #4]
8005266: 60da str r2, [r3, #12]
if (mode == USB_HOST_MODE)
8005268: 78fb ldrb r3, [r7, #3]
800526a: 2b01 cmp r3, #1
800526c: d106 bne.n 800527c <USB_SetCurrentMode+0x2c>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
800526e: 687b ldr r3, [r7, #4]
8005270: 68db ldr r3, [r3, #12]
8005272: f043 5200 orr.w r2, r3, #536870912 ; 0x20000000
8005276: 687b ldr r3, [r7, #4]
8005278: 60da str r2, [r3, #12]
800527a: e00b b.n 8005294 <USB_SetCurrentMode+0x44>
}
else if (mode == USB_DEVICE_MODE)
800527c: 78fb ldrb r3, [r7, #3]
800527e: 2b00 cmp r3, #0
8005280: d106 bne.n 8005290 <USB_SetCurrentMode+0x40>
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
8005282: 687b ldr r3, [r7, #4]
8005284: 68db ldr r3, [r3, #12]
8005286: f043 4280 orr.w r2, r3, #1073741824 ; 0x40000000
800528a: 687b ldr r3, [r7, #4]
800528c: 60da str r2, [r3, #12]
800528e: e001 b.n 8005294 <USB_SetCurrentMode+0x44>
}
else
{
return HAL_ERROR;
8005290: 2301 movs r3, #1
8005292: e003 b.n 800529c <USB_SetCurrentMode+0x4c>
}
HAL_Delay(50U);
8005294: 2032 movs r0, #50 ; 0x32
8005296: f7fb fe73 bl 8000f80 <HAL_Delay>
return HAL_OK;
800529a: 2300 movs r3, #0
}
800529c: 4618 mov r0, r3
800529e: 3708 adds r7, #8
80052a0: 46bd mov sp, r7
80052a2: bd80 pop {r7, pc}
080052a4 <USB_FlushTxFifo>:
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
80052a4: b480 push {r7}
80052a6: b085 sub sp, #20
80052a8: af00 add r7, sp, #0
80052aa: 6078 str r0, [r7, #4]
80052ac: 6039 str r1, [r7, #0]
uint32_t count = 0U;
80052ae: 2300 movs r3, #0
80052b0: 60fb str r3, [r7, #12]
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
80052b2: 683b ldr r3, [r7, #0]
80052b4: 019b lsls r3, r3, #6
80052b6: f043 0220 orr.w r2, r3, #32
80052ba: 687b ldr r3, [r7, #4]
80052bc: 611a str r2, [r3, #16]
do
{
if (++count > 200000U)
80052be: 68fb ldr r3, [r7, #12]
80052c0: 3301 adds r3, #1
80052c2: 60fb str r3, [r7, #12]
80052c4: 68fb ldr r3, [r7, #12]
80052c6: 4a09 ldr r2, [pc, #36] ; (80052ec <USB_FlushTxFifo+0x48>)
80052c8: 4293 cmp r3, r2
80052ca: d901 bls.n 80052d0 <USB_FlushTxFifo+0x2c>
{
return HAL_TIMEOUT;
80052cc: 2303 movs r3, #3
80052ce: e006 b.n 80052de <USB_FlushTxFifo+0x3a>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
80052d0: 687b ldr r3, [r7, #4]
80052d2: 691b ldr r3, [r3, #16]
80052d4: f003 0320 and.w r3, r3, #32
80052d8: 2b20 cmp r3, #32
80052da: d0f0 beq.n 80052be <USB_FlushTxFifo+0x1a>
return HAL_OK;
80052dc: 2300 movs r3, #0
}
80052de: 4618 mov r0, r3
80052e0: 3714 adds r7, #20
80052e2: 46bd mov sp, r7
80052e4: f85d 7b04 ldr.w r7, [sp], #4
80052e8: 4770 bx lr
80052ea: bf00 nop
80052ec: 00030d40 .word 0x00030d40
080052f0 <USB_FlushRxFifo>:
* @brief USB_FlushRxFifo : Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
80052f0: b480 push {r7}
80052f2: b085 sub sp, #20
80052f4: af00 add r7, sp, #0
80052f6: 6078 str r0, [r7, #4]
uint32_t count = 0;
80052f8: 2300 movs r3, #0
80052fa: 60fb str r3, [r7, #12]
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
80052fc: 687b ldr r3, [r7, #4]
80052fe: 2210 movs r2, #16
8005300: 611a str r2, [r3, #16]
do
{
if (++count > 200000U)
8005302: 68fb ldr r3, [r7, #12]
8005304: 3301 adds r3, #1
8005306: 60fb str r3, [r7, #12]
8005308: 68fb ldr r3, [r7, #12]
800530a: 4a09 ldr r2, [pc, #36] ; (8005330 <USB_FlushRxFifo+0x40>)
800530c: 4293 cmp r3, r2
800530e: d901 bls.n 8005314 <USB_FlushRxFifo+0x24>
{
return HAL_TIMEOUT;
8005310: 2303 movs r3, #3
8005312: e006 b.n 8005322 <USB_FlushRxFifo+0x32>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
8005314: 687b ldr r3, [r7, #4]
8005316: 691b ldr r3, [r3, #16]
8005318: f003 0310 and.w r3, r3, #16
800531c: 2b10 cmp r3, #16
800531e: d0f0 beq.n 8005302 <USB_FlushRxFifo+0x12>
return HAL_OK;
8005320: 2300 movs r3, #0
}
8005322: 4618 mov r0, r3
8005324: 3714 adds r7, #20
8005326: 46bd mov sp, r7
8005328: f85d 7b04 ldr.w r7, [sp], #4
800532c: 4770 bx lr
800532e: bf00 nop
8005330: 00030d40 .word 0x00030d40
08005334 <USB_CoreReset>:
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
8005334: b480 push {r7}
8005336: b085 sub sp, #20
8005338: af00 add r7, sp, #0
800533a: 6078 str r0, [r7, #4]
uint32_t count = 0U;
800533c: 2300 movs r3, #0
800533e: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
if (++count > 200000U)
8005340: 68fb ldr r3, [r7, #12]
8005342: 3301 adds r3, #1
8005344: 60fb str r3, [r7, #12]
8005346: 68fb ldr r3, [r7, #12]
8005348: 4a13 ldr r2, [pc, #76] ; (8005398 <USB_CoreReset+0x64>)
800534a: 4293 cmp r3, r2
800534c: d901 bls.n 8005352 <USB_CoreReset+0x1e>
{
return HAL_TIMEOUT;
800534e: 2303 movs r3, #3
8005350: e01b b.n 800538a <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8005352: 687b ldr r3, [r7, #4]
8005354: 691b ldr r3, [r3, #16]
8005356: 2b00 cmp r3, #0
8005358: daf2 bge.n 8005340 <USB_CoreReset+0xc>
/* Core Soft Reset */
count = 0U;
800535a: 2300 movs r3, #0
800535c: 60fb str r3, [r7, #12]
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
800535e: 687b ldr r3, [r7, #4]
8005360: 691b ldr r3, [r3, #16]
8005362: f043 0201 orr.w r2, r3, #1
8005366: 687b ldr r3, [r7, #4]
8005368: 611a str r2, [r3, #16]
do
{
if (++count > 200000U)
800536a: 68fb ldr r3, [r7, #12]
800536c: 3301 adds r3, #1
800536e: 60fb str r3, [r7, #12]
8005370: 68fb ldr r3, [r7, #12]
8005372: 4a09 ldr r2, [pc, #36] ; (8005398 <USB_CoreReset+0x64>)
8005374: 4293 cmp r3, r2
8005376: d901 bls.n 800537c <USB_CoreReset+0x48>
{
return HAL_TIMEOUT;
8005378: 2303 movs r3, #3
800537a: e006 b.n 800538a <USB_CoreReset+0x56>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
800537c: 687b ldr r3, [r7, #4]
800537e: 691b ldr r3, [r3, #16]
8005380: f003 0301 and.w r3, r3, #1
8005384: 2b01 cmp r3, #1
8005386: d0f0 beq.n 800536a <USB_CoreReset+0x36>
return HAL_OK;
8005388: 2300 movs r3, #0
}
800538a: 4618 mov r0, r3
800538c: 3714 adds r7, #20
800538e: 46bd mov sp, r7
8005390: f85d 7b04 ldr.w r7, [sp], #4
8005394: 4770 bx lr
8005396: bf00 nop
8005398: 00030d40 .word 0x00030d40
0800539c <USB_HostInit>:
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
800539c: b084 sub sp, #16
800539e: b580 push {r7, lr}
80053a0: b084 sub sp, #16
80053a2: af00 add r7, sp, #0
80053a4: 6078 str r0, [r7, #4]
80053a6: f107 001c add.w r0, r7, #28
80053aa: e880 000e stmia.w r0, {r1, r2, r3}
uint32_t USBx_BASE = (uint32_t)USBx;
80053ae: 687b ldr r3, [r7, #4]
80053b0: 60bb str r3, [r7, #8]
uint32_t i;
/* Restart the Phy Clock */
USBx_PCGCCTL = 0U;
80053b2: 68bb ldr r3, [r7, #8]
80053b4: f503 6360 add.w r3, r3, #3584 ; 0xe00
80053b8: 461a mov r2, r3
80053ba: 2300 movs r3, #0
80053bc: 6013 str r3, [r2, #0]
#else
/*
* Disable HW VBUS sensing. VBUS is internally considered to be always
* at VBUS-Valid level (5V).
*/
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
80053be: 687b ldr r3, [r7, #4]
80053c0: 6b9b ldr r3, [r3, #56] ; 0x38
80053c2: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
80053c6: 687b ldr r3, [r7, #4]
80053c8: 639a str r2, [r3, #56] ; 0x38
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
80053ca: 687b ldr r3, [r7, #4]
80053cc: 6b9b ldr r3, [r3, #56] ; 0x38
80053ce: f423 2200 bic.w r2, r3, #524288 ; 0x80000
80053d2: 687b ldr r3, [r7, #4]
80053d4: 639a str r2, [r3, #56] ; 0x38
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
80053d6: 687b ldr r3, [r7, #4]
80053d8: 6b9b ldr r3, [r3, #56] ; 0x38
80053da: f423 2280 bic.w r2, r3, #262144 ; 0x40000
80053de: 687b ldr r3, [r7, #4]
80053e0: 639a str r2, [r3, #56] ; 0x38
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Disable Battery chargin detector */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
if ((USBx->CID & (0x1U << 8)) != 0U)
80053e2: 687b ldr r3, [r7, #4]
80053e4: 6bdb ldr r3, [r3, #60] ; 0x3c
80053e6: f403 7380 and.w r3, r3, #256 ; 0x100
80053ea: 2b00 cmp r3, #0
80053ec: d018 beq.n 8005420 <USB_HostInit+0x84>
{
if (cfg.speed == USBH_FSLS_SPEED)
80053ee: 6a7b ldr r3, [r7, #36] ; 0x24
80053f0: 2b01 cmp r3, #1
80053f2: d10a bne.n 800540a <USB_HostInit+0x6e>
{
/* Force Device Enumeration to FS/LS mode only */
USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
80053f4: 68bb ldr r3, [r7, #8]
80053f6: f503 6380 add.w r3, r3, #1024 ; 0x400
80053fa: 681b ldr r3, [r3, #0]
80053fc: 68ba ldr r2, [r7, #8]
80053fe: f502 6280 add.w r2, r2, #1024 ; 0x400
8005402: f043 0304 orr.w r3, r3, #4
8005406: 6013 str r3, [r2, #0]
8005408: e014 b.n 8005434 <USB_HostInit+0x98>
}
else
{
/* Set default Max speed support */
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
800540a: 68bb ldr r3, [r7, #8]
800540c: f503 6380 add.w r3, r3, #1024 ; 0x400
8005410: 681b ldr r3, [r3, #0]
8005412: 68ba ldr r2, [r7, #8]
8005414: f502 6280 add.w r2, r2, #1024 ; 0x400
8005418: f023 0304 bic.w r3, r3, #4
800541c: 6013 str r3, [r2, #0]
800541e: e009 b.n 8005434 <USB_HostInit+0x98>
}
}
else
{
/* Set default Max speed support */
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
8005420: 68bb ldr r3, [r7, #8]
8005422: f503 6380 add.w r3, r3, #1024 ; 0x400
8005426: 681b ldr r3, [r3, #0]
8005428: 68ba ldr r2, [r7, #8]
800542a: f502 6280 add.w r2, r2, #1024 ; 0x400
800542e: f023 0304 bic.w r3, r3, #4
8005432: 6013 str r3, [r2, #0]
}
/* Make sure the FIFOs are flushed. */
(void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
8005434: 2110 movs r1, #16
8005436: 6878 ldr r0, [r7, #4]
8005438: f7ff ff34 bl 80052a4 <USB_FlushTxFifo>
(void)USB_FlushRxFifo(USBx);
800543c: 6878 ldr r0, [r7, #4]
800543e: f7ff ff57 bl 80052f0 <USB_FlushRxFifo>
/* Clear all pending HC Interrupts */
for (i = 0U; i < cfg.Host_channels; i++)
8005442: 2300 movs r3, #0
8005444: 60fb str r3, [r7, #12]
8005446: e015 b.n 8005474 <USB_HostInit+0xd8>
{
USBx_HC(i)->HCINT = 0xFFFFFFFFU;
8005448: 68fb ldr r3, [r7, #12]
800544a: 015a lsls r2, r3, #5
800544c: 68bb ldr r3, [r7, #8]
800544e: 4413 add r3, r2
8005450: f503 63a0 add.w r3, r3, #1280 ; 0x500
8005454: 461a mov r2, r3
8005456: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
800545a: 6093 str r3, [r2, #8]
USBx_HC(i)->HCINTMSK = 0U;
800545c: 68fb ldr r3, [r7, #12]
800545e: 015a lsls r2, r3, #5
8005460: 68bb ldr r3, [r7, #8]
8005462: 4413 add r3, r2
8005464: f503 63a0 add.w r3, r3, #1280 ; 0x500
8005468: 461a mov r2, r3
800546a: 2300 movs r3, #0
800546c: 60d3 str r3, [r2, #12]
for (i = 0U; i < cfg.Host_channels; i++)
800546e: 68fb ldr r3, [r7, #12]
8005470: 3301 adds r3, #1
8005472: 60fb str r3, [r7, #12]
8005474: 6a3b ldr r3, [r7, #32]
8005476: 68fa ldr r2, [r7, #12]
8005478: 429a cmp r2, r3
800547a: d3e5 bcc.n 8005448 <USB_HostInit+0xac>
}
/* Enable VBUS driving */
(void)USB_DriveVbus(USBx, 1U);
800547c: 2101 movs r1, #1
800547e: 6878 ldr r0, [r7, #4]
8005480: f000 f848 bl 8005514 <USB_DriveVbus>
HAL_Delay(200U);
8005484: 20c8 movs r0, #200 ; 0xc8
8005486: f7fb fd7b bl 8000f80 <HAL_Delay>
/* Disable all interrupts. */
USBx->GINTMSK = 0U;
800548a: 687b ldr r3, [r7, #4]
800548c: 2200 movs r2, #0
800548e: 619a str r2, [r3, #24]
/* Clear any pending interrupts */
USBx->GINTSTS = 0xFFFFFFFFU;
8005490: 687b ldr r3, [r7, #4]
8005492: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
8005496: 615a str r2, [r3, #20]
if ((USBx->CID & (0x1U << 8)) != 0U)
8005498: 687b ldr r3, [r7, #4]
800549a: 6bdb ldr r3, [r3, #60] ; 0x3c
800549c: f403 7380 and.w r3, r3, #256 ; 0x100
80054a0: 2b00 cmp r3, #0
80054a2: d00b beq.n 80054bc <USB_HostInit+0x120>
{
/* set Rx FIFO size */
USBx->GRXFSIZ = 0x200U;
80054a4: 687b ldr r3, [r7, #4]
80054a6: f44f 7200 mov.w r2, #512 ; 0x200
80054aa: 625a str r2, [r3, #36] ; 0x24
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
80054ac: 687b ldr r3, [r7, #4]
80054ae: 4a14 ldr r2, [pc, #80] ; (8005500 <USB_HostInit+0x164>)
80054b0: 629a str r2, [r3, #40] ; 0x28
USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
80054b2: 687b ldr r3, [r7, #4]
80054b4: 4a13 ldr r2, [pc, #76] ; (8005504 <USB_HostInit+0x168>)
80054b6: f8c3 2100 str.w r2, [r3, #256] ; 0x100
80054ba: e009 b.n 80054d0 <USB_HostInit+0x134>
}
else
{
/* set Rx FIFO size */
USBx->GRXFSIZ = 0x80U;
80054bc: 687b ldr r3, [r7, #4]
80054be: 2280 movs r2, #128 ; 0x80
80054c0: 625a str r2, [r3, #36] ; 0x24
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
80054c2: 687b ldr r3, [r7, #4]
80054c4: 4a10 ldr r2, [pc, #64] ; (8005508 <USB_HostInit+0x16c>)
80054c6: 629a str r2, [r3, #40] ; 0x28
USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
80054c8: 687b ldr r3, [r7, #4]
80054ca: 4a10 ldr r2, [pc, #64] ; (800550c <USB_HostInit+0x170>)
80054cc: f8c3 2100 str.w r2, [r3, #256] ; 0x100
}
/* Enable the common interrupts */
if (cfg.dma_enable == 0U)
80054d0: 6abb ldr r3, [r7, #40] ; 0x28
80054d2: 2b00 cmp r3, #0
80054d4: d105 bne.n 80054e2 <USB_HostInit+0x146>
{
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
80054d6: 687b ldr r3, [r7, #4]
80054d8: 699b ldr r3, [r3, #24]
80054da: f043 0210 orr.w r2, r3, #16
80054de: 687b ldr r3, [r7, #4]
80054e0: 619a str r2, [r3, #24]
}
/* Enable interrupts matching to the Host mode ONLY */
USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
80054e2: 687b ldr r3, [r7, #4]
80054e4: 699a ldr r2, [r3, #24]
80054e6: 4b0a ldr r3, [pc, #40] ; (8005510 <USB_HostInit+0x174>)
80054e8: 4313 orrs r3, r2
80054ea: 687a ldr r2, [r7, #4]
80054ec: 6193 str r3, [r2, #24]
USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
return HAL_OK;
80054ee: 2300 movs r3, #0
}
80054f0: 4618 mov r0, r3
80054f2: 3710 adds r7, #16
80054f4: 46bd mov sp, r7
80054f6: e8bd 4080 ldmia.w sp!, {r7, lr}
80054fa: b004 add sp, #16
80054fc: 4770 bx lr
80054fe: bf00 nop
8005500: 01000200 .word 0x01000200
8005504: 00e00300 .word 0x00e00300
8005508: 00600080 .word 0x00600080
800550c: 004000e0 .word 0x004000e0
8005510: a3200008 .word 0xa3200008
08005514 <USB_DriveVbus>:
* 0 : Deactivate VBUS
* 1 : Activate VBUS
* @retval HAL status
*/
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
8005514: b480 push {r7}
8005516: b085 sub sp, #20
8005518: af00 add r7, sp, #0
800551a: 6078 str r0, [r7, #4]
800551c: 460b mov r3, r1
800551e: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8005520: 687b ldr r3, [r7, #4]
8005522: 60fb str r3, [r7, #12]
__IO uint32_t hprt0 = 0U;
8005524: 2300 movs r3, #0
8005526: 60bb str r3, [r7, #8]
hprt0 = USBx_HPRT0;
8005528: 68fb ldr r3, [r7, #12]
800552a: f503 6388 add.w r3, r3, #1088 ; 0x440
800552e: 681b ldr r3, [r3, #0]
8005530: 60bb str r3, [r7, #8]
hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
8005532: 68bb ldr r3, [r7, #8]
8005534: f023 032e bic.w r3, r3, #46 ; 0x2e
8005538: 60bb str r3, [r7, #8]
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
800553a: 68bb ldr r3, [r7, #8]
800553c: f403 5380 and.w r3, r3, #4096 ; 0x1000
8005540: 2b00 cmp r3, #0
8005542: d109 bne.n 8005558 <USB_DriveVbus+0x44>
8005544: 78fb ldrb r3, [r7, #3]
8005546: 2b01 cmp r3, #1
8005548: d106 bne.n 8005558 <USB_DriveVbus+0x44>
{
USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
800554a: 68bb ldr r3, [r7, #8]
800554c: 68fa ldr r2, [r7, #12]
800554e: f502 6288 add.w r2, r2, #1088 ; 0x440
8005552: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8005556: 6013 str r3, [r2, #0]
}
if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
8005558: 68bb ldr r3, [r7, #8]
800555a: f403 5380 and.w r3, r3, #4096 ; 0x1000
800555e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8005562: d109 bne.n 8005578 <USB_DriveVbus+0x64>
8005564: 78fb ldrb r3, [r7, #3]
8005566: 2b00 cmp r3, #0
8005568: d106 bne.n 8005578 <USB_DriveVbus+0x64>
{
USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
800556a: 68bb ldr r3, [r7, #8]
800556c: 68fa ldr r2, [r7, #12]
800556e: f502 6288 add.w r2, r2, #1088 ; 0x440
8005572: f423 5380 bic.w r3, r3, #4096 ; 0x1000
8005576: 6013 str r3, [r2, #0]
}
return HAL_OK;
8005578: 2300 movs r3, #0
}
800557a: 4618 mov r0, r3
800557c: 3714 adds r7, #20
800557e: 46bd mov sp, r7
8005580: f85d 7b04 ldr.w r7, [sp], #4
8005584: 4770 bx lr
...
08005588 <MX_FATFS_Init>:
/* USER CODE BEGIN Variables */
/* USER CODE END Variables */
void MX_FATFS_Init(void)
{
8005588: b580 push {r7, lr}
800558a: af00 add r7, sp, #0
/*## FatFS: Link the SD driver ###########################*/
retSD = FATFS_LinkDriver(&SD_Driver, SDPath);
800558c: 4904 ldr r1, [pc, #16] ; (80055a0 <MX_FATFS_Init+0x18>)
800558e: 4805 ldr r0, [pc, #20] ; (80055a4 <MX_FATFS_Init+0x1c>)
8005590: f000 fa78 bl 8005a84 <FATFS_LinkDriver>
8005594: 4603 mov r3, r0
8005596: 461a mov r2, r3
8005598: 4b03 ldr r3, [pc, #12] ; (80055a8 <MX_FATFS_Init+0x20>)
800559a: 701a strb r2, [r3, #0]
/* USER CODE BEGIN Init */
/* additional user code for init */
/* USER CODE END Init */
}
800559c: bf00 nop
800559e: bd80 pop {r7, pc}
80055a0: 200004f8 .word 0x200004f8
80055a4: 08005b2c .word 0x08005b2c
80055a8: 200004f4 .word 0x200004f4
080055ac <BSP_SD_Init>:
/**
* @brief Initializes the SD card device.
* @retval SD status
*/
__weak uint8_t BSP_SD_Init(void)
{
80055ac: b580 push {r7, lr}
80055ae: b082 sub sp, #8
80055b0: af00 add r7, sp, #0
uint8_t sd_state = MSD_OK;
80055b2: 2300 movs r3, #0
80055b4: 71fb strb r3, [r7, #7]
/* Check if the SD card is plugged in the slot */
if (BSP_SD_IsDetected() != SD_PRESENT)
80055b6: f000 f87b bl 80056b0 <BSP_SD_IsDetected>
80055ba: 4603 mov r3, r0
80055bc: 2b01 cmp r3, #1
80055be: d001 beq.n 80055c4 <BSP_SD_Init+0x18>
{
return MSD_ERROR;
80055c0: 2301 movs r3, #1
80055c2: e012 b.n 80055ea <BSP_SD_Init+0x3e>
}
/* HAL SD initialization */
sd_state = HAL_SD_Init(&hsd);
80055c4: 480b ldr r0, [pc, #44] ; (80055f4 <BSP_SD_Init+0x48>)
80055c6: f7fd fd39 bl 800303c <HAL_SD_Init>
80055ca: 4603 mov r3, r0
80055cc: 71fb strb r3, [r7, #7]
/* Configure SD Bus width (4 bits mode selected) */
if (sd_state == MSD_OK)
80055ce: 79fb ldrb r3, [r7, #7]
80055d0: 2b00 cmp r3, #0
80055d2: d109 bne.n 80055e8 <BSP_SD_Init+0x3c>
{
/* Enable wide operation */
if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
80055d4: f44f 6100 mov.w r1, #2048 ; 0x800
80055d8: 4806 ldr r0, [pc, #24] ; (80055f4 <BSP_SD_Init+0x48>)
80055da: f7fe f97f bl 80038dc <HAL_SD_ConfigWideBusOperation>
80055de: 4603 mov r3, r0
80055e0: 2b00 cmp r3, #0
80055e2: d001 beq.n 80055e8 <BSP_SD_Init+0x3c>
{
sd_state = MSD_ERROR;
80055e4: 2301 movs r3, #1
80055e6: 71fb strb r3, [r7, #7]
}
}
return sd_state;
80055e8: 79fb ldrb r3, [r7, #7]
}
80055ea: 4618 mov r0, r3
80055ec: 3708 adds r7, #8
80055ee: 46bd mov sp, r7
80055f0: bd80 pop {r7, pc}
80055f2: bf00 nop
80055f4: 20000110 .word 0x20000110
080055f8 <BSP_SD_ReadBlocks_DMA>:
* @param ReadAddr: Address from where data is to be read
* @param NumOfBlocks: Number of SD blocks to read
* @retval SD status
*/
__weak uint8_t BSP_SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)
{
80055f8: b580 push {r7, lr}
80055fa: b086 sub sp, #24
80055fc: af00 add r7, sp, #0
80055fe: 60f8 str r0, [r7, #12]
8005600: 60b9 str r1, [r7, #8]
8005602: 607a str r2, [r7, #4]
uint8_t sd_state = MSD_OK;
8005604: 2300 movs r3, #0
8005606: 75fb strb r3, [r7, #23]
/* Read block(s) in DMA transfer mode */
if (HAL_SD_ReadBlocks_DMA(&hsd, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)
8005608: 687b ldr r3, [r7, #4]
800560a: 68ba ldr r2, [r7, #8]
800560c: 68f9 ldr r1, [r7, #12]
800560e: 4806 ldr r0, [pc, #24] ; (8005628 <BSP_SD_ReadBlocks_DMA+0x30>)
8005610: f7fd fdc2 bl 8003198 <HAL_SD_ReadBlocks_DMA>
8005614: 4603 mov r3, r0
8005616: 2b00 cmp r3, #0
8005618: d001 beq.n 800561e <BSP_SD_ReadBlocks_DMA+0x26>
{
sd_state = MSD_ERROR;
800561a: 2301 movs r3, #1
800561c: 75fb strb r3, [r7, #23]
}
return sd_state;
800561e: 7dfb ldrb r3, [r7, #23]
}
8005620: 4618 mov r0, r3
8005622: 3718 adds r7, #24
8005624: 46bd mov sp, r7
8005626: bd80 pop {r7, pc}
8005628: 20000110 .word 0x20000110
0800562c <BSP_SD_WriteBlocks_DMA>:
* @param WriteAddr: Address from where data is to be written
* @param NumOfBlocks: Number of SD blocks to write
* @retval SD status
*/
__weak uint8_t BSP_SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)
{
800562c: b580 push {r7, lr}
800562e: b086 sub sp, #24
8005630: af00 add r7, sp, #0
8005632: 60f8 str r0, [r7, #12]
8005634: 60b9 str r1, [r7, #8]
8005636: 607a str r2, [r7, #4]
uint8_t sd_state = MSD_OK;
8005638: 2300 movs r3, #0
800563a: 75fb strb r3, [r7, #23]
/* Write block(s) in DMA transfer mode */
if (HAL_SD_WriteBlocks_DMA(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)
800563c: 687b ldr r3, [r7, #4]
800563e: 68ba ldr r2, [r7, #8]
8005640: 68f9 ldr r1, [r7, #12]
8005642: 4806 ldr r0, [pc, #24] ; (800565c <BSP_SD_WriteBlocks_DMA+0x30>)
8005644: f7fd fe8a bl 800335c <HAL_SD_WriteBlocks_DMA>
8005648: 4603 mov r3, r0
800564a: 2b00 cmp r3, #0
800564c: d001 beq.n 8005652 <BSP_SD_WriteBlocks_DMA+0x26>
{
sd_state = MSD_ERROR;
800564e: 2301 movs r3, #1
8005650: 75fb strb r3, [r7, #23]
}
return sd_state;
8005652: 7dfb ldrb r3, [r7, #23]
}
8005654: 4618 mov r0, r3
8005656: 3718 adds r7, #24
8005658: 46bd mov sp, r7
800565a: bd80 pop {r7, pc}
800565c: 20000110 .word 0x20000110
08005660 <BSP_SD_GetCardState>:
* This value can be one of the following values:
* @arg SD_TRANSFER_OK: No data transfer is acting
* @arg SD_TRANSFER_BUSY: Data transfer is acting
*/
__weak uint8_t BSP_SD_GetCardState(void)
{
8005660: b580 push {r7, lr}
8005662: af00 add r7, sp, #0
return ((HAL_SD_GetCardState(&hsd) == HAL_SD_CARD_TRANSFER ) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);
8005664: 4805 ldr r0, [pc, #20] ; (800567c <BSP_SD_GetCardState+0x1c>)
8005666: f7fe f9d3 bl 8003a10 <HAL_SD_GetCardState>
800566a: 4603 mov r3, r0
800566c: 2b04 cmp r3, #4
800566e: bf14 ite ne
8005670: 2301 movne r3, #1
8005672: 2300 moveq r3, #0
8005674: b2db uxtb r3, r3
}
8005676: 4618 mov r0, r3
8005678: bd80 pop {r7, pc}
800567a: bf00 nop
800567c: 20000110 .word 0x20000110
08005680 <BSP_SD_GetCardInfo>:
* @brief Get SD information about specific SD card.
* @param CardInfo: Pointer to HAL_SD_CardInfoTypedef structure
* @retval None
*/
__weak void BSP_SD_GetCardInfo(HAL_SD_CardInfoTypeDef *CardInfo)
{
8005680: b580 push {r7, lr}
8005682: b082 sub sp, #8
8005684: af00 add r7, sp, #0
8005686: 6078 str r0, [r7, #4]
/* Get SD card Information */
HAL_SD_GetCardInfo(&hsd, CardInfo);
8005688: 6879 ldr r1, [r7, #4]
800568a: 4803 ldr r0, [pc, #12] ; (8005698 <BSP_SD_GetCardInfo+0x18>)
800568c: f7fe f8fa bl 8003884 <HAL_SD_GetCardInfo>
}
8005690: bf00 nop
8005692: 3708 adds r7, #8
8005694: 46bd mov sp, r7
8005696: bd80 pop {r7, pc}
8005698: 20000110 .word 0x20000110
0800569c <HAL_SD_RxCpltCallback>:
* @brief Rx Transfer completed callback
* @param hsd: SD handle
* @retval None
*/
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
{
800569c: b580 push {r7, lr}
800569e: b082 sub sp, #8
80056a0: af00 add r7, sp, #0
80056a2: 6078 str r0, [r7, #4]
BSP_SD_ReadCpltCallback();
80056a4: f000 f996 bl 80059d4 <BSP_SD_ReadCpltCallback>
}
80056a8: bf00 nop
80056aa: 3708 adds r7, #8
80056ac: 46bd mov sp, r7
80056ae: bd80 pop {r7, pc}
080056b0 <BSP_SD_IsDetected>:
* @brief Detects if SD card is correctly plugged in the memory slot or not.
* @param None
* @retval Returns if SD is detected or not
*/
__weak uint8_t BSP_SD_IsDetected(void)
{
80056b0: b580 push {r7, lr}
80056b2: b082 sub sp, #8
80056b4: af00 add r7, sp, #0
__IO uint8_t status = SD_PRESENT;
80056b6: 2301 movs r3, #1
80056b8: 71fb strb r3, [r7, #7]
if (BSP_PlatformIsDetected() == 0x0)
80056ba: f000 f80b bl 80056d4 <BSP_PlatformIsDetected>
80056be: 4603 mov r3, r0
80056c0: 2b00 cmp r3, #0
80056c2: d101 bne.n 80056c8 <BSP_SD_IsDetected+0x18>
{
status = SD_NOT_PRESENT;
80056c4: 2300 movs r3, #0
80056c6: 71fb strb r3, [r7, #7]
}
return status;
80056c8: 79fb ldrb r3, [r7, #7]
80056ca: b2db uxtb r3, r3
}
80056cc: 4618 mov r0, r3
80056ce: 3708 adds r7, #8
80056d0: 46bd mov sp, r7
80056d2: bd80 pop {r7, pc}
080056d4 <BSP_PlatformIsDetected>:
*
******************************************************************************
*/
#include "fatfs_platform.h"
uint8_t BSP_PlatformIsDetected(void) {
80056d4: b580 push {r7, lr}
80056d6: b082 sub sp, #8
80056d8: af00 add r7, sp, #0
uint8_t status = SD_PRESENT;
80056da: 2301 movs r3, #1
80056dc: 71fb strb r3, [r7, #7]
/* Check SD card detect pin */
if(HAL_GPIO_ReadPin(SD_DETECT_GPIO_PORT, SD_DETECT_PIN) != GPIO_PIN_RESET)
80056de: f44f 7100 mov.w r1, #512 ; 0x200
80056e2: 4806 ldr r0, [pc, #24] ; (80056fc <BSP_PlatformIsDetected+0x28>)
80056e4: f7fc f9de bl 8001aa4 <HAL_GPIO_ReadPin>
80056e8: 4603 mov r3, r0
80056ea: 2b00 cmp r3, #0
80056ec: d001 beq.n 80056f2 <BSP_PlatformIsDetected+0x1e>
{
status = SD_NOT_PRESENT;
80056ee: 2300 movs r3, #0
80056f0: 71fb strb r3, [r7, #7]
}
/* USER CODE BEGIN 1 */
/* user code can be inserted here */
/* USER CODE END 1 */
return status;
80056f2: 79fb ldrb r3, [r7, #7]
}
80056f4: 4618 mov r0, r3
80056f6: 3708 adds r7, #8
80056f8: 46bd mov sp, r7
80056fa: bd80 pop {r7, pc}
80056fc: 40020400 .word 0x40020400
08005700 <SD_CheckStatusWithTimeout>:
/* USER CODE END beforeFunctionSection */
/* Private functions ---------------------------------------------------------*/
static int SD_CheckStatusWithTimeout(uint32_t timeout)
{
8005700: b580 push {r7, lr}
8005702: b084 sub sp, #16
8005704: af00 add r7, sp, #0
8005706: 6078 str r0, [r7, #4]
uint32_t timer = HAL_GetTick();
8005708: f7fb fc2e bl 8000f68 <HAL_GetTick>
800570c: 60f8 str r0, [r7, #12]
/* block until SDIO IP is ready again or a timeout occur */
while(HAL_GetTick() - timer < timeout)
800570e: e006 b.n 800571e <SD_CheckStatusWithTimeout+0x1e>
{
if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
8005710: f7ff ffa6 bl 8005660 <BSP_SD_GetCardState>
8005714: 4603 mov r3, r0
8005716: 2b00 cmp r3, #0
8005718: d101 bne.n 800571e <SD_CheckStatusWithTimeout+0x1e>
{
return 0;
800571a: 2300 movs r3, #0
800571c: e009 b.n 8005732 <SD_CheckStatusWithTimeout+0x32>
while(HAL_GetTick() - timer < timeout)
800571e: f7fb fc23 bl 8000f68 <HAL_GetTick>
8005722: 4602 mov r2, r0
8005724: 68fb ldr r3, [r7, #12]
8005726: 1ad3 subs r3, r2, r3
8005728: 687a ldr r2, [r7, #4]
800572a: 429a cmp r2, r3
800572c: d8f0 bhi.n 8005710 <SD_CheckStatusWithTimeout+0x10>
}
}
return -1;
800572e: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff
}
8005732: 4618 mov r0, r3
8005734: 3710 adds r7, #16
8005736: 46bd mov sp, r7
8005738: bd80 pop {r7, pc}
...
0800573c <SD_CheckStatus>:
static DSTATUS SD_CheckStatus(BYTE lun)
{
800573c: b580 push {r7, lr}
800573e: b082 sub sp, #8
8005740: af00 add r7, sp, #0
8005742: 4603 mov r3, r0
8005744: 71fb strb r3, [r7, #7]
Stat = STA_NOINIT;
8005746: 4b0b ldr r3, [pc, #44] ; (8005774 <SD_CheckStatus+0x38>)
8005748: 2201 movs r2, #1
800574a: 701a strb r2, [r3, #0]
if(BSP_SD_GetCardState() == MSD_OK)
800574c: f7ff ff88 bl 8005660 <BSP_SD_GetCardState>
8005750: 4603 mov r3, r0
8005752: 2b00 cmp r3, #0
8005754: d107 bne.n 8005766 <SD_CheckStatus+0x2a>
{
Stat &= ~STA_NOINIT;
8005756: 4b07 ldr r3, [pc, #28] ; (8005774 <SD_CheckStatus+0x38>)
8005758: 781b ldrb r3, [r3, #0]
800575a: b2db uxtb r3, r3
800575c: f023 0301 bic.w r3, r3, #1
8005760: b2da uxtb r2, r3
8005762: 4b04 ldr r3, [pc, #16] ; (8005774 <SD_CheckStatus+0x38>)
8005764: 701a strb r2, [r3, #0]
}
return Stat;
8005766: 4b03 ldr r3, [pc, #12] ; (8005774 <SD_CheckStatus+0x38>)
8005768: 781b ldrb r3, [r3, #0]
800576a: b2db uxtb r3, r3
}
800576c: 4618 mov r0, r3
800576e: 3708 adds r7, #8
8005770: 46bd mov sp, r7
8005772: bd80 pop {r7, pc}
8005774: 20000009 .word 0x20000009
08005778 <SD_initialize>:
* @brief Initializes a Drive
* @param lun : not used
* @retval DSTATUS: Operation status
*/
DSTATUS SD_initialize(BYTE lun)
{
8005778: b580 push {r7, lr}
800577a: b082 sub sp, #8
800577c: af00 add r7, sp, #0
800577e: 4603 mov r3, r0
8005780: 71fb strb r3, [r7, #7]
#if !defined(DISABLE_SD_INIT)
if(BSP_SD_Init() == MSD_OK)
8005782: f7ff ff13 bl 80055ac <BSP_SD_Init>
8005786: 4603 mov r3, r0
8005788: 2b00 cmp r3, #0
800578a: d107 bne.n 800579c <SD_initialize+0x24>
{
Stat = SD_CheckStatus(lun);
800578c: 79fb ldrb r3, [r7, #7]
800578e: 4618 mov r0, r3
8005790: f7ff ffd4 bl 800573c <SD_CheckStatus>
8005794: 4603 mov r3, r0
8005796: 461a mov r2, r3
8005798: 4b04 ldr r3, [pc, #16] ; (80057ac <SD_initialize+0x34>)
800579a: 701a strb r2, [r3, #0]
#else
Stat = SD_CheckStatus(lun);
#endif
return Stat;
800579c: 4b03 ldr r3, [pc, #12] ; (80057ac <SD_initialize+0x34>)
800579e: 781b ldrb r3, [r3, #0]
80057a0: b2db uxtb r3, r3
}
80057a2: 4618 mov r0, r3
80057a4: 3708 adds r7, #8
80057a6: 46bd mov sp, r7
80057a8: bd80 pop {r7, pc}
80057aa: bf00 nop
80057ac: 20000009 .word 0x20000009
080057b0 <SD_status>:
* @brief Gets Disk Status
* @param lun : not used
* @retval DSTATUS: Operation status
*/
DSTATUS SD_status(BYTE lun)
{
80057b0: b580 push {r7, lr}
80057b2: b082 sub sp, #8
80057b4: af00 add r7, sp, #0
80057b6: 4603 mov r3, r0
80057b8: 71fb strb r3, [r7, #7]
return SD_CheckStatus(lun);
80057ba: 79fb ldrb r3, [r7, #7]
80057bc: 4618 mov r0, r3
80057be: f7ff ffbd bl 800573c <SD_CheckStatus>
80057c2: 4603 mov r3, r0
}
80057c4: 4618 mov r0, r3
80057c6: 3708 adds r7, #8
80057c8: 46bd mov sp, r7
80057ca: bd80 pop {r7, pc}
080057cc <SD_read>:
* @param count: Number of sectors to read (1..128)
* @retval DRESULT: Operation result
*/
DRESULT SD_read(BYTE lun, BYTE *buff, DWORD sector, UINT count)
{
80057cc: b580 push {r7, lr}
80057ce: b086 sub sp, #24
80057d0: af00 add r7, sp, #0
80057d2: 60b9 str r1, [r7, #8]
80057d4: 607a str r2, [r7, #4]
80057d6: 603b str r3, [r7, #0]
80057d8: 4603 mov r3, r0
80057da: 73fb strb r3, [r7, #15]
DRESULT res = RES_ERROR;
80057dc: 2301 movs r3, #1
80057de: 75fb strb r3, [r7, #23]
/*
* ensure the SDCard is ready for a new operation
*/
if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
80057e0: f247 5030 movw r0, #30000 ; 0x7530
80057e4: f7ff ff8c bl 8005700 <SD_CheckStatusWithTimeout>
80057e8: 4603 mov r3, r0
80057ea: 2b00 cmp r3, #0
80057ec: da01 bge.n 80057f2 <SD_read+0x26>
{
return res;
80057ee: 7dfb ldrb r3, [r7, #23]
80057f0: e03b b.n 800586a <SD_read+0x9e>
#if defined(ENABLE_SCRATCH_BUFFER)
if (!((uint32_t)buff & 0x3))
{
#endif
if(BSP_SD_ReadBlocks_DMA((uint32_t*)buff,
80057f2: 683a ldr r2, [r7, #0]
80057f4: 6879 ldr r1, [r7, #4]
80057f6: 68b8 ldr r0, [r7, #8]
80057f8: f7ff fefe bl 80055f8 <BSP_SD_ReadBlocks_DMA>
80057fc: 4603 mov r3, r0
80057fe: 2b00 cmp r3, #0
8005800: d132 bne.n 8005868 <SD_read+0x9c>
(uint32_t) (sector),
count) == MSD_OK)
{
ReadStatus = 0;
8005802: 4b1c ldr r3, [pc, #112] ; (8005874 <SD_read+0xa8>)
8005804: 2200 movs r2, #0
8005806: 601a str r2, [r3, #0]
/* Wait that the reading process is completed or a timeout occurs */
timeout = HAL_GetTick();
8005808: f7fb fbae bl 8000f68 <HAL_GetTick>
800580c: 6138 str r0, [r7, #16]
while((ReadStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT))
800580e: bf00 nop
8005810: 4b18 ldr r3, [pc, #96] ; (8005874 <SD_read+0xa8>)
8005812: 681b ldr r3, [r3, #0]
8005814: 2b00 cmp r3, #0
8005816: d108 bne.n 800582a <SD_read+0x5e>
8005818: f7fb fba6 bl 8000f68 <HAL_GetTick>
800581c: 4602 mov r2, r0
800581e: 693b ldr r3, [r7, #16]
8005820: 1ad3 subs r3, r2, r3
8005822: f247 522f movw r2, #29999 ; 0x752f
8005826: 4293 cmp r3, r2
8005828: d9f2 bls.n 8005810 <SD_read+0x44>
{
}
/* in case of a timeout return error */
if (ReadStatus == 0)
800582a: 4b12 ldr r3, [pc, #72] ; (8005874 <SD_read+0xa8>)
800582c: 681b ldr r3, [r3, #0]
800582e: 2b00 cmp r3, #0
8005830: d102 bne.n 8005838 <SD_read+0x6c>
{
res = RES_ERROR;
8005832: 2301 movs r3, #1
8005834: 75fb strb r3, [r7, #23]
8005836: e017 b.n 8005868 <SD_read+0x9c>
}
else
{
ReadStatus = 0;
8005838: 4b0e ldr r3, [pc, #56] ; (8005874 <SD_read+0xa8>)
800583a: 2200 movs r2, #0
800583c: 601a str r2, [r3, #0]
timeout = HAL_GetTick();
800583e: f7fb fb93 bl 8000f68 <HAL_GetTick>
8005842: 6138 str r0, [r7, #16]
while((HAL_GetTick() - timeout) < SD_TIMEOUT)
8005844: e007 b.n 8005856 <SD_read+0x8a>
{
if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
8005846: f7ff ff0b bl 8005660 <BSP_SD_GetCardState>
800584a: 4603 mov r3, r0
800584c: 2b00 cmp r3, #0
800584e: d102 bne.n 8005856 <SD_read+0x8a>
{
res = RES_OK;
8005850: 2300 movs r3, #0
8005852: 75fb strb r3, [r7, #23]
adjust the address and the D-Cache size to invalidate accordingly.
*/
alignedAddr = (uint32_t)buff & ~0x1F;
SCB_InvalidateDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
#endif
break;
8005854: e008 b.n 8005868 <SD_read+0x9c>
while((HAL_GetTick() - timeout) < SD_TIMEOUT)
8005856: f7fb fb87 bl 8000f68 <HAL_GetTick>
800585a: 4602 mov r2, r0
800585c: 693b ldr r3, [r7, #16]
800585e: 1ad3 subs r3, r2, r3
8005860: f247 522f movw r2, #29999 ; 0x752f
8005864: 4293 cmp r3, r2
8005866: d9ee bls.n 8005846 <SD_read+0x7a>
if ((i == count) && (ret == MSD_OK))
res = RES_OK;
}
#endif
return res;
8005868: 7dfb ldrb r3, [r7, #23]
}
800586a: 4618 mov r0, r3
800586c: 3718 adds r7, #24
800586e: 46bd mov sp, r7
8005870: bd80 pop {r7, pc}
8005872: bf00 nop
8005874: 2000002c .word 0x2000002c
08005878 <SD_write>:
* @retval DRESULT: Operation result
*/
#if _USE_WRITE == 1
DRESULT SD_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count)
{
8005878: b580 push {r7, lr}
800587a: b086 sub sp, #24
800587c: af00 add r7, sp, #0
800587e: 60b9 str r1, [r7, #8]
8005880: 607a str r2, [r7, #4]
8005882: 603b str r3, [r7, #0]
8005884: 4603 mov r3, r0
8005886: 73fb strb r3, [r7, #15]
DRESULT res = RES_ERROR;
8005888: 2301 movs r3, #1
800588a: 75fb strb r3, [r7, #23]
#if defined(ENABLE_SCRATCH_BUFFER)
uint8_t ret;
int i;
#endif
WriteStatus = 0;
800588c: 4b24 ldr r3, [pc, #144] ; (8005920 <SD_write+0xa8>)
800588e: 2200 movs r2, #0
8005890: 601a str r2, [r3, #0]
#if (ENABLE_SD_DMA_CACHE_MAINTENANCE == 1)
uint32_t alignedAddr;
#endif
if (SD_CheckStatusWithTimeout(SD_TIMEOUT) < 0)
8005892: f247 5030 movw r0, #30000 ; 0x7530
8005896: f7ff ff33 bl 8005700 <SD_CheckStatusWithTimeout>
800589a: 4603 mov r3, r0
800589c: 2b00 cmp r3, #0
800589e: da01 bge.n 80058a4 <SD_write+0x2c>
{
return res;
80058a0: 7dfb ldrb r3, [r7, #23]
80058a2: e038 b.n 8005916 <SD_write+0x9e>
*/
alignedAddr = (uint32_t)buff & ~0x1F;
SCB_CleanDCache_by_Addr((uint32_t*)alignedAddr, count*BLOCKSIZE + ((uint32_t)buff - alignedAddr));
#endif
if(BSP_SD_WriteBlocks_DMA((uint32_t*)buff,
80058a4: 683a ldr r2, [r7, #0]
80058a6: 6879 ldr r1, [r7, #4]
80058a8: 68b8 ldr r0, [r7, #8]
80058aa: f7ff febf bl 800562c <BSP_SD_WriteBlocks_DMA>
80058ae: 4603 mov r3, r0
80058b0: 2b00 cmp r3, #0
80058b2: d12f bne.n 8005914 <SD_write+0x9c>
(uint32_t)(sector),
count) == MSD_OK)
{
/* Wait that writing process is completed or a timeout occurs */
timeout = HAL_GetTick();
80058b4: f7fb fb58 bl 8000f68 <HAL_GetTick>
80058b8: 6138 str r0, [r7, #16]
while((WriteStatus == 0) && ((HAL_GetTick() - timeout) < SD_TIMEOUT))
80058ba: bf00 nop
80058bc: 4b18 ldr r3, [pc, #96] ; (8005920 <SD_write+0xa8>)
80058be: 681b ldr r3, [r3, #0]
80058c0: 2b00 cmp r3, #0
80058c2: d108 bne.n 80058d6 <SD_write+0x5e>
80058c4: f7fb fb50 bl 8000f68 <HAL_GetTick>
80058c8: 4602 mov r2, r0
80058ca: 693b ldr r3, [r7, #16]
80058cc: 1ad3 subs r3, r2, r3
80058ce: f247 522f movw r2, #29999 ; 0x752f
80058d2: 4293 cmp r3, r2
80058d4: d9f2 bls.n 80058bc <SD_write+0x44>
{
}
/* in case of a timeout return error */
if (WriteStatus == 0)
80058d6: 4b12 ldr r3, [pc, #72] ; (8005920 <SD_write+0xa8>)
80058d8: 681b ldr r3, [r3, #0]
80058da: 2b00 cmp r3, #0
80058dc: d102 bne.n 80058e4 <SD_write+0x6c>
{
res = RES_ERROR;
80058de: 2301 movs r3, #1
80058e0: 75fb strb r3, [r7, #23]
80058e2: e017 b.n 8005914 <SD_write+0x9c>
}
else
{
WriteStatus = 0;
80058e4: 4b0e ldr r3, [pc, #56] ; (8005920 <SD_write+0xa8>)
80058e6: 2200 movs r2, #0
80058e8: 601a str r2, [r3, #0]
timeout = HAL_GetTick();
80058ea: f7fb fb3d bl 8000f68 <HAL_GetTick>
80058ee: 6138 str r0, [r7, #16]
while((HAL_GetTick() - timeout) < SD_TIMEOUT)
80058f0: e007 b.n 8005902 <SD_write+0x8a>
{
if (BSP_SD_GetCardState() == SD_TRANSFER_OK)
80058f2: f7ff feb5 bl 8005660 <BSP_SD_GetCardState>
80058f6: 4603 mov r3, r0
80058f8: 2b00 cmp r3, #0
80058fa: d102 bne.n 8005902 <SD_write+0x8a>
{
res = RES_OK;
80058fc: 2300 movs r3, #0
80058fe: 75fb strb r3, [r7, #23]
break;
8005900: e008 b.n 8005914 <SD_write+0x9c>
while((HAL_GetTick() - timeout) < SD_TIMEOUT)
8005902: f7fb fb31 bl 8000f68 <HAL_GetTick>
8005906: 4602 mov r2, r0
8005908: 693b ldr r3, [r7, #16]
800590a: 1ad3 subs r3, r2, r3
800590c: f247 522f movw r2, #29999 ; 0x752f
8005910: 4293 cmp r3, r2
8005912: d9ee bls.n 80058f2 <SD_write+0x7a>
}
if ((i == count) && (ret == MSD_OK))
res = RES_OK;
}
#endif
return res;
8005914: 7dfb ldrb r3, [r7, #23]
}
8005916: 4618 mov r0, r3
8005918: 3718 adds r7, #24
800591a: 46bd mov sp, r7
800591c: bd80 pop {r7, pc}
800591e: bf00 nop
8005920: 20000028 .word 0x20000028
08005924 <SD_ioctl>:
* @param *buff: Buffer to send/receive control data
* @retval DRESULT: Operation result
*/
#if _USE_IOCTL == 1
DRESULT SD_ioctl(BYTE lun, BYTE cmd, void *buff)
{
8005924: b580 push {r7, lr}
8005926: b08c sub sp, #48 ; 0x30
8005928: af00 add r7, sp, #0
800592a: 4603 mov r3, r0
800592c: 603a str r2, [r7, #0]
800592e: 71fb strb r3, [r7, #7]
8005930: 460b mov r3, r1
8005932: 71bb strb r3, [r7, #6]
DRESULT res = RES_ERROR;
8005934: 2301 movs r3, #1
8005936: f887 302f strb.w r3, [r7, #47] ; 0x2f
BSP_SD_CardInfo CardInfo;
if (Stat & STA_NOINIT) return RES_NOTRDY;
800593a: 4b25 ldr r3, [pc, #148] ; (80059d0 <SD_ioctl+0xac>)
800593c: 781b ldrb r3, [r3, #0]
800593e: b2db uxtb r3, r3
8005940: f003 0301 and.w r3, r3, #1
8005944: 2b00 cmp r3, #0
8005946: d001 beq.n 800594c <SD_ioctl+0x28>
8005948: 2303 movs r3, #3
800594a: e03c b.n 80059c6 <SD_ioctl+0xa2>
switch (cmd)
800594c: 79bb ldrb r3, [r7, #6]
800594e: 2b03 cmp r3, #3
8005950: d834 bhi.n 80059bc <SD_ioctl+0x98>
8005952: a201 add r2, pc, #4 ; (adr r2, 8005958 <SD_ioctl+0x34>)
8005954: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005958: 08005969 .word 0x08005969
800595c: 08005971 .word 0x08005971
8005960: 08005989 .word 0x08005989
8005964: 080059a3 .word 0x080059a3
{
/* Make sure that no pending write process */
case CTRL_SYNC :
res = RES_OK;
8005968: 2300 movs r3, #0
800596a: f887 302f strb.w r3, [r7, #47] ; 0x2f
break;
800596e: e028 b.n 80059c2 <SD_ioctl+0x9e>
/* Get number of sectors on the disk (DWORD) */
case GET_SECTOR_COUNT :
BSP_SD_GetCardInfo(&CardInfo);
8005970: f107 030c add.w r3, r7, #12
8005974: 4618 mov r0, r3
8005976: f7ff fe83 bl 8005680 <BSP_SD_GetCardInfo>
*(DWORD*)buff = CardInfo.LogBlockNbr;
800597a: 6a7a ldr r2, [r7, #36] ; 0x24
800597c: 683b ldr r3, [r7, #0]
800597e: 601a str r2, [r3, #0]
res = RES_OK;
8005980: 2300 movs r3, #0
8005982: f887 302f strb.w r3, [r7, #47] ; 0x2f
break;
8005986: e01c b.n 80059c2 <SD_ioctl+0x9e>
/* Get R/W sector size (WORD) */
case GET_SECTOR_SIZE :
BSP_SD_GetCardInfo(&CardInfo);
8005988: f107 030c add.w r3, r7, #12
800598c: 4618 mov r0, r3
800598e: f7ff fe77 bl 8005680 <BSP_SD_GetCardInfo>
*(WORD*)buff = CardInfo.LogBlockSize;
8005992: 6abb ldr r3, [r7, #40] ; 0x28
8005994: b29a uxth r2, r3
8005996: 683b ldr r3, [r7, #0]
8005998: 801a strh r2, [r3, #0]
res = RES_OK;
800599a: 2300 movs r3, #0
800599c: f887 302f strb.w r3, [r7, #47] ; 0x2f
break;
80059a0: e00f b.n 80059c2 <SD_ioctl+0x9e>
/* Get erase block size in unit of sector (DWORD) */
case GET_BLOCK_SIZE :
BSP_SD_GetCardInfo(&CardInfo);
80059a2: f107 030c add.w r3, r7, #12
80059a6: 4618 mov r0, r3
80059a8: f7ff fe6a bl 8005680 <BSP_SD_GetCardInfo>
*(DWORD*)buff = CardInfo.LogBlockSize / SD_DEFAULT_BLOCK_SIZE;
80059ac: 6abb ldr r3, [r7, #40] ; 0x28
80059ae: 0a5a lsrs r2, r3, #9
80059b0: 683b ldr r3, [r7, #0]
80059b2: 601a str r2, [r3, #0]
res = RES_OK;
80059b4: 2300 movs r3, #0
80059b6: f887 302f strb.w r3, [r7, #47] ; 0x2f
break;
80059ba: e002 b.n 80059c2 <SD_ioctl+0x9e>
default:
res = RES_PARERR;
80059bc: 2304 movs r3, #4
80059be: f887 302f strb.w r3, [r7, #47] ; 0x2f
}
return res;
80059c2: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
}
80059c6: 4618 mov r0, r3
80059c8: 3730 adds r7, #48 ; 0x30
80059ca: 46bd mov sp, r7
80059cc: bd80 pop {r7, pc}
80059ce: bf00 nop
80059d0: 20000009 .word 0x20000009
080059d4 <BSP_SD_ReadCpltCallback>:
* @brief Rx Transfer completed callbacks
* @param hsd: SD handle
* @retval None
*/
void BSP_SD_ReadCpltCallback(void)
{
80059d4: b480 push {r7}
80059d6: af00 add r7, sp, #0
ReadStatus = 1;
80059d8: 4b03 ldr r3, [pc, #12] ; (80059e8 <BSP_SD_ReadCpltCallback+0x14>)
80059da: 2201 movs r2, #1
80059dc: 601a str r2, [r3, #0]
}
80059de: bf00 nop
80059e0: 46bd mov sp, r7
80059e2: f85d 7b04 ldr.w r7, [sp], #4
80059e6: 4770 bx lr
80059e8: 2000002c .word 0x2000002c
080059ec <FATFS_LinkDriverEx>:
* @param lun : only used for USB Key Disk to add multi-lun management
else the parameter must be equal to 0
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
{
80059ec: b480 push {r7}
80059ee: b087 sub sp, #28
80059f0: af00 add r7, sp, #0
80059f2: 60f8 str r0, [r7, #12]
80059f4: 60b9 str r1, [r7, #8]
80059f6: 4613 mov r3, r2
80059f8: 71fb strb r3, [r7, #7]
uint8_t ret = 1;
80059fa: 2301 movs r3, #1
80059fc: 75fb strb r3, [r7, #23]
uint8_t DiskNum = 0;
80059fe: 2300 movs r3, #0
8005a00: 75bb strb r3, [r7, #22]
if(disk.nbr < _VOLUMES)
8005a02: 4b1f ldr r3, [pc, #124] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a04: 7a5b ldrb r3, [r3, #9]
8005a06: b2db uxtb r3, r3
8005a08: 2b00 cmp r3, #0
8005a0a: d131 bne.n 8005a70 <FATFS_LinkDriverEx+0x84>
{
disk.is_initialized[disk.nbr] = 0;
8005a0c: 4b1c ldr r3, [pc, #112] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a0e: 7a5b ldrb r3, [r3, #9]
8005a10: b2db uxtb r3, r3
8005a12: 461a mov r2, r3
8005a14: 4b1a ldr r3, [pc, #104] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a16: 2100 movs r1, #0
8005a18: 5499 strb r1, [r3, r2]
disk.drv[disk.nbr] = drv;
8005a1a: 4b19 ldr r3, [pc, #100] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a1c: 7a5b ldrb r3, [r3, #9]
8005a1e: b2db uxtb r3, r3
8005a20: 4a17 ldr r2, [pc, #92] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a22: 009b lsls r3, r3, #2
8005a24: 4413 add r3, r2
8005a26: 68fa ldr r2, [r7, #12]
8005a28: 605a str r2, [r3, #4]
disk.lun[disk.nbr] = lun;
8005a2a: 4b15 ldr r3, [pc, #84] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a2c: 7a5b ldrb r3, [r3, #9]
8005a2e: b2db uxtb r3, r3
8005a30: 461a mov r2, r3
8005a32: 4b13 ldr r3, [pc, #76] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a34: 4413 add r3, r2
8005a36: 79fa ldrb r2, [r7, #7]
8005a38: 721a strb r2, [r3, #8]
DiskNum = disk.nbr++;
8005a3a: 4b11 ldr r3, [pc, #68] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a3c: 7a5b ldrb r3, [r3, #9]
8005a3e: b2db uxtb r3, r3
8005a40: 1c5a adds r2, r3, #1
8005a42: b2d1 uxtb r1, r2
8005a44: 4a0e ldr r2, [pc, #56] ; (8005a80 <FATFS_LinkDriverEx+0x94>)
8005a46: 7251 strb r1, [r2, #9]
8005a48: 75bb strb r3, [r7, #22]
path[0] = DiskNum + '0';
8005a4a: 7dbb ldrb r3, [r7, #22]
8005a4c: 3330 adds r3, #48 ; 0x30
8005a4e: b2da uxtb r2, r3
8005a50: 68bb ldr r3, [r7, #8]
8005a52: 701a strb r2, [r3, #0]
path[1] = ':';
8005a54: 68bb ldr r3, [r7, #8]
8005a56: 3301 adds r3, #1
8005a58: 223a movs r2, #58 ; 0x3a
8005a5a: 701a strb r2, [r3, #0]
path[2] = '/';
8005a5c: 68bb ldr r3, [r7, #8]
8005a5e: 3302 adds r3, #2
8005a60: 222f movs r2, #47 ; 0x2f
8005a62: 701a strb r2, [r3, #0]
path[3] = 0;
8005a64: 68bb ldr r3, [r7, #8]
8005a66: 3303 adds r3, #3
8005a68: 2200 movs r2, #0
8005a6a: 701a strb r2, [r3, #0]
ret = 0;
8005a6c: 2300 movs r3, #0
8005a6e: 75fb strb r3, [r7, #23]
}
return ret;
8005a70: 7dfb ldrb r3, [r7, #23]
}
8005a72: 4618 mov r0, r3
8005a74: 371c adds r7, #28
8005a76: 46bd mov sp, r7
8005a78: f85d 7b04 ldr.w r7, [sp], #4
8005a7c: 4770 bx lr
8005a7e: bf00 nop
8005a80: 20000030 .word 0x20000030
08005a84 <FATFS_LinkDriver>:
* @param drv: pointer to the disk IO Driver structure
* @param path: pointer to the logical drive path
* @retval Returns 0 in case of success, otherwise 1.
*/
uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
{
8005a84: b580 push {r7, lr}
8005a86: b082 sub sp, #8
8005a88: af00 add r7, sp, #0
8005a8a: 6078 str r0, [r7, #4]
8005a8c: 6039 str r1, [r7, #0]
return FATFS_LinkDriverEx(drv, path, 0);
8005a8e: 2200 movs r2, #0
8005a90: 6839 ldr r1, [r7, #0]
8005a92: 6878 ldr r0, [r7, #4]
8005a94: f7ff ffaa bl 80059ec <FATFS_LinkDriverEx>
8005a98: 4603 mov r3, r0
}
8005a9a: 4618 mov r0, r3
8005a9c: 3708 adds r7, #8
8005a9e: 46bd mov sp, r7
8005aa0: bd80 pop {r7, pc}
...
08005aa4 <__libc_init_array>:
8005aa4: b570 push {r4, r5, r6, lr}
8005aa6: 4d0d ldr r5, [pc, #52] ; (8005adc <__libc_init_array+0x38>)
8005aa8: 4c0d ldr r4, [pc, #52] ; (8005ae0 <__libc_init_array+0x3c>)
8005aaa: 1b64 subs r4, r4, r5
8005aac: 10a4 asrs r4, r4, #2
8005aae: 2600 movs r6, #0
8005ab0: 42a6 cmp r6, r4
8005ab2: d109 bne.n 8005ac8 <__libc_init_array+0x24>
8005ab4: 4d0b ldr r5, [pc, #44] ; (8005ae4 <__libc_init_array+0x40>)
8005ab6: 4c0c ldr r4, [pc, #48] ; (8005ae8 <__libc_init_array+0x44>)
8005ab8: f000 f820 bl 8005afc <_init>
8005abc: 1b64 subs r4, r4, r5
8005abe: 10a4 asrs r4, r4, #2
8005ac0: 2600 movs r6, #0
8005ac2: 42a6 cmp r6, r4
8005ac4: d105 bne.n 8005ad2 <__libc_init_array+0x2e>
8005ac6: bd70 pop {r4, r5, r6, pc}
8005ac8: f855 3b04 ldr.w r3, [r5], #4
8005acc: 4798 blx r3
8005ace: 3601 adds r6, #1
8005ad0: e7ee b.n 8005ab0 <__libc_init_array+0xc>
8005ad2: f855 3b04 ldr.w r3, [r5], #4
8005ad6: 4798 blx r3
8005ad8: 3601 adds r6, #1
8005ada: e7f2 b.n 8005ac2 <__libc_init_array+0x1e>
8005adc: 08005b48 .word 0x08005b48
8005ae0: 08005b48 .word 0x08005b48
8005ae4: 08005b48 .word 0x08005b48
8005ae8: 08005b4c .word 0x08005b4c
08005aec <memset>:
8005aec: 4402 add r2, r0
8005aee: 4603 mov r3, r0
8005af0: 4293 cmp r3, r2
8005af2: d100 bne.n 8005af6 <memset+0xa>
8005af4: 4770 bx lr
8005af6: f803 1b01 strb.w r1, [r3], #1
8005afa: e7f9 b.n 8005af0 <memset+0x4>
08005afc <_init>:
8005afc: b5f8 push {r3, r4, r5, r6, r7, lr}
8005afe: bf00 nop
8005b00: bcf8 pop {r3, r4, r5, r6, r7}
8005b02: bc08 pop {r3}
8005b04: 469e mov lr, r3
8005b06: 4770 bx lr
08005b08 <_fini>:
8005b08: b5f8 push {r3, r4, r5, r6, r7, lr}
8005b0a: bf00 nop
8005b0c: bcf8 pop {r3, r4, r5, r6, r7}
8005b0e: bc08 pop {r3}
8005b10: 469e mov lr, r3
8005b12: 4770 bx lr
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