stm32cube update
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
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<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
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<link rel="File-List" href="Library_files/filelist.xml">
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<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for BSP Components Common Drivers</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
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<style>
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||||
<!--
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||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{mso-style-parent:"";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
h2
|
||||
{mso-style-next:Normal;
|
||||
margin-top:12.0pt;
|
||||
margin-right:0in;
|
||||
margin-bottom:3.0pt;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
|
||||
font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
font-weight:bold;
|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
a:visited, span.MsoHyperlinkFollowed
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
p
|
||||
{mso-margin-top-alt:auto;
|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
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||||
@page Section1
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||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
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||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
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||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
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<meta content="MCD Application Team" name="author"></head>
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<body link="blue" vlink="blue">
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<div class="Section1">
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<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
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</o:p></span></p>
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||||
<div align="center">
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||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
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||||
<tbody>
|
||||
<tr>
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<td style="padding: 0cm;" valign="top">
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<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
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<tbody>
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<tr>
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<td style="vertical-align: top;">
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<p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
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Notes for BSP Components Common Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
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<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
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2015 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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</td>
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</tbody>
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</table>
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<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
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<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
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<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.0.1 / 21-July-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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Changes<o:p></o:p></span></u></b></p>
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<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">tsensor.h: Fix compilation issue on TSENSOR_InitTypeDef</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V4.0.0 / 22-June-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">accelero.h: add <span style="font-style: italic;">*DeInit</span> field in <span style="font-style: italic;">ACCELERO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">audio.h: add <span style="font-style: italic;">*DeInit</span> field in <span style="font-style: italic;">AUDIO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">idd.h: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">Shunt0StabDelay, Shunt1StabDelay, Shunt2StabDelay, Shunt3StabDelay, Shunt4StabDelay and ShuntNbOnBoard </span></span><span style="font-size: 10pt; font-family: Verdana;">fields in <span style="font-style: italic;">IDD_ConfigTypeDef</span> </span><span style="font-size: 10pt; font-family: Verdana;">structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">rename <span style="font-style: italic;">ShuntNumber</span> field to <span style="font-style: italic;">ShuntNbUsed</span> in </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">IDD_ConfigTypeDef</span> structure</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">magneto.h: add <span style="font-style: italic;">*DeInit</span> field in <span style="font-style: italic;">MAGNETO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Important Note:</span> this release V4.0.0 is not backward compatible with V3.0.0</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.0.0 / 28-April-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">accelero.h: </span><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">*LowPower</span> field in <span style="font-style: italic;">ACCELERO_DrvTypeDef</span> structure</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li><span style="font-size: 10pt; font-family: Verdana;">magneto.h: </span><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">*LowPower</span> field in <span style="font-style: italic;">MAGNETO_DrvTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">gyro.h: add <span style="font-style: italic;">*DeInit</span> and <span style="font-style: italic;">*LowPower</span> fields in <span style="font-style: italic;">GYRO_DrvTypeDef</span> structure<br></span></li><li><span style="font-size: 10pt; font-family: Verdana;">camera.h: add <span style="font-style: italic;">CAMERA_COLOR_EFFECT_NONE</span> define</span></li><li><span style="font-size: 10pt; font-family: Verdana;">idd.h: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">add <span style="font-style: italic;">MeasureNb</span>, <span style="font-style: italic;">DeltaDelayUnit</span> and <span style="font-style: italic;">DeltaDelayValue</span> fields in <span style="font-style: italic;">IDD_ConfigTypeDef</span> structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">rename <span style="font-style: italic;">PreDelay</span> field to <span style="font-style: italic;">PreDelayUnit</span> in </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">IDD_ConfigTypeDef</span> structure</span></li></ul>
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<li><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">Important Note:</span> this release V3.0.0 is not backward compatible with V2.2.0<br>
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<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Magnetometer </span><span style="font-size: 10pt; font-family: Verdana;">driver function prototypes added (magneto.h file)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Update "idd.h" file to provide DeInit() and WakeUp() services in IDD current measurement driver</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.0 / 06-February-2015 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
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|
||||
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||||
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|
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|
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<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IDD current measurement </span><span style="font-size: 10pt; font-family: Verdana;">driver function prototypes added (idd.h file)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">io.h: add new typedef enum IO_PinState with IO_PIN_RESET and IO_PIN_SET values<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 15-December-2014 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
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|
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|
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|
||||
|
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|
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|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
|
||||
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|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Update "io.h" file to support MFX (Multi Function eXpander) device available on some STM32 boards</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">add new entries for IO_ModeTypedef enumeration structure</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li><span style="font-size: 10pt; font-family: Verdana;">update the IO_DrvTypeDef structure</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update all return values and function parameters to uint32_t</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add a return value for Config field</span></li></ul></ul><li style="font-family: Verdana;"><small><span style="font-weight: bold;">Important Note</span>: this version V2.0.0 is not backward compatible with V1.2.1</small></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 / 02-December-2014 <o:p></o:p></span></h3>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
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|
||||
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||||
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|
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|
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||||
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||||
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|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">gyro.h: change “__GIRO_H” by “__GYRO_H” to fix compilation issue under Mac OS</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 18-June-2014 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
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|
||||
|
||||
|
||||
|
||||
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|
||||
|
||||
|
||||
|
||||
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
|
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|
||||
|
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|
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|
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|
||||
|
||||
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|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">EPD (</span><span style="font-size: 10pt; font-family: Verdana;">E Paper Display) driver function prototype added (epd.h file)<br>
|
||||
</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 21-March-2014 <o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
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|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
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|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
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|
||||
|
||||
|
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|
||||
|
||||
|
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|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Temperature Sensor driver function prototype added</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">First official release with </span><span style="font-size: 10pt; font-family: Verdana;">Accelerometer, </span><span style="font-size: 10pt; font-family: Verdana;">Audio, Camera, Gyroscope, IO, LCD and Touch Screen drivers function prototypes </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2>
|
||||
<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:</span><br>
|
||||
</font>
|
||||
<ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
||||
in binary form must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
|
||||
</font>
|
||||
</li></ol>
|
||||
<font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";"></span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
|
||||
|
||||
</div>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><font size="-1"></font><o:p></o:p></span></p>
|
||||
<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
|
||||
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
|
||||
</body></html>
|
||||
@@ -0,0 +1,143 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file accelero.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This header file contains the functions prototypes for the Accelerometer driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __ACCELERO_H
|
||||
#define __ACCELERO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ACCELERO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ACCELERO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ACCELERO_Driver_structure Accelerometer Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(uint16_t);
|
||||
void (*DeInit)(void);
|
||||
uint8_t (*ReadID)(void);
|
||||
void (*Reset)(void);
|
||||
void (*LowPower)(void);
|
||||
void (*ConfigIT)(void);
|
||||
void (*EnableIT)(uint8_t);
|
||||
void (*DisableIT)(uint8_t);
|
||||
uint8_t (*ITStatus)(uint16_t);
|
||||
void (*ClearIT)(void);
|
||||
void (*FilterConfig)(uint8_t);
|
||||
void (*FilterCmd)(uint8_t);
|
||||
void (*GetXYZ)(int16_t *);
|
||||
}ACCELERO_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ACCELERO_Configuration_structure Accelerometer Configuration structure
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ACCELERO struct */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Power_Mode; /* Power-down/Normal Mode */
|
||||
uint8_t AccOutput_DataRate; /* OUT data rate */
|
||||
uint8_t Axes_Enable; /* Axes enable */
|
||||
uint8_t High_Resolution; /* High Resolution enabling/disabling */
|
||||
uint8_t BlockData_Update; /* Block Data Update */
|
||||
uint8_t Endianness; /* Endian Data selection */
|
||||
uint8_t AccFull_Scale; /* Full Scale selection */
|
||||
uint8_t Communication_Mode;
|
||||
}ACCELERO_InitTypeDef;
|
||||
|
||||
/* ACCELERO High Pass Filter struct */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t HighPassFilter_Mode_Selection; /* Internal filter mode */
|
||||
uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */
|
||||
uint8_t HighPassFilter_AOI1; /* HPF_enabling/disabling for AOI function on interrupt 1 */
|
||||
uint8_t HighPassFilter_AOI2; /* HPF_enabling/disabling for AOI function on interrupt 2 */
|
||||
uint8_t HighPassFilter_Data_Sel;
|
||||
uint8_t HighPassFilter_Stat;
|
||||
}ACCELERO_FilterConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ACCELERO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,122 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file audio.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This header file contains the common defines and functions prototypes
|
||||
* for the Audio driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AUDIO_H
|
||||
#define __AUDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AUDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AUDIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Codec audio Standards */
|
||||
#define CODEC_STANDARD 0x04
|
||||
#define I2S_STANDARD I2S_STANDARD_PHILIPS
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AUDIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AUDIO_Driver_structure Audio Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t (*Init)(uint16_t, uint16_t, uint8_t, uint32_t);
|
||||
void (*DeInit)(void);
|
||||
uint32_t (*ReadID)(uint16_t);
|
||||
uint32_t (*Play)(uint16_t, uint16_t*, uint16_t);
|
||||
uint32_t (*Pause)(uint16_t);
|
||||
uint32_t (*Resume)(uint16_t);
|
||||
uint32_t (*Stop)(uint16_t, uint32_t);
|
||||
uint32_t (*SetFrequency)(uint16_t, uint32_t);
|
||||
uint32_t (*SetVolume)(uint16_t, uint8_t);
|
||||
uint32_t (*SetMute)(uint16_t, uint32_t);
|
||||
uint32_t (*SetOutputMode)(uint16_t, uint8_t);
|
||||
uint32_t (*Reset)(uint16_t);
|
||||
}AUDIO_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __AUDIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,141 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file camera.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This header file contains the common defines and functions prototypes
|
||||
* for the camera driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __CAMERA_H
|
||||
#define __CAMERA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAMERA
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAMERA_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAMERA_Driver_structure Camera Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(uint16_t, uint32_t);
|
||||
uint16_t (*ReadID)(uint16_t);
|
||||
void (*Config)(uint16_t, uint32_t, uint32_t, uint32_t);
|
||||
}CAMERA_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAMERA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAMERA_R160x120 0x00 /* QQVGA Resolution */
|
||||
#define CAMERA_R320x240 0x01 /* QVGA Resolution */
|
||||
#define CAMERA_R480x272 0x02 /* 480x272 Resolution */
|
||||
#define CAMERA_R640x480 0x03 /* VGA Resolution */
|
||||
|
||||
#define CAMERA_CONTRAST_BRIGHTNESS 0x00 /* Camera contrast brightness features */
|
||||
#define CAMERA_BLACK_WHITE 0x01 /* Camera black white feature */
|
||||
#define CAMERA_COLOR_EFFECT 0x03 /* Camera color effect feature */
|
||||
|
||||
#define CAMERA_BRIGHTNESS_LEVEL0 0x00 /* Brightness level -2 */
|
||||
#define CAMERA_BRIGHTNESS_LEVEL1 0x01 /* Brightness level -1 */
|
||||
#define CAMERA_BRIGHTNESS_LEVEL2 0x02 /* Brightness level 0 */
|
||||
#define CAMERA_BRIGHTNESS_LEVEL3 0x03 /* Brightness level +1 */
|
||||
#define CAMERA_BRIGHTNESS_LEVEL4 0x04 /* Brightness level +2 */
|
||||
|
||||
#define CAMERA_CONTRAST_LEVEL0 0x05 /* Contrast level -2 */
|
||||
#define CAMERA_CONTRAST_LEVEL1 0x06 /* Contrast level -1 */
|
||||
#define CAMERA_CONTRAST_LEVEL2 0x07 /* Contrast level 0 */
|
||||
#define CAMERA_CONTRAST_LEVEL3 0x08 /* Contrast level +1 */
|
||||
#define CAMERA_CONTRAST_LEVEL4 0x09 /* Contrast level +2 */
|
||||
|
||||
#define CAMERA_BLACK_WHITE_BW 0x00 /* Black and white effect */
|
||||
#define CAMERA_BLACK_WHITE_NEGATIVE 0x01 /* Negative effect */
|
||||
#define CAMERA_BLACK_WHITE_BW_NEGATIVE 0x02 /* BW and Negative effect */
|
||||
#define CAMERA_BLACK_WHITE_NORMAL 0x03 /* Normal effect */
|
||||
|
||||
#define CAMERA_COLOR_EFFECT_NONE 0x00 /* No effects */
|
||||
#define CAMERA_COLOR_EFFECT_BLUE 0x01 /* Blue effect */
|
||||
#define CAMERA_COLOR_EFFECT_GREEN 0x02 /* Green effect */
|
||||
#define CAMERA_COLOR_EFFECT_RED 0x03 /* Red effect */
|
||||
#define CAMERA_COLOR_EFFECT_ANTIQUE 0x04 /* Antique effect */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CAMERA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,115 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file epd.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This file contains all the functions prototypes for the
|
||||
* EPD (E Paper Display) driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __EPD_H
|
||||
#define __EPD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EPD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EPD_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EPD_Driver_structure E Paper Display Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(void);
|
||||
void (*WritePixel)(uint8_t);
|
||||
|
||||
/* Optimized operation */
|
||||
void (*SetDisplayWindow)(uint16_t, uint16_t, uint16_t, uint16_t);
|
||||
void (*RefreshDisplay)(void);
|
||||
void (*CloseChargePump)(void);
|
||||
|
||||
uint16_t (*GetEpdPixelWidth)(void);
|
||||
uint16_t (*GetEpdPixelHeight)(void);
|
||||
void (*DrawImage)(uint16_t, uint16_t, uint16_t, uint16_t, uint8_t*);
|
||||
}
|
||||
EPD_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* EPD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,145 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file gyro.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This header file contains the functions prototypes for the gyroscope driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __GYRO_H
|
||||
#define __GYRO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GYRO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GYRO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GYRO_Driver_structure Gyroscope Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(uint16_t);
|
||||
void (*DeInit)(void);
|
||||
uint8_t (*ReadID)(void);
|
||||
void (*Reset)(void);
|
||||
void (*LowPower)(uint16_t);
|
||||
void (*ConfigIT)(uint16_t);
|
||||
void (*EnableIT)(uint8_t);
|
||||
void (*DisableIT)(uint8_t);
|
||||
uint8_t (*ITStatus)(uint16_t, uint16_t);
|
||||
void (*ClearIT)(uint16_t, uint16_t);
|
||||
void (*FilterConfig)(uint8_t);
|
||||
void (*FilterCmd)(uint8_t);
|
||||
void (*GetXYZ)(float *);
|
||||
}GYRO_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GYRO_Config_structure Gyroscope Configuration structure
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Power_Mode; /* Power-down/Sleep/Normal Mode */
|
||||
uint8_t Output_DataRate; /* OUT data rate */
|
||||
uint8_t Axes_Enable; /* Axes enable */
|
||||
uint8_t Band_Width; /* Bandwidth selection */
|
||||
uint8_t BlockData_Update; /* Block Data Update */
|
||||
uint8_t Endianness; /* Endian Data selection */
|
||||
uint8_t Full_Scale; /* Full Scale selection */
|
||||
}GYRO_InitTypeDef;
|
||||
|
||||
/* GYRO High Pass Filter struct */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t HighPassFilter_Mode_Selection; /* Internal filter mode */
|
||||
uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */
|
||||
}GYRO_FilterConfigTypeDef;
|
||||
|
||||
/*GYRO Interrupt struct */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register */
|
||||
uint8_t Interrupt_Axes; /* X, Y, Z Axes Interrupts */
|
||||
uint8_t Interrupt_ActiveEdge; /* Interrupt Active edge */
|
||||
}GYRO_InterruptConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GYRO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,168 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file idd.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This file contains all the functions prototypes for the IDD driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __IDD_H
|
||||
#define __IDD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IDD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IDD_Exported_Types IDD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IDD_Config_structure IDD Configuration structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t AmpliGain; /*!< Specifies ampli gain value
|
||||
*/
|
||||
uint16_t VddMin; /*!< Specifies minimum MCU VDD can reach to protect MCU from reset
|
||||
*/
|
||||
uint16_t Shunt0Value; /*!< Specifies value of Shunt 0 if existing
|
||||
*/
|
||||
uint16_t Shunt1Value; /*!< Specifies value of Shunt 1 if existing
|
||||
*/
|
||||
uint16_t Shunt2Value; /*!< Specifies value of Shunt 2 if existing
|
||||
*/
|
||||
uint16_t Shunt3Value; /*!< Specifies value of Shunt 3 if existing
|
||||
*/
|
||||
uint16_t Shunt4Value; /*!< Specifies value of Shunt 4 if existing
|
||||
*/
|
||||
uint16_t Shunt0StabDelay; /*!< Specifies delay of Shunt 0 stabilization if existing
|
||||
*/
|
||||
uint16_t Shunt1StabDelay; /*!< Specifies delay of Shunt 1 stabilization if existing
|
||||
*/
|
||||
uint16_t Shunt2StabDelay; /*!< Specifies delay of Shunt 2 stabilization if existing
|
||||
*/
|
||||
uint16_t Shunt3StabDelay; /*!< Specifies delay of Shunt 3 stabilization if existing
|
||||
*/
|
||||
uint16_t Shunt4StabDelay; /*!< Specifies delay of Shunt 4 stabilization if existing
|
||||
*/
|
||||
uint8_t ShuntNbOnBoard; /*!< Specifies number of shunts that are present on board
|
||||
This parameter can be a value of @ref IDD_shunt_number */
|
||||
uint8_t ShuntNbUsed; /*!< Specifies number of shunts used for measurement
|
||||
This parameter can be a value of @ref IDD_shunt_number */
|
||||
uint8_t VrefMeasurement; /*!< Specifies if Vref is automatically measured before each Idd measurement
|
||||
This parameter can be a value of @ref IDD_Vref_Measurement */
|
||||
uint8_t Calibration; /*!< Specifies if calibration is done before each Idd measurement
|
||||
*/
|
||||
uint8_t PreDelayUnit; /*!< Specifies Pre delay unit
|
||||
This parameter can be a value of @ref IDD_PreDelay */
|
||||
uint8_t PreDelayValue; /*!< Specifies Pre delay value in selected unit
|
||||
*/
|
||||
uint8_t MeasureNb; /*!< Specifies number of Measure to be performed
|
||||
This parameter can be a value between 1 and 256 */
|
||||
uint8_t DeltaDelayUnit; /*!< Specifies Delta delay unit
|
||||
This parameter can be a value of @ref IDD_DeltaDelay */
|
||||
uint8_t DeltaDelayValue; /*!< Specifies Delta delay between 2 measures
|
||||
value can be between 1 and 128 */
|
||||
}IDD_ConfigTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IDD_Driver_structure IDD Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(uint16_t);
|
||||
void (*DeInit)(uint16_t);
|
||||
uint16_t (*ReadID)(uint16_t);
|
||||
void (*Reset)(uint16_t);
|
||||
void (*LowPower)(uint16_t);
|
||||
void (*WakeUp)(uint16_t);
|
||||
void (*Start)(uint16_t);
|
||||
void (*Config)(uint16_t,IDD_ConfigTypeDef);
|
||||
void (*GetValue)(uint16_t, uint32_t *);
|
||||
void (*EnableIT)(uint16_t);
|
||||
void (*ClearIT)(uint16_t);
|
||||
uint8_t (*GetITStatus)(uint16_t);
|
||||
void (*DisableIT)(uint16_t);
|
||||
void (*ErrorEnableIT)(uint16_t);
|
||||
void (*ErrorClearIT)(uint16_t);
|
||||
uint8_t (*ErrorGetITStatus)(uint16_t);
|
||||
void (*ErrorDisableIT)(uint16_t);
|
||||
uint8_t (*ErrorGetSrc)(uint16_t);
|
||||
uint8_t (*ErrorGetCode)(uint16_t);
|
||||
}IDD_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IDD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,150 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file io.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This file contains all the functions prototypes for the IO driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __IO_H
|
||||
#define __IO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IO_PIN_RESET = 0,
|
||||
IO_PIN_SET
|
||||
}IO_PinState;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
IO_MODE_INPUT = 0, /* input floating */
|
||||
IO_MODE_OUTPUT, /* output Push Pull */
|
||||
IO_MODE_IT_RISING_EDGE, /* float input - irq detect on rising edge */
|
||||
IO_MODE_IT_FALLING_EDGE, /* float input - irq detect on falling edge */
|
||||
IO_MODE_IT_LOW_LEVEL, /* float input - irq detect on low level */
|
||||
IO_MODE_IT_HIGH_LEVEL, /* float input - irq detect on high level */
|
||||
/* following modes only available on MFX*/
|
||||
IO_MODE_ANALOG, /* analog mode */
|
||||
IO_MODE_OFF, /* when pin isn't used*/
|
||||
IO_MODE_INPUT_PU, /* input with internal pull up resistor */
|
||||
IO_MODE_INPUT_PD, /* input with internal pull down resistor */
|
||||
IO_MODE_OUTPUT_OD, /* Open Drain output without internal resistor */
|
||||
IO_MODE_OUTPUT_OD_PU, /* Open Drain output with internal pullup resistor */
|
||||
IO_MODE_OUTPUT_OD_PD, /* Open Drain output with internal pulldown resistor */
|
||||
IO_MODE_OUTPUT_PP, /* PushPull output without internal resistor */
|
||||
IO_MODE_OUTPUT_PP_PU, /* PushPull output with internal pullup resistor */
|
||||
IO_MODE_OUTPUT_PP_PD, /* PushPull output with internal pulldown resistor */
|
||||
IO_MODE_IT_RISING_EDGE_PU, /* push up resistor input - irq on rising edge */
|
||||
IO_MODE_IT_RISING_EDGE_PD, /* push dw resistor input - irq on rising edge */
|
||||
IO_MODE_IT_FALLING_EDGE_PU, /* push up resistor input - irq on falling edge */
|
||||
IO_MODE_IT_FALLING_EDGE_PD, /* push dw resistor input - irq on falling edge */
|
||||
IO_MODE_IT_LOW_LEVEL_PU, /* push up resistor input - irq detect on low level */
|
||||
IO_MODE_IT_LOW_LEVEL_PD, /* push dw resistor input - irq detect on low level */
|
||||
IO_MODE_IT_HIGH_LEVEL_PU, /* push up resistor input - irq detect on high level */
|
||||
IO_MODE_IT_HIGH_LEVEL_PD, /* push dw resistor input - irq detect on high level */
|
||||
|
||||
}IO_ModeTypedef;
|
||||
|
||||
/** @defgroup IO_Driver_structure IO Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(uint16_t);
|
||||
uint16_t (*ReadID)(uint16_t);
|
||||
void (*Reset)(uint16_t);
|
||||
|
||||
void (*Start)(uint16_t, uint32_t);
|
||||
uint8_t (*Config)(uint16_t, uint32_t, IO_ModeTypedef);
|
||||
void (*WritePin)(uint16_t, uint32_t, uint8_t);
|
||||
uint32_t (*ReadPin)(uint16_t, uint32_t);
|
||||
|
||||
void (*EnableIT)(uint16_t);
|
||||
void (*DisableIT)(uint16_t);
|
||||
uint32_t (*ITStatus)(uint16_t, uint32_t);
|
||||
void (*ClearIT)(uint16_t, uint32_t);
|
||||
|
||||
}IO_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,114 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file lcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This file contains all the functions prototypes for the LCD driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __LCD_H
|
||||
#define __LCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Driver_structure LCD Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(void);
|
||||
uint16_t (*ReadID)(void);
|
||||
void (*DisplayOn)(void);
|
||||
void (*DisplayOff)(void);
|
||||
void (*SetCursor)(uint16_t, uint16_t);
|
||||
void (*WritePixel)(uint16_t, uint16_t, uint16_t);
|
||||
uint16_t (*ReadPixel)(uint16_t, uint16_t);
|
||||
|
||||
/* Optimized operation */
|
||||
void (*SetDisplayWindow)(uint16_t, uint16_t, uint16_t, uint16_t);
|
||||
void (*DrawHLine)(uint16_t, uint16_t, uint16_t, uint16_t);
|
||||
void (*DrawVLine)(uint16_t, uint16_t, uint16_t, uint16_t);
|
||||
|
||||
uint16_t (*GetLcdPixelWidth)(void);
|
||||
uint16_t (*GetLcdPixelHeight)(void);
|
||||
void (*DrawBitmap)(uint16_t, uint16_t, uint8_t*);
|
||||
void (*DrawRGBImage)(uint16_t, uint16_t, uint16_t, uint16_t, uint8_t*);
|
||||
}LCD_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,125 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file magneto.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This header file contains the functions prototypes for the MAGNETO driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MAGNETO_H
|
||||
#define __MAGNETO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MAGNETO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MAGNETO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MAGNETO_Config_structure Magnetometer Configuration structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Register1;
|
||||
uint8_t Register2;
|
||||
uint8_t Register3;
|
||||
uint8_t Register4;
|
||||
uint8_t Register5;
|
||||
}MAGNETO_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MAGNETO_Driver_structure Magnetometer Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(MAGNETO_InitTypeDef);
|
||||
void (*DeInit)(void);
|
||||
uint8_t (*ReadID)(void);
|
||||
void (*Reset)(void);
|
||||
void (*LowPower)(void);
|
||||
void (*ConfigIT)(void);
|
||||
void (*EnableIT)(uint8_t);
|
||||
void (*DisableIT)(uint8_t);
|
||||
uint8_t (*ITStatus)(uint16_t);
|
||||
void (*ClearIT)(void);
|
||||
void (*FilterConfig)(uint8_t);
|
||||
void (*FilterCmd)(uint8_t);
|
||||
void (*GetXYZ)(int16_t *);
|
||||
}MAGNETO_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MAGNETO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,107 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file ts.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This file contains all the functions prototypes for the Touch Screen driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TS_H
|
||||
#define __TS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TS_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TS_Driver_structure Touch Sensor Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(uint16_t);
|
||||
uint16_t (*ReadID)(uint16_t);
|
||||
void (*Reset)(uint16_t);
|
||||
void (*Start)(uint16_t);
|
||||
uint8_t (*DetectTouch)(uint16_t);
|
||||
void (*GetXY)(uint16_t, uint16_t*, uint16_t*);
|
||||
void (*EnableIT)(uint16_t);
|
||||
void (*ClearIT)(uint16_t);
|
||||
uint8_t (*GetITStatus)(uint16_t);
|
||||
void (*DisableIT)(uint16_t);
|
||||
}TS_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,118 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file tsensor.h
|
||||
* @author MCD Application Team
|
||||
* @version V4.0.1
|
||||
* @date 21-July-2015
|
||||
* @brief This header file contains the functions prototypes for the
|
||||
* Temperature Sensor driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSENSOR_H
|
||||
#define __TSENSOR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TSENSOR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TSENSOR_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TSENSOR_Config_structure Temperature Sensor Configuration structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t AlertMode; /* Alert Mode Temperature out of range*/
|
||||
uint8_t ConversionMode; /* Continuous/One Shot Mode */
|
||||
uint8_t ConversionResolution; /* Temperature Resolution */
|
||||
uint8_t ConversionRate; /* Number of measure per second */
|
||||
uint8_t TemperatureLimitHigh; /* High Temperature Limit Range */
|
||||
uint8_t TemperatureLimitLow; /* Low Temperature Limit Range */
|
||||
}TSENSOR_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TSENSOR_Driver_structure Temperature Sensor Driver structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void (*Init)(uint16_t, TSENSOR_InitTypeDef *);
|
||||
uint8_t (*IsReady)(uint16_t, uint32_t);
|
||||
uint8_t (*ReadStatus)(uint16_t);
|
||||
uint16_t (*ReadTemp)(uint16_t);
|
||||
}TSENSOR_DrvTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TSENSOR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,743 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
|
||||
|
||||
|
||||
<link rel="File-List" href="Library_files/filelist.xml">
|
||||
|
||||
|
||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for CS43L22 Component Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{mso-style-parent:"";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
h2
|
||||
{mso-style-next:Normal;
|
||||
margin-top:12.0pt;
|
||||
margin-right:0in;
|
||||
margin-bottom:3.0pt;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
|
||||
font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
font-weight:bold;
|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
a:visited, span.MsoHyperlinkFollowed
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
p
|
||||
{mso-margin-top-alt:auto;
|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
@page Section1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
|
||||
<meta content="MCD Application Team" name="author"></head>
|
||||
<body link="blue" vlink="blue">
|
||||
<div class="Section1">
|
||||
<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
||||
</o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="vertical-align: top;">
|
||||
<p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for CS43L22 Component Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
||||
2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
<tr style="">
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<span style="font-family: "Times New Roman";">
|
||||
</span>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 206px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.3 / 05-October-2017 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.c/.h: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update VOLUME_CONVERT macro to return 255 if the input volume is greater than 100.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Update cs43l22_SetVolume API to check on convertedvol instead of Volume</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 206px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.2 / 02-October-2015 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.c/.h: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Move VOLUME_CONVERT macro from cs43l22.h to cs43l22.c as internally used to convert volume.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add literals instead of magic number for cs34l22 registers.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 220px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.1 / 16-September-2015 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.c: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Enable the digital soft ramp to avoid clac noise.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Improve mute/unmute by muting/unmuting also the DAC inputs. </span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 24-June-2015 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.h/.c: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add codec de-initialization function: cs43l22_DeInit()</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add Audio IO </span><span style="font-size: 10pt; font-family: Verdana;">de-initialization function prototype: AUDIO_IO_DeInit()</span></li><li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">NOTE:</span> This release must be used with BSP Common
|
||||
driver V4.0.0 or later</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-February-2015 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.h/.c: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add AUDIO_FREQUENCY_xxx defines for frequencies capabilities (8K to 192K)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add codec reset function: cs43l22_Reset()<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 02-December-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;">
|
||||
<li><span style="font-size: 10pt; font-family: Verdana;">cs43l22.h: change "\" by "/" in the include path to fix compilation issue under Linux</span></li>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 210px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;">
|
||||
<li><span style="font-size: 10pt; font-family: Verdana;">First official release of CS43L22 audio codec </span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
|
||||
</ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2>
|
||||
<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:</span><br>
|
||||
</font>
|
||||
<ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
||||
in binary form must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
|
||||
</font>
|
||||
</li></ol>
|
||||
<font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";"></span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
|
||||
|
||||
</div>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><font size="-1"></font><o:p></o:p></span></p>
|
||||
<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
|
||||
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"></span></u></span><span style="color: black;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
|
||||
</body></html>
|
||||
@@ -0,0 +1,493 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file cs43l22.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides the CS43L22 Audio Codec driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "cs43l22.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CS43L22
|
||||
* @brief This file provides a set of functions needed to drive the
|
||||
* CS43L22 audio codec.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define VOLUME_CONVERT(Volume) (((Volume) > 100)? 255:((uint8_t)(((Volume) * 255) / 100)))
|
||||
/* Uncomment this line to enable verifying data sent to codec after each write
|
||||
operation (for debug purpose) */
|
||||
#if !defined (VERIFY_WRITTENDATA)
|
||||
/* #define VERIFY_WRITTENDATA */
|
||||
#endif /* VERIFY_WRITTENDATA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Audio codec driver structure initialization */
|
||||
AUDIO_DrvTypeDef cs43l22_drv =
|
||||
{
|
||||
cs43l22_Init,
|
||||
cs43l22_DeInit,
|
||||
cs43l22_ReadID,
|
||||
|
||||
cs43l22_Play,
|
||||
cs43l22_Pause,
|
||||
cs43l22_Resume,
|
||||
cs43l22_Stop,
|
||||
|
||||
cs43l22_SetFrequency,
|
||||
cs43l22_SetVolume,
|
||||
cs43l22_SetMute,
|
||||
cs43l22_SetOutputMode,
|
||||
cs43l22_Reset,
|
||||
};
|
||||
|
||||
static uint8_t Is_cs43l22_Stop = 1;
|
||||
|
||||
volatile uint8_t OutputDev = 0;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Function_Prototypes
|
||||
* @{
|
||||
*/
|
||||
static uint8_t CODEC_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the audio codec and the control interface.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @param OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
|
||||
* OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO .
|
||||
* @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_Init(uint16_t DeviceAddr, uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
|
||||
/* Initialize the Control interface of the Audio Codec */
|
||||
AUDIO_IO_Init();
|
||||
|
||||
/* Keep Codec powered OFF */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x01);
|
||||
|
||||
/*Save Output device for mute ON/OFF procedure*/
|
||||
switch (OutputDevice)
|
||||
{
|
||||
case OUTPUT_DEVICE_SPEAKER:
|
||||
OutputDev = 0xFA;
|
||||
break;
|
||||
|
||||
case OUTPUT_DEVICE_HEADPHONE:
|
||||
OutputDev = 0xAF;
|
||||
break;
|
||||
|
||||
case OUTPUT_DEVICE_BOTH:
|
||||
OutputDev = 0xAA;
|
||||
break;
|
||||
|
||||
case OUTPUT_DEVICE_AUTO:
|
||||
OutputDev = 0x05;
|
||||
break;
|
||||
|
||||
default:
|
||||
OutputDev = 0x05;
|
||||
break;
|
||||
}
|
||||
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, OutputDev);
|
||||
|
||||
/* Clock configuration: Auto detection */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_CLOCKING_CTL, 0x81);
|
||||
|
||||
/* Set the Slave Mode and the audio Standard */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_INTERFACE_CTL1, CODEC_STANDARD);
|
||||
|
||||
/* Set the Master volume */
|
||||
counter += cs43l22_SetVolume(DeviceAddr, Volume);
|
||||
|
||||
/* If the Speaker is enabled, set the Mono mode and volume attenuation level */
|
||||
if(OutputDevice != OUTPUT_DEVICE_HEADPHONE)
|
||||
{
|
||||
/* Set the Speaker Mono mode */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_PLAYBACK_CTL2, 0x06);
|
||||
|
||||
/* Set the Speaker attenuation level */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_SPEAKER_A_VOL, 0x00);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_SPEAKER_B_VOL, 0x00);
|
||||
}
|
||||
|
||||
/* Additional configuration for the CODEC. These configurations are done to reduce
|
||||
the time needed for the Codec to power off. If these configurations are removed,
|
||||
then a long delay should be added between powering off the Codec and switching
|
||||
off the I2S peripheral MCLK clock (which is the operating clock for Codec).
|
||||
If this delay is not inserted, then the codec will not shut down properly and
|
||||
it results in high noise after shut down. */
|
||||
|
||||
/* Disable the analog soft ramp */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_ANALOG_ZC_SR_SETT, 0x00);
|
||||
/* Disable the digital soft ramp */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MISC_CTL, 0x04);
|
||||
/* Disable the limiter attack level */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_LIMIT_CTL1, 0x00);
|
||||
/* Adjust Bass and Treble levels */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_TONE_CTL, 0x0F);
|
||||
/* Adjust PCM volume level */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_PCMA_VOL, 0x0A);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_PCMB_VOL, 0x0A);
|
||||
|
||||
/* Return communication control value */
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the audio codec.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void cs43l22_DeInit(void)
|
||||
{
|
||||
/* Deinitialize Audio Codec interface */
|
||||
AUDIO_IO_DeInit();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the CS43L22 ID.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @retval The CS43L22 ID
|
||||
*/
|
||||
uint32_t cs43l22_ReadID(uint16_t DeviceAddr)
|
||||
{
|
||||
uint8_t Value;
|
||||
/* Initialize the Control interface of the Audio Codec */
|
||||
AUDIO_IO_Init();
|
||||
|
||||
Value = AUDIO_IO_Read(DeviceAddr, CS43L22_CHIPID_ADDR);
|
||||
Value = (Value & CS43L22_ID_MASK);
|
||||
|
||||
return((uint32_t) Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the audio Codec play feature.
|
||||
* @note For this codec no Play options are required.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
|
||||
if(Is_cs43l22_Stop == 1)
|
||||
{
|
||||
/* Enable the digital soft ramp */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MISC_CTL, 0x06);
|
||||
|
||||
/* Enable Output device */
|
||||
counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
|
||||
|
||||
/* Power on the Codec */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x9E);
|
||||
Is_cs43l22_Stop = 0;
|
||||
}
|
||||
|
||||
/* Return communication control value */
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Pauses playing on the audio codec.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_Pause(uint16_t DeviceAddr)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
|
||||
/* Pause the audio file playing */
|
||||
/* Mute the output first */
|
||||
counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_ON);
|
||||
|
||||
/* Put the Codec in Power save mode */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x01);
|
||||
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resumes playing on the audio codec.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_Resume(uint16_t DeviceAddr)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
volatile uint32_t index = 0x00;
|
||||
/* Resumes the audio file playing */
|
||||
/* Unmute the output first */
|
||||
counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
|
||||
|
||||
for(index = 0x00; index < 0xFF; index++);
|
||||
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, OutputDev);
|
||||
|
||||
/* Exit the Power save mode */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x9E);
|
||||
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops audio Codec playing. It powers down the codec.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @param CodecPdwnMode: selects the power down mode.
|
||||
* - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
|
||||
* mode, the codec is set to default configuration
|
||||
* (user should re-Initialize the codec in order to
|
||||
* play again the audio stream).
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
|
||||
/* Mute the output first */
|
||||
counter += cs43l22_SetMute(DeviceAddr, AUDIO_MUTE_ON);
|
||||
|
||||
/* Disable the digital soft ramp */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MISC_CTL, 0x04);
|
||||
|
||||
/* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL1, 0x9F);
|
||||
|
||||
Is_cs43l22_Stop = 1;
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets higher or lower the codec volume level.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @param Volume: a byte value from 0 to 255 (refer to codec registers
|
||||
* description for more details).
|
||||
*
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_SetVolume(uint16_t DeviceAddr, uint8_t Volume)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
uint8_t convertedvol = VOLUME_CONVERT(Volume);
|
||||
|
||||
if(convertedvol > 0xE6)
|
||||
{
|
||||
/* Set the Master volume */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_A_VOL, convertedvol - 0xE7);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_B_VOL, convertedvol - 0xE7);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the Master volume */
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_A_VOL, convertedvol + 0x19);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_MASTER_B_VOL, convertedvol + 0x19);
|
||||
}
|
||||
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets new frequency.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @param AudioFreq: Audio frequency used to play the audio stream.
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the mute feature on the audio codec.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
|
||||
* mute mode.
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_SetMute(uint16_t DeviceAddr, uint32_t Cmd)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
|
||||
/* Set the Mute mode */
|
||||
if(Cmd == AUDIO_MUTE_ON)
|
||||
{
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xFF);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_A_VOL, 0x01);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_B_VOL, 0x01);
|
||||
}
|
||||
else /* AUDIO_MUTE_OFF Disable the Mute */
|
||||
{
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_A_VOL, 0x00);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_HEADPHONE_B_VOL, 0x00);
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, OutputDev);
|
||||
}
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Switch dynamically (while audio file is played) the output target
|
||||
* (speaker or headphone).
|
||||
* @note This function modifies a global variable of the audio codec driver: OutputDev.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
|
||||
* OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_SetOutputMode(uint16_t DeviceAddr, uint8_t Output)
|
||||
{
|
||||
uint32_t counter = 0;
|
||||
|
||||
switch (Output)
|
||||
{
|
||||
case OUTPUT_DEVICE_SPEAKER:
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xFA); /* SPK always ON & HP always OFF */
|
||||
OutputDev = 0xFA;
|
||||
break;
|
||||
|
||||
case OUTPUT_DEVICE_HEADPHONE:
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xAF); /* SPK always OFF & HP always ON */
|
||||
OutputDev = 0xAF;
|
||||
break;
|
||||
|
||||
case OUTPUT_DEVICE_BOTH:
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0xAA); /* SPK always ON & HP always ON */
|
||||
OutputDev = 0xAA;
|
||||
break;
|
||||
|
||||
case OUTPUT_DEVICE_AUTO:
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0x05); /* Detect the HP or the SPK automatically */
|
||||
OutputDev = 0x05;
|
||||
break;
|
||||
|
||||
default:
|
||||
counter += CODEC_IO_Write(DeviceAddr, CS43L22_REG_POWER_CTL2, 0x05); /* Detect the HP or the SPK automatically */
|
||||
OutputDev = 0x05;
|
||||
break;
|
||||
}
|
||||
return counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets cs43l22 registers.
|
||||
* @param DeviceAddr: Device address on communication Bus.
|
||||
* @retval 0 if correct communication, else wrong communication
|
||||
*/
|
||||
uint32_t cs43l22_Reset(uint16_t DeviceAddr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes/Read a single data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Reg address
|
||||
* @param Value: Data to be written
|
||||
* @retval None
|
||||
*/
|
||||
static uint8_t CODEC_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
AUDIO_IO_Write(Addr, Reg, Value);
|
||||
|
||||
#ifdef VERIFY_WRITTENDATA
|
||||
/* Verify that the data has been correctly written */
|
||||
result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1;
|
||||
#endif /* VERIFY_WRITTENDATA */
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,226 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file cs43l22.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the cs43l22.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __CS43L22_H
|
||||
#define __CS43L22_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "../Common/audio.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Component
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CS43L22
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Codec User defines ******************************/
|
||||
/******************************************************************************/
|
||||
/* Codec output DEVICE */
|
||||
#define OUTPUT_DEVICE_SPEAKER 1
|
||||
#define OUTPUT_DEVICE_HEADPHONE 2
|
||||
#define OUTPUT_DEVICE_BOTH 3
|
||||
#define OUTPUT_DEVICE_AUTO 4
|
||||
|
||||
/* Volume Levels values */
|
||||
#define DEFAULT_VOLMIN 0x00
|
||||
#define DEFAULT_VOLMAX 0xFF
|
||||
#define DEFAULT_VOLSTEP 0x04
|
||||
|
||||
#define AUDIO_PAUSE 0
|
||||
#define AUDIO_RESUME 1
|
||||
|
||||
/* Codec POWER DOWN modes */
|
||||
#define CODEC_PDWN_HW 1
|
||||
#define CODEC_PDWN_SW 2
|
||||
|
||||
/* MUTE commands */
|
||||
#define AUDIO_MUTE_ON 1
|
||||
#define AUDIO_MUTE_OFF 0
|
||||
|
||||
/* AUDIO FREQUENCY */
|
||||
#define AUDIO_FREQUENCY_192K ((uint32_t)192000)
|
||||
#define AUDIO_FREQUENCY_96K ((uint32_t)96000)
|
||||
#define AUDIO_FREQUENCY_48K ((uint32_t)48000)
|
||||
#define AUDIO_FREQUENCY_44K ((uint32_t)44100)
|
||||
#define AUDIO_FREQUENCY_32K ((uint32_t)32000)
|
||||
#define AUDIO_FREQUENCY_22K ((uint32_t)22050)
|
||||
#define AUDIO_FREQUENCY_16K ((uint32_t)16000)
|
||||
#define AUDIO_FREQUENCY_11K ((uint32_t)11025)
|
||||
#define AUDIO_FREQUENCY_8K ((uint32_t)8000)
|
||||
|
||||
/** CS43l22 Registers ***/
|
||||
#define CS43L22_REG_ID 0x01
|
||||
#define CS43L22_REG_POWER_CTL1 0x02
|
||||
#define CS43L22_REG_POWER_CTL2 0x04
|
||||
#define CS43L22_REG_CLOCKING_CTL 0x05
|
||||
#define CS43L22_REG_INTERFACE_CTL1 0x06
|
||||
#define CS43L22_REG_INTERFACE_CTL2 0x07
|
||||
#define CS43L22_REG_PASSTHR_A_SELECT 0x08
|
||||
#define CS43L22_REG_PASSTHR_B_SELECT 0x09
|
||||
#define CS43L22_REG_ANALOG_ZC_SR_SETT 0x0A
|
||||
#define CS43L22_REG_PASSTHR_GANG_CTL 0x0C
|
||||
#define CS43L22_REG_PLAYBACK_CTL1 0x0D
|
||||
#define CS43L22_REG_MISC_CTL 0x0E
|
||||
#define CS43L22_REG_PLAYBACK_CTL2 0x0F
|
||||
#define CS43L22_REG_PASSTHR_A_VOL 0x14
|
||||
#define CS43L22_REG_PASSTHR_B_VOL 0x15
|
||||
#define CS43L22_REG_PCMA_VOL 0x1A
|
||||
#define CS43L22_REG_PCMB_VOL 0x1B
|
||||
#define CS43L22_REG_BEEP_FREQ_ON_TIME 0x1C
|
||||
#define CS43L22_REG_BEEP_VOL_OFF_TIME 0x1D
|
||||
#define CS43L22_REG_BEEP_TONE_CFG 0x1E
|
||||
#define CS43L22_REG_TONE_CTL 0x1F
|
||||
#define CS43L22_REG_MASTER_A_VOL 0x20
|
||||
#define CS43L22_REG_MASTER_B_VOL 0x21
|
||||
#define CS43L22_REG_HEADPHONE_A_VOL 0x22
|
||||
#define CS43L22_REG_HEADPHONE_B_VOL 0x23
|
||||
#define CS43L22_REG_SPEAKER_A_VOL 0x24
|
||||
#define CS43L22_REG_SPEAKER_B_VOL 0x25
|
||||
#define CS43L22_REG_CH_MIXER_SWAP 0x26
|
||||
#define CS43L22_REG_LIMIT_CTL1 0x27
|
||||
#define CS43L22_REG_LIMIT_CTL2 0x28
|
||||
#define CS43L22_REG_LIMIT_ATTACK_RATE 0x29
|
||||
#define CS43L22_REG_OVF_CLK_STATUS 0x2E
|
||||
#define CS43L22_REG_BATT_COMPENSATION 0x2F
|
||||
#define CS43L22_REG_VP_BATTERY_LEVEL 0x30
|
||||
#define CS43L22_REG_SPEAKER_STATUS 0x31
|
||||
#define CS43L22_REG_TEMPMONITOR_CTL 0x32
|
||||
#define CS43L22_REG_THERMAL_FOLDBACK 0x33
|
||||
#define CS43L22_REG_CHARGE_PUMP_FREQ 0x34
|
||||
|
||||
/******************************************************************************/
|
||||
/****************************** REGISTER MAPPING ******************************/
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @brief CS43L22 ID
|
||||
*/
|
||||
#define CS43L22_ID 0xE0
|
||||
#define CS43L22_ID_MASK 0xF8
|
||||
/**
|
||||
* @brief Chip ID Register: Chip I.D. and Revision Register
|
||||
* Read only register
|
||||
* Default value: 0x01
|
||||
* [7:3] CHIPID[4:0]: I.D. code for the CS43L22.
|
||||
* Default value: 11100b
|
||||
* [2:0] REVID[2:0]: CS43L22 revision level.
|
||||
* Default value:
|
||||
* 000 - Rev A0
|
||||
* 001 - Rev A1
|
||||
* 010 - Rev B0
|
||||
* 011 - Rev B1
|
||||
*/
|
||||
#define CS43L22_CHIPID_ADDR 0x01
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CS43L22_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
Audio Codec functions
|
||||
------------------------------------------------------------------------------*/
|
||||
/* High Layer codec functions */
|
||||
uint32_t cs43l22_Init(uint16_t DeviceAddr, uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
|
||||
void cs43l22_DeInit(void);
|
||||
uint32_t cs43l22_ReadID(uint16_t DeviceAddr);
|
||||
uint32_t cs43l22_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size);
|
||||
uint32_t cs43l22_Pause(uint16_t DeviceAddr);
|
||||
uint32_t cs43l22_Resume(uint16_t DeviceAddr);
|
||||
uint32_t cs43l22_Stop(uint16_t DeviceAddr, uint32_t Cmd);
|
||||
uint32_t cs43l22_SetVolume(uint16_t DeviceAddr, uint8_t Volume);
|
||||
uint32_t cs43l22_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq);
|
||||
uint32_t cs43l22_SetMute(uint16_t DeviceAddr, uint32_t Cmd);
|
||||
uint32_t cs43l22_SetOutputMode(uint16_t DeviceAddr, uint8_t Output);
|
||||
uint32_t cs43l22_Reset(uint16_t DeviceAddr);
|
||||
|
||||
/* AUDIO IO functions */
|
||||
void AUDIO_IO_Init(void);
|
||||
void AUDIO_IO_DeInit(void);
|
||||
void AUDIO_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
|
||||
uint8_t AUDIO_IO_Read(uint8_t Addr, uint8_t Reg);
|
||||
|
||||
/* Audio driver structure */
|
||||
extern AUDIO_DrvTypeDef cs43l22_drv;
|
||||
|
||||
#endif /* __CS43L22_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,55 @@
|
||||
<!DOCTYPE html>
|
||||
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
|
||||
<head>
|
||||
<meta charset="utf-8" />
|
||||
<meta name="generator" content="pandoc" />
|
||||
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
|
||||
<title>Release Notes for I3G4250D Component Drivers</title>
|
||||
<style type="text/css">
|
||||
code{white-space: pre-wrap;}
|
||||
span.smallcaps{font-variant: small-caps;}
|
||||
span.underline{text-decoration: underline;}
|
||||
div.column{display: inline-block; vertical-align: top; width: 50%;}
|
||||
</style>
|
||||
<link rel="stylesheet" href="_htmresc/mini-st.css" />
|
||||
<!--[if lt IE 9]>
|
||||
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
|
||||
<![endif]-->
|
||||
</head>
|
||||
<body>
|
||||
<div class="row">
|
||||
<div class="col-sm-12 col-lg-4">
|
||||
<div class="card fluid">
|
||||
<div class="sectione dark">
|
||||
<center>
|
||||
<h1 id="release-notes-for-i3g4250d-component-drivers"><small>Release Notes for</small> <mark>I3G4250D Component Drivers</mark></h1>
|
||||
<p>Copyright © 2020 STMicroelectronics<br />
|
||||
</p>
|
||||
<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
|
||||
</center>
|
||||
</div>
|
||||
</div>
|
||||
<h1 id="license">License</h1>
|
||||
<p>Licensed by ST under BSD 3-Clause license (the "License"). You may not use this package except in compliance with the License. You may obtain a copy of the License at:</p>
|
||||
<p><a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a></p>
|
||||
<h1 id="purpose">Purpose</h1>
|
||||
<p>This directory contains the I3G4250D component drivers.</p>
|
||||
</div>
|
||||
<div class="col-sm-12 col-lg-8">
|
||||
<h1 id="update-history">Update History</h1>
|
||||
<div class="collapse">
|
||||
<input type="checkbox" id="collapse-section1" Checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 20-July-2020</label>
|
||||
<div>
|
||||
<h2 id="main-changes">Main Changes</h2>
|
||||
<ul>
|
||||
<li>First official release of I3G4250D gyroscope</li>
|
||||
</ul>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
</div>
|
||||
<footer class="sticky">
|
||||
For complete documentation on <mark>STM32 Microcontrollers</mark> , visit: <a href="http://www.st.com/STM32">http://www.st.com/STM32</a>
|
||||
</footer>
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
|
After Width: | Height: | Size: 18 KiB |
@@ -0,0 +1,399 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file i3g4250d.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides a set of functions needed to manage the I3G4250D,
|
||||
* ST MEMS motion sensor, 3-axis digital output gyroscope.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "i3g4250d.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I3G4250D
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I3G4250D_Private_TypesDefinitions Private Types Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3G4250D_Private_Defines Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3G4250D_Private_Macros Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3G4250D_Private_Variables Private Variables
|
||||
* @{
|
||||
*/
|
||||
GYRO_DrvTypeDef I3g4250Drv =
|
||||
{
|
||||
I3G4250D_Init,
|
||||
I3G4250D_DeInit,
|
||||
I3G4250D_ReadID,
|
||||
I3G4250D_RebootCmd,
|
||||
I3G4250D_LowPower,
|
||||
I3G4250D_INT1InterruptConfig,
|
||||
I3G4250D_EnableIT,
|
||||
I3G4250D_DisableIT,
|
||||
0,
|
||||
0,
|
||||
I3G4250D_FilterConfig,
|
||||
I3G4250D_FilterCmd,
|
||||
I3G4250D_ReadXYZAngRate
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3G4250D_Private_FunctionPrototypes Private Function Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I3G4250D_Private_Functions Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set I3G4250D Initialization.
|
||||
* @param I3G4250D_InitStruct: pointer to a I3G4250D_InitTypeDef structure
|
||||
* that contains the configuration setting for the I3G4250D.
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_Init(uint16_t InitStruct)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Configure the low level interface */
|
||||
GYRO_IO_Init();
|
||||
|
||||
/* Write value to MEMS CTRL_REG1 register */
|
||||
ctrl = (uint8_t) InitStruct;
|
||||
GYRO_IO_Write(&ctrl, I3G4250D_CTRL_REG1_ADDR, 1);
|
||||
|
||||
/* Write value to MEMS CTRL_REG4 register */
|
||||
ctrl = (uint8_t)(InitStruct >> 8);
|
||||
GYRO_IO_Write(&ctrl, I3G4250D_CTRL_REG4_ADDR, 1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief I3G4250D De-initialization
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_DeInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read ID address of I3G4250D
|
||||
* @param None
|
||||
* @retval ID name
|
||||
*/
|
||||
uint8_t I3G4250D_ReadID(void)
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
/* Configure the low level interface */
|
||||
GYRO_IO_Init();
|
||||
|
||||
/* Read WHO I AM register */
|
||||
GYRO_IO_Read(&tmp, I3G4250D_WHO_AM_I_ADDR, 1);
|
||||
|
||||
/* Return the ID */
|
||||
return (uint8_t)tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reboot memory content of I3G4250D
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_RebootCmd(void)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG5 register */
|
||||
GYRO_IO_Read(&tmpreg, I3G4250D_CTRL_REG5_ADDR, 1);
|
||||
|
||||
/* Enable or Disable the reboot memory */
|
||||
tmpreg |= I3G4250D_BOOT_REBOOTMEMORY;
|
||||
|
||||
/* Write value to MEMS CTRL_REG5 register */
|
||||
GYRO_IO_Write(&tmpreg, I3G4250D_CTRL_REG5_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set I3G4250D in low-power mode
|
||||
* @param I3G4250D_InitStruct: pointer to a I3G4250D_InitTypeDef structure
|
||||
* that contains the configuration setting for the I3G4250D.
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_LowPower(uint16_t InitStruct)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Write value to MEMS CTRL_REG1 register */
|
||||
ctrl = (uint8_t) InitStruct;
|
||||
GYRO_IO_Write(&ctrl, I3G4250D_CTRL_REG1_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set I3G4250D Interrupt INT1 configuration
|
||||
* @param Int1Config: the configuration setting for the I3G4250D Interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_INT1InterruptConfig(uint16_t Int1Config)
|
||||
{
|
||||
uint8_t ctrl_cfr = 0x00, ctrl3 = 0x00;
|
||||
|
||||
/* Read INT1_CFG register */
|
||||
GYRO_IO_Read(&ctrl_cfr, I3G4250D_INT1_CFG_ADDR, 1);
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
GYRO_IO_Read(&ctrl3, I3G4250D_CTRL_REG3_ADDR, 1);
|
||||
|
||||
ctrl_cfr &= 0x80;
|
||||
ctrl_cfr |= ((uint8_t) Int1Config >> 8);
|
||||
|
||||
ctrl3 &= 0xDF;
|
||||
ctrl3 |= ((uint8_t) Int1Config);
|
||||
|
||||
/* Write value to MEMS INT1_CFG register */
|
||||
GYRO_IO_Write(&ctrl_cfr, I3G4250D_INT1_CFG_ADDR, 1);
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
GYRO_IO_Write(&ctrl3, I3G4250D_CTRL_REG3_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable INT1 or INT2 interrupt
|
||||
* @param IntSel: choice of INT1 or INT2
|
||||
* This parameter can be:
|
||||
* @arg I3G4250D_INT1
|
||||
* @arg I3G4250D_INT2
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_EnableIT(uint8_t IntSel)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
GYRO_IO_Read(&tmpreg, I3G4250D_CTRL_REG3_ADDR, 1);
|
||||
|
||||
if (IntSel == I3G4250D_INT1)
|
||||
{
|
||||
tmpreg &= 0x7F;
|
||||
tmpreg |= I3G4250D_INT1INTERRUPT_ENABLE;
|
||||
}
|
||||
else if (IntSel == I3G4250D_INT2)
|
||||
{
|
||||
tmpreg &= 0xF7;
|
||||
tmpreg |= I3G4250D_INT2INTERRUPT_ENABLE;
|
||||
}
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
GYRO_IO_Write(&tmpreg, I3G4250D_CTRL_REG3_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable INT1 or INT2 interrupt
|
||||
* @param IntSel: choice of INT1 or INT2
|
||||
* This parameter can be:
|
||||
* @arg I3G4250D_INT1
|
||||
* @arg I3G4250D_INT2
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_DisableIT(uint8_t IntSel)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
GYRO_IO_Read(&tmpreg, I3G4250D_CTRL_REG3_ADDR, 1);
|
||||
|
||||
if (IntSel == I3G4250D_INT1)
|
||||
{
|
||||
tmpreg &= 0x7F;
|
||||
tmpreg |= I3G4250D_INT1INTERRUPT_DISABLE;
|
||||
}
|
||||
else if (IntSel == I3G4250D_INT2)
|
||||
{
|
||||
tmpreg &= 0xF7;
|
||||
tmpreg |= I3G4250D_INT2INTERRUPT_DISABLE;
|
||||
}
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
GYRO_IO_Write(&tmpreg, I3G4250D_CTRL_REG3_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set High Pass Filter Modality
|
||||
* @param FilterStruct: contains the configuration setting for the L3GD20.
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_FilterConfig(uint8_t FilterStruct)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
GYRO_IO_Read(&tmpreg, I3G4250D_CTRL_REG2_ADDR, 1);
|
||||
|
||||
tmpreg &= 0xC0;
|
||||
|
||||
/* Configure MEMS: mode and cutoff frequency */
|
||||
tmpreg |= FilterStruct;
|
||||
|
||||
/* Write value to MEMS CTRL_REG2 register */
|
||||
GYRO_IO_Write(&tmpreg, I3G4250D_CTRL_REG2_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable High Pass Filter
|
||||
* @param HighPassFilterState: new state of the High Pass Filter feature.
|
||||
* This parameter can be:
|
||||
* @arg: I3G4250D_HIGHPASSFILTER_DISABLE
|
||||
* @arg: I3G4250D_HIGHPASSFILTER_ENABLE
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_FilterCmd(uint8_t HighPassFilterState)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG5 register */
|
||||
GYRO_IO_Read(&tmpreg, I3G4250D_CTRL_REG5_ADDR, 1);
|
||||
|
||||
tmpreg &= 0xEF;
|
||||
|
||||
tmpreg |= HighPassFilterState;
|
||||
|
||||
/* Write value to MEMS CTRL_REG5 register */
|
||||
GYRO_IO_Write(&tmpreg, I3G4250D_CTRL_REG5_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get status for I3G4250D data
|
||||
* @param None
|
||||
* @retval Data status in a I3G4250D Data
|
||||
*/
|
||||
uint8_t I3G4250D_GetDataStatus(void)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read STATUS_REG register */
|
||||
GYRO_IO_Read(&tmpreg, I3G4250D_STATUS_REG_ADDR, 1);
|
||||
|
||||
return tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Calculate the I3G4250D angular data.
|
||||
* @param pfData: Data out pointer
|
||||
* @retval None
|
||||
*/
|
||||
void I3G4250D_ReadXYZAngRate(float *pfData)
|
||||
{
|
||||
uint8_t tmpbuffer[6] = {0};
|
||||
int16_t RawData[3] = {0};
|
||||
uint8_t tmpreg = 0;
|
||||
float sensitivity = 0;
|
||||
int i = 0;
|
||||
|
||||
GYRO_IO_Read(&tmpreg, I3G4250D_CTRL_REG4_ADDR, 1);
|
||||
|
||||
GYRO_IO_Read(tmpbuffer, I3G4250D_OUT_X_L_ADDR, 6);
|
||||
|
||||
/* check in the control register 4 the data alignment (Big Endian or Little Endian)*/
|
||||
if (!(tmpreg & I3G4250D_BLE_MSB))
|
||||
{
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
RawData[i] = (int16_t)(((uint16_t)tmpbuffer[2 * i + 1] << 8) + tmpbuffer[2 * i]);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
RawData[i] = (int16_t)(((uint16_t)tmpbuffer[2 * i] << 8) + tmpbuffer[2 * i + 1]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch the sensitivity value set in the CRTL4 */
|
||||
switch (tmpreg & I3G4250D_FULLSCALE_SELECTION)
|
||||
{
|
||||
case I3G4250D_FULLSCALE_245:
|
||||
sensitivity = I3G4250D_SENSITIVITY_245DPS;
|
||||
break;
|
||||
|
||||
case I3G4250D_FULLSCALE_500:
|
||||
sensitivity = I3G4250D_SENSITIVITY_500DPS;
|
||||
break;
|
||||
|
||||
case I3G4250D_FULLSCALE_2000:
|
||||
sensitivity = I3G4250D_SENSITIVITY_2000DPS;
|
||||
break;
|
||||
}
|
||||
/* Multiplied by sensitivity */
|
||||
for (i = 0; i < 3; i++)
|
||||
{
|
||||
pfData[i] = (float)(RawData[i] * sensitivity);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,305 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file i3g4250d.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the i3g4250d.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __I3G4250D_H
|
||||
#define __I3G4250D_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "../Common/gyro.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I3G4250D
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I3G4250D_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** START REGISTER MAPPING **************************/
|
||||
/******************************************************************************/
|
||||
#define I3G4250D_WHO_AM_I_ADDR 0x0F /* device identification register */
|
||||
#define I3G4250D_CTRL_REG1_ADDR 0x20 /* Control register 1 */
|
||||
#define I3G4250D_CTRL_REG2_ADDR 0x21 /* Control register 2 */
|
||||
#define I3G4250D_CTRL_REG3_ADDR 0x22 /* Control register 3 */
|
||||
#define I3G4250D_CTRL_REG4_ADDR 0x23 /* Control register 4 */
|
||||
#define I3G4250D_CTRL_REG5_ADDR 0x24 /* Control register 5 */
|
||||
#define I3G4250D_REFERENCE_REG_ADDR 0x25 /* Reference register */
|
||||
#define I3G4250D_OUT_TEMP_ADDR 0x26 /* Out temp register */
|
||||
#define I3G4250D_STATUS_REG_ADDR 0x27 /* Status register */
|
||||
#define I3G4250D_OUT_X_L_ADDR 0x28 /* Output Register X */
|
||||
#define I3G4250D_OUT_X_H_ADDR 0x29 /* Output Register X */
|
||||
#define I3G4250D_OUT_Y_L_ADDR 0x2A /* Output Register Y */
|
||||
#define I3G4250D_OUT_Y_H_ADDR 0x2B /* Output Register Y */
|
||||
#define I3G4250D_OUT_Z_L_ADDR 0x2C /* Output Register Z */
|
||||
#define I3G4250D_OUT_Z_H_ADDR 0x2D /* Output Register Z */
|
||||
#define I3G4250D_FIFO_CTRL_REG_ADDR 0x2E /* Fifo control Register */
|
||||
#define I3G4250D_FIFO_SRC_REG_ADDR 0x2F /* Fifo src Register */
|
||||
|
||||
#define I3G4250D_INT1_CFG_ADDR 0x30 /* Interrupt 1 configuration Register */
|
||||
#define I3G4250D_INT1_SRC_ADDR 0x31 /* Interrupt 1 source Register */
|
||||
#define I3G4250D_INT1_TSH_XH_ADDR 0x32 /* Interrupt 1 Threshold X register */
|
||||
#define I3G4250D_INT1_TSH_XL_ADDR 0x33 /* Interrupt 1 Threshold X register */
|
||||
#define I3G4250D_INT1_TSH_YH_ADDR 0x34 /* Interrupt 1 Threshold Y register */
|
||||
#define I3G4250D_INT1_TSH_YL_ADDR 0x35 /* Interrupt 1 Threshold Y register */
|
||||
#define I3G4250D_INT1_TSH_ZH_ADDR 0x36 /* Interrupt 1 Threshold Z register */
|
||||
#define I3G4250D_INT1_TSH_ZL_ADDR 0x37 /* Interrupt 1 Threshold Z register */
|
||||
#define I3G4250D_INT1_DURATION_ADDR 0x38 /* Interrupt 1 DURATION register */
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** END REGISTER MAPPING ***************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define I_AM_I3G4250D ((uint8_t)0xD3)
|
||||
|
||||
/** @defgroup Power_Mode_selection Power Mode selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_MODE_POWERDOWN ((uint8_t)0x00)
|
||||
#define I3G4250D_MODE_ACTIVE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OutPut_DataRate_Selection OutPut DataRate Selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_OUTPUT_DATARATE_1 ((uint8_t)0x00)
|
||||
#define I3G4250D_OUTPUT_DATARATE_2 ((uint8_t)0x40)
|
||||
#define I3G4250D_OUTPUT_DATARATE_3 ((uint8_t)0x80)
|
||||
#define I3G4250D_OUTPUT_DATARATE_4 ((uint8_t)0xC0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Axes_Selection Axes Selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_X_ENABLE ((uint8_t)0x02)
|
||||
#define I3G4250D_Y_ENABLE ((uint8_t)0x01)
|
||||
#define I3G4250D_Z_ENABLE ((uint8_t)0x04)
|
||||
#define I3G4250D_AXES_ENABLE ((uint8_t)0x07)
|
||||
#define I3G4250D_AXES_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bandwidth_Selection Bandwidth Selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_BANDWIDTH_1 ((uint8_t)0x00)
|
||||
#define I3G4250D_BANDWIDTH_2 ((uint8_t)0x10)
|
||||
#define I3G4250D_BANDWIDTH_3 ((uint8_t)0x20)
|
||||
#define I3G4250D_BANDWIDTH_4 ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Full_Scale_Selection Full Scale Selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_FULLSCALE_245 ((uint8_t)0x00)
|
||||
#define I3G4250D_FULLSCALE_500 ((uint8_t)0x10)
|
||||
#define I3G4250D_FULLSCALE_2000 ((uint8_t)0x20)
|
||||
#define I3G4250D_FULLSCALE_SELECTION ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Full_Scale_Sensitivity Full Scale Sensitivity
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_SENSITIVITY_245DPS ((float)8.75f) /*!< gyroscope sensitivity with 250 dps full scale [DPS/LSB] */
|
||||
#define I3G4250D_SENSITIVITY_500DPS ((float)17.50f) /*!< gyroscope sensitivity with 500 dps full scale [DPS/LSB] */
|
||||
#define I3G4250D_SENSITIVITY_2000DPS ((float)70.00f) /*!< gyroscope sensitivity with 2000 dps full scale [DPS/LSB] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup Block_Data_Update Block Data Update
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_BlockDataUpdate_Continous ((uint8_t)0x00)
|
||||
#define I3G4250D_BlockDataUpdate_Single ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Endian_Data_selection Endian Data selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_BLE_LSB ((uint8_t)0x00)
|
||||
#define I3G4250D_BLE_MSB ((uint8_t)0x40)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup High_Pass_Filter_status High Pass Filter status
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_HIGHPASSFILTER_DISABLE ((uint8_t)0x00)
|
||||
#define I3G4250D_HIGHPASSFILTER_ENABLE ((uint8_t)0x10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT1_INT2_selection Selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_INT1 ((uint8_t)0x00)
|
||||
#define I3G4250D_INT2 ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT1_Interrupt_status Interrupt Status
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_INT1INTERRUPT_DISABLE ((uint8_t)0x00)
|
||||
#define I3G4250D_INT1INTERRUPT_ENABLE ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT2_Interrupt_status Interrupt Status
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_INT2INTERRUPT_DISABLE ((uint8_t)0x00)
|
||||
#define I3G4250D_INT2INTERRUPT_ENABLE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT1_Interrupt_ActiveEdge Interrupt Active Edge
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_INT1INTERRUPT_LOW_EDGE ((uint8_t)0x20)
|
||||
#define I3G4250D_INT1INTERRUPT_HIGH_EDGE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Boot_Mode_selection Boot Mode Selection
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_BOOT_NORMALMODE ((uint8_t)0x00)
|
||||
#define I3G4250D_BOOT_REBOOTMEMORY ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup High_Pass_Filter_Mode High Pass Filter Mode
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_HPM_NORMAL_MODE_RES ((uint8_t)0x00)
|
||||
#define I3G4250D_HPM_REF_SIGNAL ((uint8_t)0x10)
|
||||
#define I3G4250D_HPM_NORMAL_MODE ((uint8_t)0x20)
|
||||
#define I3G4250D_HPM_AUTORESET_INT ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup High_Pass_CUT OFF_Frequency High Pass CUT OFF Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I3G4250D_HPFCF_0 0x00
|
||||
#define I3G4250D_HPFCF_1 0x01
|
||||
#define I3G4250D_HPFCF_2 0x02
|
||||
#define I3G4250D_HPFCF_3 0x03
|
||||
#define I3G4250D_HPFCF_4 0x04
|
||||
#define I3G4250D_HPFCF_5 0x05
|
||||
#define I3G4250D_HPFCF_6 0x06
|
||||
#define I3G4250D_HPFCF_7 0x07
|
||||
#define I3G4250D_HPFCF_8 0x08
|
||||
#define I3G4250D_HPFCF_9 0x09
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup I3G4250D_Exported_Functions Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/* Sensor Configuration Functions */
|
||||
void I3G4250D_Init(uint16_t InitStruct);
|
||||
void I3G4250D_DeInit(void);
|
||||
void I3G4250D_LowPower(uint16_t InitStruct);
|
||||
uint8_t I3G4250D_ReadID(void);
|
||||
void I3G4250D_RebootCmd(void);
|
||||
|
||||
/* Interrupt Configuration Functions */
|
||||
void I3G4250D_INT1InterruptConfig(uint16_t Int1Config);
|
||||
void I3G4250D_EnableIT(uint8_t IntSel);
|
||||
void I3G4250D_DisableIT(uint8_t IntSel);
|
||||
|
||||
/* High Pass Filter Configuration Functions */
|
||||
void I3G4250D_FilterConfig(uint8_t FilterStruct);
|
||||
void I3G4250D_FilterCmd(uint8_t HighPassFilterState);
|
||||
void I3G4250D_ReadXYZAngRate(float *pfData);
|
||||
uint8_t I3G4250D_GetDataStatus(void);
|
||||
|
||||
/* Gyroscope IO functions */
|
||||
void GYRO_IO_Init(void);
|
||||
void GYRO_IO_DeInit(void);
|
||||
void GYRO_IO_Write(uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
|
||||
void GYRO_IO_Read(uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);
|
||||
|
||||
/* Gyroscope driver structure */
|
||||
extern GYRO_DrvTypeDef I3g4250Drv;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __I3G4250D_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,461 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
|
||||
|
||||
|
||||
<link rel="File-List" href="Library_files/filelist.xml">
|
||||
|
||||
|
||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for L3GD20 Component Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{mso-style-parent:"";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
h2
|
||||
{mso-style-next:Normal;
|
||||
margin-top:12.0pt;
|
||||
margin-right:0in;
|
||||
margin-bottom:3.0pt;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
|
||||
font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
font-weight:bold;
|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
a:visited, span.MsoHyperlinkFollowed
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
p
|
||||
{mso-margin-top-alt:auto;
|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
@page Section1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
|
||||
<meta content="MCD Application Team" name="author"></head>
|
||||
<body link="blue" vlink="blue">
|
||||
<div class="Section1">
|
||||
<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
||||
</o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="vertical-align: top;">
|
||||
<p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for L3GD20 Component Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
||||
2015 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table style="width: 675pt;" class="MsoNormalTable" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
<tr style="">
|
||||
<td style="padding: 0cm;" valign="top"><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 24-June-2015 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">l3gd20.h/.c: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add gyroscope de-initialization function: L3GD20_DeInit()</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add gyroscope low power configuration</span><span style="font-size: 10pt; font-family: Verdana;"> function: </span><span style="font-size: 10pt; font-family: Verdana;">L3GD20_LowPower</span><span style="font-size: 10pt; font-family: Verdana;">()</span></li><li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">NOTE:</span> This release must be used with BSP Common
|
||||
driver V4.0.0 or later</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 27-November-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;">
|
||||
<li><span style="font-size: 10pt; font-family: Verdana;">l3gd20.h: change "\" by "/" in the include path to fix compilation issue under Linux</span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span></li><li><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous formatting and comments update</span></li>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-June-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;">
|
||||
<li><span style="font-size: 10pt; font-family: Verdana;">Update to support new revision of L3GD20 component having new device ID 0xD5 (new define added: I_AM_L3GD20_TR)</span></li>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release of L3GD20 gyroscope </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:</span><br>
|
||||
</font>
|
||||
<ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
||||
in binary form must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
|
||||
</font>
|
||||
</li></ol>
|
||||
<font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";"></span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
|
||||
|
||||
</div>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><o:p></o:p></span></p>
|
||||
<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
|
||||
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span></div>
|
||||
</td>
|
||||
</tr>
|
||||
<tr><td style="padding: 0cm;" valign="top"><br>
|
||||
</td></tr></tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
|
||||
</body></html>
|
||||
@@ -0,0 +1,416 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file l3gd20.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 26-June-2015
|
||||
* @brief This file provides a set of functions needed to manage the L3GD20,
|
||||
* ST MEMS motion sensor, 3-axis digital output gyroscope.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "l3gd20.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup L3GD20
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup L3GD20_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup L3GD20_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup L3GD20_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup L3GD20_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
GYRO_DrvTypeDef L3gd20Drv =
|
||||
{
|
||||
L3GD20_Init,
|
||||
L3GD20_DeInit,
|
||||
L3GD20_ReadID,
|
||||
L3GD20_RebootCmd,
|
||||
L3GD20_LowPower,
|
||||
L3GD20_INT1InterruptConfig,
|
||||
L3GD20_EnableIT,
|
||||
L3GD20_DisableIT,
|
||||
0,
|
||||
0,
|
||||
L3GD20_FilterConfig,
|
||||
L3GD20_FilterCmd,
|
||||
L3GD20_ReadXYZAngRate
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup L3GD20_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup L3GD20_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set L3GD20 Initialization.
|
||||
* @param L3GD20_InitStruct: pointer to a L3GD20_InitTypeDef structure
|
||||
* that contains the configuration setting for the L3GD20.
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_Init(uint16_t InitStruct)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Configure the low level interface */
|
||||
GYRO_IO_Init();
|
||||
|
||||
/* Write value to MEMS CTRL_REG1 register */
|
||||
ctrl = (uint8_t) InitStruct;
|
||||
GYRO_IO_Write(&ctrl, L3GD20_CTRL_REG1_ADDR, 1);
|
||||
|
||||
/* Write value to MEMS CTRL_REG4 register */
|
||||
ctrl = (uint8_t) (InitStruct >> 8);
|
||||
GYRO_IO_Write(&ctrl, L3GD20_CTRL_REG4_ADDR, 1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief L3GD20 De-initialization
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_DeInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read ID address of L3GD20
|
||||
* @param None
|
||||
* @retval ID name
|
||||
*/
|
||||
uint8_t L3GD20_ReadID(void)
|
||||
{
|
||||
uint8_t tmp;
|
||||
|
||||
/* Configure the low level interface */
|
||||
GYRO_IO_Init();
|
||||
|
||||
/* Read WHO I AM register */
|
||||
GYRO_IO_Read(&tmp, L3GD20_WHO_AM_I_ADDR, 1);
|
||||
|
||||
/* Return the ID */
|
||||
return (uint8_t)tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reboot memory content of L3GD20
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_RebootCmd(void)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG5 register */
|
||||
GYRO_IO_Read(&tmpreg, L3GD20_CTRL_REG5_ADDR, 1);
|
||||
|
||||
/* Enable or Disable the reboot memory */
|
||||
tmpreg |= L3GD20_BOOT_REBOOTMEMORY;
|
||||
|
||||
/* Write value to MEMS CTRL_REG5 register */
|
||||
GYRO_IO_Write(&tmpreg, L3GD20_CTRL_REG5_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set L3GD20 in low-power mode
|
||||
* @param
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_LowPower(uint16_t InitStruct)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Write value to MEMS CTRL_REG1 register */
|
||||
ctrl = (uint8_t) InitStruct;
|
||||
GYRO_IO_Write(&ctrl, L3GD20_CTRL_REG1_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set L3GD20 Interrupt INT1 configuration
|
||||
* @param Int1Config: the configuration setting for the L3GD20 Interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_INT1InterruptConfig(uint16_t Int1Config)
|
||||
{
|
||||
uint8_t ctrl_cfr = 0x00, ctrl3 = 0x00;
|
||||
|
||||
/* Read INT1_CFG register */
|
||||
GYRO_IO_Read(&ctrl_cfr, L3GD20_INT1_CFG_ADDR, 1);
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
GYRO_IO_Read(&ctrl3, L3GD20_CTRL_REG3_ADDR, 1);
|
||||
|
||||
ctrl_cfr &= 0x80;
|
||||
ctrl_cfr |= ((uint8_t) Int1Config >> 8);
|
||||
|
||||
ctrl3 &= 0xDF;
|
||||
ctrl3 |= ((uint8_t) Int1Config);
|
||||
|
||||
/* Write value to MEMS INT1_CFG register */
|
||||
GYRO_IO_Write(&ctrl_cfr, L3GD20_INT1_CFG_ADDR, 1);
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
GYRO_IO_Write(&ctrl3, L3GD20_CTRL_REG3_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable INT1 or INT2 interrupt
|
||||
* @param IntSel: choice of INT1 or INT2
|
||||
* This parameter can be:
|
||||
* @arg L3GD20_INT1
|
||||
* @arg L3GD20_INT2
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_EnableIT(uint8_t IntSel)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
GYRO_IO_Read(&tmpreg, L3GD20_CTRL_REG3_ADDR, 1);
|
||||
|
||||
if(IntSel == L3GD20_INT1)
|
||||
{
|
||||
tmpreg &= 0x7F;
|
||||
tmpreg |= L3GD20_INT1INTERRUPT_ENABLE;
|
||||
}
|
||||
else if(IntSel == L3GD20_INT2)
|
||||
{
|
||||
tmpreg &= 0xF7;
|
||||
tmpreg |= L3GD20_INT2INTERRUPT_ENABLE;
|
||||
}
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
GYRO_IO_Write(&tmpreg, L3GD20_CTRL_REG3_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable INT1 or INT2 interrupt
|
||||
* @param IntSel: choice of INT1 or INT2
|
||||
* This parameter can be:
|
||||
* @arg L3GD20_INT1
|
||||
* @arg L3GD20_INT2
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_DisableIT(uint8_t IntSel)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
GYRO_IO_Read(&tmpreg, L3GD20_CTRL_REG3_ADDR, 1);
|
||||
|
||||
if(IntSel == L3GD20_INT1)
|
||||
{
|
||||
tmpreg &= 0x7F;
|
||||
tmpreg |= L3GD20_INT1INTERRUPT_DISABLE;
|
||||
}
|
||||
else if(IntSel == L3GD20_INT2)
|
||||
{
|
||||
tmpreg &= 0xF7;
|
||||
tmpreg |= L3GD20_INT2INTERRUPT_DISABLE;
|
||||
}
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
GYRO_IO_Write(&tmpreg, L3GD20_CTRL_REG3_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set High Pass Filter Modality
|
||||
* @param FilterStruct: contains the configuration setting for the L3GD20.
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_FilterConfig(uint8_t FilterStruct)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
GYRO_IO_Read(&tmpreg, L3GD20_CTRL_REG2_ADDR, 1);
|
||||
|
||||
tmpreg &= 0xC0;
|
||||
|
||||
/* Configure MEMS: mode and cutoff frequency */
|
||||
tmpreg |= FilterStruct;
|
||||
|
||||
/* Write value to MEMS CTRL_REG2 register */
|
||||
GYRO_IO_Write(&tmpreg, L3GD20_CTRL_REG2_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable High Pass Filter
|
||||
* @param HighPassFilterState: new state of the High Pass Filter feature.
|
||||
* This parameter can be:
|
||||
* @arg: L3GD20_HIGHPASSFILTER_DISABLE
|
||||
* @arg: L3GD20_HIGHPASSFILTER_ENABLE
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_FilterCmd(uint8_t HighPassFilterState)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG5 register */
|
||||
GYRO_IO_Read(&tmpreg, L3GD20_CTRL_REG5_ADDR, 1);
|
||||
|
||||
tmpreg &= 0xEF;
|
||||
|
||||
tmpreg |= HighPassFilterState;
|
||||
|
||||
/* Write value to MEMS CTRL_REG5 register */
|
||||
GYRO_IO_Write(&tmpreg, L3GD20_CTRL_REG5_ADDR, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get status for L3GD20 data
|
||||
* @param None
|
||||
* @retval Data status in a L3GD20 Data
|
||||
*/
|
||||
uint8_t L3GD20_GetDataStatus(void)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read STATUS_REG register */
|
||||
GYRO_IO_Read(&tmpreg, L3GD20_STATUS_REG_ADDR, 1);
|
||||
|
||||
return tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Calculate the L3GD20 angular data.
|
||||
* @param pfData: Data out pointer
|
||||
* @retval None
|
||||
*/
|
||||
void L3GD20_ReadXYZAngRate(float *pfData)
|
||||
{
|
||||
uint8_t tmpbuffer[6] ={0};
|
||||
int16_t RawData[3] = {0};
|
||||
uint8_t tmpreg = 0;
|
||||
float sensitivity = 0;
|
||||
int i =0;
|
||||
|
||||
GYRO_IO_Read(&tmpreg,L3GD20_CTRL_REG4_ADDR,1);
|
||||
|
||||
GYRO_IO_Read(tmpbuffer,L3GD20_OUT_X_L_ADDR,6);
|
||||
|
||||
/* check in the control register 4 the data alignment (Big Endian or Little Endian)*/
|
||||
if(!(tmpreg & L3GD20_BLE_MSB))
|
||||
{
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
RawData[i]=(int16_t)(((uint16_t)tmpbuffer[2*i+1] << 8) + tmpbuffer[2*i]);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
RawData[i]=(int16_t)(((uint16_t)tmpbuffer[2*i] << 8) + tmpbuffer[2*i+1]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch the sensitivity value set in the CRTL4 */
|
||||
switch(tmpreg & L3GD20_FULLSCALE_SELECTION)
|
||||
{
|
||||
case L3GD20_FULLSCALE_250:
|
||||
sensitivity=L3GD20_SENSITIVITY_250DPS;
|
||||
break;
|
||||
|
||||
case L3GD20_FULLSCALE_500:
|
||||
sensitivity=L3GD20_SENSITIVITY_500DPS;
|
||||
break;
|
||||
|
||||
case L3GD20_FULLSCALE_2000:
|
||||
sensitivity=L3GD20_SENSITIVITY_2000DPS;
|
||||
break;
|
||||
}
|
||||
/* Divide by sensitivity */
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
pfData[i]=(float)(RawData[i] * sensitivity);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,324 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file l3gd20.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 26-June-2015
|
||||
* @brief This file contains all the functions prototypes for the l3gd20.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __L3GD20_H
|
||||
#define __L3GD20_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "../Common/gyro.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup L3GD20
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup L3GD20_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** START REGISTER MAPPING **************************/
|
||||
/******************************************************************************/
|
||||
#define L3GD20_WHO_AM_I_ADDR 0x0F /* device identification register */
|
||||
#define L3GD20_CTRL_REG1_ADDR 0x20 /* Control register 1 */
|
||||
#define L3GD20_CTRL_REG2_ADDR 0x21 /* Control register 2 */
|
||||
#define L3GD20_CTRL_REG3_ADDR 0x22 /* Control register 3 */
|
||||
#define L3GD20_CTRL_REG4_ADDR 0x23 /* Control register 4 */
|
||||
#define L3GD20_CTRL_REG5_ADDR 0x24 /* Control register 5 */
|
||||
#define L3GD20_REFERENCE_REG_ADDR 0x25 /* Reference register */
|
||||
#define L3GD20_OUT_TEMP_ADDR 0x26 /* Out temp register */
|
||||
#define L3GD20_STATUS_REG_ADDR 0x27 /* Status register */
|
||||
#define L3GD20_OUT_X_L_ADDR 0x28 /* Output Register X */
|
||||
#define L3GD20_OUT_X_H_ADDR 0x29 /* Output Register X */
|
||||
#define L3GD20_OUT_Y_L_ADDR 0x2A /* Output Register Y */
|
||||
#define L3GD20_OUT_Y_H_ADDR 0x2B /* Output Register Y */
|
||||
#define L3GD20_OUT_Z_L_ADDR 0x2C /* Output Register Z */
|
||||
#define L3GD20_OUT_Z_H_ADDR 0x2D /* Output Register Z */
|
||||
#define L3GD20_FIFO_CTRL_REG_ADDR 0x2E /* Fifo control Register */
|
||||
#define L3GD20_FIFO_SRC_REG_ADDR 0x2F /* Fifo src Register */
|
||||
|
||||
#define L3GD20_INT1_CFG_ADDR 0x30 /* Interrupt 1 configuration Register */
|
||||
#define L3GD20_INT1_SRC_ADDR 0x31 /* Interrupt 1 source Register */
|
||||
#define L3GD20_INT1_TSH_XH_ADDR 0x32 /* Interrupt 1 Threshold X register */
|
||||
#define L3GD20_INT1_TSH_XL_ADDR 0x33 /* Interrupt 1 Threshold X register */
|
||||
#define L3GD20_INT1_TSH_YH_ADDR 0x34 /* Interrupt 1 Threshold Y register */
|
||||
#define L3GD20_INT1_TSH_YL_ADDR 0x35 /* Interrupt 1 Threshold Y register */
|
||||
#define L3GD20_INT1_TSH_ZH_ADDR 0x36 /* Interrupt 1 Threshold Z register */
|
||||
#define L3GD20_INT1_TSH_ZL_ADDR 0x37 /* Interrupt 1 Threshold Z register */
|
||||
#define L3GD20_INT1_DURATION_ADDR 0x38 /* Interrupt 1 DURATION register */
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** END REGISTER MAPPING ***************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define I_AM_L3GD20 ((uint8_t)0xD4)
|
||||
#define I_AM_L3GD20_TR ((uint8_t)0xD5)
|
||||
|
||||
/** @defgroup Power_Mode_selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_MODE_POWERDOWN ((uint8_t)0x00)
|
||||
#define L3GD20_MODE_ACTIVE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OutPut_DataRate_Selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_OUTPUT_DATARATE_1 ((uint8_t)0x00)
|
||||
#define L3GD20_OUTPUT_DATARATE_2 ((uint8_t)0x40)
|
||||
#define L3GD20_OUTPUT_DATARATE_3 ((uint8_t)0x80)
|
||||
#define L3GD20_OUTPUT_DATARATE_4 ((uint8_t)0xC0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Axes_Selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_X_ENABLE ((uint8_t)0x02)
|
||||
#define L3GD20_Y_ENABLE ((uint8_t)0x01)
|
||||
#define L3GD20_Z_ENABLE ((uint8_t)0x04)
|
||||
#define L3GD20_AXES_ENABLE ((uint8_t)0x07)
|
||||
#define L3GD20_AXES_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bandwidth_Selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_BANDWIDTH_1 ((uint8_t)0x00)
|
||||
#define L3GD20_BANDWIDTH_2 ((uint8_t)0x10)
|
||||
#define L3GD20_BANDWIDTH_3 ((uint8_t)0x20)
|
||||
#define L3GD20_BANDWIDTH_4 ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Full_Scale_Selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_FULLSCALE_250 ((uint8_t)0x00)
|
||||
#define L3GD20_FULLSCALE_500 ((uint8_t)0x10)
|
||||
#define L3GD20_FULLSCALE_2000 ((uint8_t)0x20)
|
||||
#define L3GD20_FULLSCALE_SELECTION ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Full_Scale_Sensitivity
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_SENSITIVITY_250DPS ((float)8.75f) /*!< gyroscope sensitivity with 250 dps full scale [DPS/LSB] */
|
||||
#define L3GD20_SENSITIVITY_500DPS ((float)17.50f) /*!< gyroscope sensitivity with 500 dps full scale [DPS/LSB] */
|
||||
#define L3GD20_SENSITIVITY_2000DPS ((float)70.00f) /*!< gyroscope sensitivity with 2000 dps full scale [DPS/LSB] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup Block_Data_Update
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_BlockDataUpdate_Continous ((uint8_t)0x00)
|
||||
#define L3GD20_BlockDataUpdate_Single ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Endian_Data_selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_BLE_LSB ((uint8_t)0x00)
|
||||
#define L3GD20_BLE_MSB ((uint8_t)0x40)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup High_Pass_Filter_status
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_HIGHPASSFILTER_DISABLE ((uint8_t)0x00)
|
||||
#define L3GD20_HIGHPASSFILTER_ENABLE ((uint8_t)0x10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT1_INT2_selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_INT1 ((uint8_t)0x00)
|
||||
#define L3GD20_INT2 ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT1_Interrupt_status
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_INT1INTERRUPT_DISABLE ((uint8_t)0x00)
|
||||
#define L3GD20_INT1INTERRUPT_ENABLE ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT2_Interrupt_status
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_INT2INTERRUPT_DISABLE ((uint8_t)0x00)
|
||||
#define L3GD20_INT2INTERRUPT_ENABLE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup INT1_Interrupt_ActiveEdge
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_INT1INTERRUPT_LOW_EDGE ((uint8_t)0x20)
|
||||
#define L3GD20_INT1INTERRUPT_HIGH_EDGE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Boot_Mode_selection
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_BOOT_NORMALMODE ((uint8_t)0x00)
|
||||
#define L3GD20_BOOT_REBOOTMEMORY ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup High_Pass_Filter_Mode
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_HPM_NORMAL_MODE_RES ((uint8_t)0x00)
|
||||
#define L3GD20_HPM_REF_SIGNAL ((uint8_t)0x10)
|
||||
#define L3GD20_HPM_NORMAL_MODE ((uint8_t)0x20)
|
||||
#define L3GD20_HPM_AUTORESET_INT ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup High_Pass_CUT OFF_Frequency
|
||||
* @{
|
||||
*/
|
||||
#define L3GD20_HPFCF_0 0x00
|
||||
#define L3GD20_HPFCF_1 0x01
|
||||
#define L3GD20_HPFCF_2 0x02
|
||||
#define L3GD20_HPFCF_3 0x03
|
||||
#define L3GD20_HPFCF_4 0x04
|
||||
#define L3GD20_HPFCF_5 0x05
|
||||
#define L3GD20_HPFCF_6 0x06
|
||||
#define L3GD20_HPFCF_7 0x07
|
||||
#define L3GD20_HPFCF_8 0x08
|
||||
#define L3GD20_HPFCF_9 0x09
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup L3GD20_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Sensor Configuration Functions */
|
||||
void L3GD20_Init(uint16_t InitStruct);
|
||||
void L3GD20_DeInit(void);
|
||||
void L3GD20_LowPower(uint16_t InitStruct);
|
||||
uint8_t L3GD20_ReadID(void);
|
||||
void L3GD20_RebootCmd(void);
|
||||
|
||||
/* Interrupt Configuration Functions */
|
||||
void L3GD20_INT1InterruptConfig(uint16_t Int1Config);
|
||||
void L3GD20_EnableIT(uint8_t IntSel);
|
||||
void L3GD20_DisableIT(uint8_t IntSel);
|
||||
|
||||
/* High Pass Filter Configuration Functions */
|
||||
void L3GD20_FilterConfig(uint8_t FilterStruct);
|
||||
void L3GD20_FilterCmd(uint8_t HighPassFilterState);
|
||||
void L3GD20_ReadXYZAngRate(float *pfData);
|
||||
uint8_t L3GD20_GetDataStatus(void);
|
||||
|
||||
/* Gyroscope IO functions */
|
||||
void GYRO_IO_Init(void);
|
||||
void GYRO_IO_DeInit(void);
|
||||
void GYRO_IO_Write(uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
|
||||
void GYRO_IO_Read(uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);
|
||||
|
||||
/* Gyroscope driver structure */
|
||||
extern GYRO_DrvTypeDef L3gd20Drv;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __L3GD20_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,227 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
||||
|
||||
|
||||
|
||||
|
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|
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|
||||
|
||||
|
||||
|
||||
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
|
||||
|
||||
|
||||
<link rel="File-List" href="Library_files/filelist.xml">
|
||||
|
||||
|
||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for LSM303DLHC Component Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{mso-style-parent:"";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
h2
|
||||
{mso-style-next:Normal;
|
||||
margin-top:12.0pt;
|
||||
margin-right:0in;
|
||||
margin-bottom:3.0pt;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
|
||||
font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
font-weight:bold;
|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
a:visited, span.MsoHyperlinkFollowed
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
p
|
||||
{mso-margin-top-alt:auto;
|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
@page Section1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
|
||||
<meta content="MCD Application Team" name="author"></head>
|
||||
<body link="blue" vlink="blue">
|
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<div class="Section1">
|
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<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
||||
</o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="vertical-align: top;">
|
||||
<p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for LSM303AGR Component Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
||||
2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
<tr style="">
|
||||
<td class="MsoNormal" style="padding: 0cm;" valign="top"><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 09-November-2020 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes</span></u></b></p><ul style="list-style-type: square;"><li><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 10pt; font-family: Verdana;">Remove extra comment.</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 10-October-2016 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
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|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Arial; color: white;"><o:p></o:p></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:</span><br>
|
||||
</font>
|
||||
<ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
||||
in binary form must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
|
||||
</font>
|
||||
</li></ol>
|
||||
<font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";"></span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
|
||||
|
||||
</div>
|
||||
|
||||
<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
|
||||
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<div style="margin-left: 160px;"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span></div>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
|
||||
</body></html>
|
||||
@@ -0,0 +1,628 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file lsm303agr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 10-October-2016
|
||||
* @brief This file provides a set of functions needed to manage the lsm303agr
|
||||
* MEMS accelerometer.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "lsm303agr.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LSM303AGR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303AGR_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303AGR_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303AGR_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303AGR_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
ACCELERO_DrvTypeDef Lsm303agrDrv =
|
||||
{
|
||||
LSM303AGR_AccInit,
|
||||
LSM303AGR_AccDeInit,
|
||||
LSM303AGR_AccReadID,
|
||||
LSM303AGR_AccRebootCmd,
|
||||
0,
|
||||
LSM303AGR_AccZClickITConfig,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
LSM303AGR_AccFilterConfig,
|
||||
LSM303AGR_AccFilterCmd,
|
||||
LSM303AGR_AccReadXYZ
|
||||
};
|
||||
|
||||
uint8_t tmpreg2A[8] = {0x00};
|
||||
uint8_t tmpreg3A = 0x00;
|
||||
uint8_t tmpregcfgA = 0x00;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303AGR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set LSM303AGR Initialization.
|
||||
* @param InitStruct: Init parameters
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccInit(uint16_t InitStruct)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Low level init */
|
||||
COMPASSACCELERO_IO_Init();
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG1 register */
|
||||
ctrl = (uint8_t) InitStruct;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG1_A, ctrl);
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG4 register */
|
||||
ctrl = (uint8_t) (InitStruct << 8);
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG4_A, ctrl);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LSM303AGR De-initialization.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccDeInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read LSM303AGR ID.
|
||||
* @param None
|
||||
* @retval ID
|
||||
*/
|
||||
uint8_t LSM303AGR_AccReadID(void)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Low level init */
|
||||
COMPASSACCELERO_IO_Init();
|
||||
|
||||
/* Read value at Who am I register address */
|
||||
ctrl = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_WHO_AM_I_ADDR);
|
||||
|
||||
return ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reboot memory content of LSM303AGR
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccRebootCmd(void)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG5 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG5_A);
|
||||
|
||||
/* Enable or Disable the reboot memory */
|
||||
tmpreg |= LSM303AGR_BOOT_REBOOTMEMORY;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG5 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG5_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set High Pass Filter Modality
|
||||
* @param FilterStruct: contains data for filter config
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccFilterConfig(uint8_t FilterStruct)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG2_A);
|
||||
|
||||
tmpreg &= 0x0C;
|
||||
tmpreg |= FilterStruct;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG2 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG2_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable High Pass Filter
|
||||
* @param HighPassFilterState: new state of the High Pass Filter feature.
|
||||
* This parameter can be:
|
||||
* @arg: LSM303AGR_HIGHPASSFILTER_DISABLE
|
||||
* @arg: LSM303AGR_HIGHPASSFILTER_ENABLE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccFilterCmd(uint8_t HighPassFilterState)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG2_A);
|
||||
|
||||
tmpreg &= 0xF7;
|
||||
|
||||
tmpreg |= HighPassFilterState;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG2 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG2_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read X, Y & Z Acceleration values
|
||||
* @param pData: Data out pointer
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccReadXYZ(int16_t* pData)
|
||||
{
|
||||
int16_t pnRawData[3];
|
||||
uint8_t ctrlx[2]={0,0};
|
||||
int8_t buffer[6];
|
||||
uint8_t i = 0;
|
||||
uint8_t sensitivity = LSM303AGR_ACC_SENSITIVITY_2G;
|
||||
|
||||
/* Read the acceleration control register content */
|
||||
ctrlx[0] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG4_A);
|
||||
ctrlx[1] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG5_A);
|
||||
|
||||
/* Read output register X, Y & Z acceleration */
|
||||
buffer[0] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_OUT_X_L_A);
|
||||
buffer[1] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_OUT_X_H_A);
|
||||
buffer[2] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_OUT_Y_L_A);
|
||||
buffer[3] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_OUT_Y_H_A);
|
||||
buffer[4] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_OUT_Z_L_A);
|
||||
buffer[5] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_OUT_Z_H_A);
|
||||
|
||||
/* Check in the control register4 the data alignment*/
|
||||
if(!(ctrlx[0] & LSM303AGR_BLE_MSB))
|
||||
{
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
pnRawData[i]=((int16_t)((uint16_t)buffer[2*i+1] << 8) + buffer[2*i]);
|
||||
}
|
||||
}
|
||||
else /* Big Endian Mode */
|
||||
{
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
pnRawData[i]=((int16_t)((uint16_t)buffer[2*i] << 8) + buffer[2*i+1]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Normal mode */
|
||||
/* Switch the sensitivity value set in the CRTL4 */
|
||||
switch(ctrlx[0] & LSM303AGR_FULLSCALE_16G)
|
||||
{
|
||||
case LSM303AGR_FULLSCALE_2G:
|
||||
sensitivity = LSM303AGR_ACC_SENSITIVITY_2G;
|
||||
break;
|
||||
case LSM303AGR_FULLSCALE_4G:
|
||||
sensitivity = LSM303AGR_ACC_SENSITIVITY_4G;
|
||||
break;
|
||||
case LSM303AGR_FULLSCALE_8G:
|
||||
sensitivity = LSM303AGR_ACC_SENSITIVITY_8G;
|
||||
break;
|
||||
case LSM303AGR_FULLSCALE_16G:
|
||||
sensitivity = LSM303AGR_ACC_SENSITIVITY_16G;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Obtain the mg value for the three axis */
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
pData[i]=(pnRawData[i] * sensitivity);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable High Pass Filter on CLick
|
||||
* @param HighPassFilterState: new state of the High Pass Filter feature.
|
||||
* This parameter can be:
|
||||
* @arg: LSM303AGR_HPF_CLICK_DISABLE
|
||||
* @arg: LSM303AGR_HPF_CLICK_ENABLE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccFilterClickCmd(uint8_t HighPassFilterClickState)
|
||||
{
|
||||
uint8_t tmpreg = 0x00;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG2_A);
|
||||
|
||||
tmpreg &= ~(LSM303AGR_HPF_CLICK_ENABLE);
|
||||
|
||||
tmpreg |= HighPassFilterClickState;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG2 regsister */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG2_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable LSM303AGR Interrupt1
|
||||
* @param LSM303AGR_IT: specifies the LSM303AGR interrupt source to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303AGR_IT1_CLICK
|
||||
* @arg LSM303AGR_IT1_AOI1
|
||||
* @arg LSM303AGR_IT1_AOI2
|
||||
* @arg LSM303AGR_IT1_DRY1
|
||||
* @arg LSM303AGR_IT1_DRY2
|
||||
* @arg LSM303AGR_IT1_WTM
|
||||
* @arg LSM303AGR_IT1_OVERRUN
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccIT1Enable(uint8_t LSM303AGR_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG3_A);
|
||||
|
||||
/* Enable IT1 */
|
||||
tmpval |= LSM303AGR_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG3_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable LSM303AGR Interrupt1
|
||||
* @param LSM303AGR_IT: specifies the LSM303AGR interrupt source to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303AGR_IT1_CLICK
|
||||
* @arg LSM303AGR_IT1_AOI1
|
||||
* @arg LSM303AGR_IT1_AOI2
|
||||
* @arg LSM303AGR_IT1_DRY1
|
||||
* @arg LSM303AGR_IT1_DRY2
|
||||
* @arg LSM303AGR_IT1_WTM
|
||||
* @arg LSM303AGR_IT1_OVERRUN
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccIT1Disable(uint8_t LSM303AGR_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG3_A);
|
||||
|
||||
/* Disable IT1 */
|
||||
tmpval &= ~LSM303AGR_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG3_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable LSM303AGR Interrupt2
|
||||
* @param LSM303AGR_IT: specifies the LSM303AGR interrupt source to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303AGR_IT2_CLICK
|
||||
* @arg LSM303AGR_IT2_INT1
|
||||
* @arg LSM303AGR_IT2_INT2
|
||||
* @arg LSM303AGR_IT2_BOOT
|
||||
* @arg LSM303AGR_IT2_ACT
|
||||
* @arg LSM303AGR_IT2_HLACTIVE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccIT2Enable(uint8_t LSM303AGR_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG6_A);
|
||||
|
||||
/* Enable IT2 */
|
||||
tmpval |= LSM303AGR_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG6_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable LSM303AGR Interrupt2
|
||||
* @param LSM303AGR_IT: specifies the LSM303AGR interrupt source to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303AGR_IT2_CLICK
|
||||
* @arg LSM303AGR_IT2_INT1
|
||||
* @arg LSM303AGR_IT2_INT2
|
||||
* @arg LSM303AGR_IT2_BOOT
|
||||
* @arg LSM303AGR_IT2_ACT
|
||||
* @arg LSM303AGR_IT2_HLACTIVE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccIT2Disable(uint8_t LSM303AGR_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG6_A);
|
||||
|
||||
/* Disable IT2 */
|
||||
tmpval &= ~LSM303AGR_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CTRL_REG6_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT1 interrupt enable
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: Axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccINT1InterruptEnable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT1_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_INT1_CFG_A);
|
||||
|
||||
/* Enable the selected interrupt */
|
||||
tmpval |= (ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT1_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_INT1_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT1 interrupt disable
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: Axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccINT1InterruptDisable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT1_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_INT1_CFG_A);
|
||||
|
||||
/* Disable the selected interrupt */
|
||||
tmpval &= ~(ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT1_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_INT1_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT2 interrupt enable
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccINT2InterruptEnable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT2_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_INT2_CFG_A);
|
||||
|
||||
/* Enable the selected interrupt */
|
||||
tmpval |= (ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT2_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_INT2_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT2 interrupt config
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccINT2InterruptDisable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT2_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_INT2_CFG_A);
|
||||
|
||||
/* Disable the selected interrupt */
|
||||
tmpval &= ~(ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT2_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_INT2_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Click interrupt enable
|
||||
* @param ITClick: the selected interrupt to enable
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccClickITEnable(uint8_t ITClick)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CLICK_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CLICK_CFG_A);
|
||||
|
||||
/* Enable the selected interrupt */
|
||||
tmpval |= ITClick;
|
||||
|
||||
/* Write value to MEMS CLICK CFG register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CLICK_CFG_A, tmpval);
|
||||
|
||||
/* Configure Click Threshold on Z axis */
|
||||
tmpval = 0x0A;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CLICK_THS_A, tmpval);
|
||||
|
||||
/* Configure Time Limit */
|
||||
tmpval = 0x05;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_TIME_LIMIT_A, tmpval);
|
||||
|
||||
/* Configure Latency */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_TIME_LATENCY_A, tmpval);
|
||||
|
||||
/* Configure Click Window */
|
||||
tmpval = 0x32;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_TIME_WINDOW_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Click interrupt disable
|
||||
* @param ITClick: the selected click interrupt to disable
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccClickITDisable(uint8_t ITClick)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CLICK_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303AGR_CLICK_CFG_A);
|
||||
|
||||
/* Disable the selected interrupt */
|
||||
tmpval &= ~ITClick;
|
||||
|
||||
/* Write value to MEMS CLICK_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303AGR_CLICK_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Click on Z axis interrupt config
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_AccZClickITConfig(void)
|
||||
{
|
||||
/* Configure low level IT config */
|
||||
COMPASSACCELERO_IO_ITConfig();
|
||||
|
||||
/* Select click IT as INT1 interrupt */
|
||||
LSM303AGR_AccIT1Enable(LSM303AGR_IT1_CLICK);
|
||||
|
||||
/* Enable High pass filter for click IT */
|
||||
LSM303AGR_AccFilterClickCmd(LSM303AGR_HPF_CLICK_ENABLE);
|
||||
|
||||
/* Enable simple click IT on Z axis, */
|
||||
LSM303AGR_AccClickITEnable(LSM303AGR_Z_SINGLE_CLICK);
|
||||
}
|
||||
|
||||
#ifdef MAGNET
|
||||
/**
|
||||
* @brief Set LSM303AGR Mag Initialization.
|
||||
* @param LSM303AGR_InitStruct: pointer to a LSM303AGR_MagInitTypeDef structure
|
||||
* that contains the configuration setting for the LSM303AGR.
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303AGR_MagInit(LSM303AGRMag_InitTypeDef *LSM303AGR_InitStruct)
|
||||
{
|
||||
uint8_t cra_regm = 0x00, crb_regm = 0x00, mr_regm = 0x00;
|
||||
|
||||
/* Configure MEMS: temp and Data rate */
|
||||
cra_regm |= (uint8_t) (LSM303AGR_InitStruct->Temperature_Sensor | LSM303AGR_InitStruct->MagOutput_DataRate);
|
||||
|
||||
/* Configure MEMS: full Scale */
|
||||
crb_regm |= (uint8_t) (LSM303AGR_InitStruct->MagFull_Scale);
|
||||
|
||||
/* Configure MEMS: working mode */
|
||||
mr_regm |= (uint8_t) (LSM303AGR_InitStruct->Working_Mode);
|
||||
|
||||
/* Write value to Mag MEMS CRA_REG register */
|
||||
COMPASSACCELERO_IO_Write(MAG_I2C_ADDRESS, LSM303AGR_CRA_REG_M, 1, &cra_regm);
|
||||
|
||||
/* Write value to Mag MEMS CRB_REG register */
|
||||
COMPASSACCELERO_IO_Write(MAG_I2C_ADDRESS, LSM303AGR_CRB_REG_M, 1, &crb_regm);
|
||||
|
||||
/* Write value to Mag MEMS MR_REG register */
|
||||
COMPASSACCELERO_IO_Write(MAG_I2C_ADDRESS, LSM303AGR_MR_REG_M, 1, &mr_regm);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get status for Mag LSM303AGR data
|
||||
* @param None
|
||||
* @retval Data status in a LSM303AGR Data register
|
||||
*/
|
||||
uint8_t LSM303AGR_MagGetDataStatus(void)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read Mag STATUS register */
|
||||
COMPASSACCELERO_IO_Read(MAG_I2C_ADDRESS, LSM303AGR_SR_REG_M, 1, &tmpreg);
|
||||
|
||||
return tmpreg;
|
||||
}
|
||||
#endif /* MAGNET */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,521 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file lsm303agr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.0
|
||||
* @date 10-October-2016
|
||||
* @brief This file contains all the functions prototypes for the lsm303agr.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __LSM303AGR_H
|
||||
#define __LSM303AGR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "../Common/accelero.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LSM303AGR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303AGR_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** START REGISTER MAPPING **************************/
|
||||
/******************************************************************************/
|
||||
/* Exported constant IO ------------------------------------------------------*/
|
||||
#define ACC_I2C_ADDRESS 0x32
|
||||
#define MAG_I2C_ADDRESS 0x3C
|
||||
|
||||
/* Temperature sensor Registers (New vs lsm303dlhc.h) */
|
||||
#define LSM303AGR_STATUS_REG_AUX_A 0x07 /* status register */
|
||||
#define LSM303AGR_OUT_TEMP_L_A 0x0C /* output temperature register */
|
||||
#define LSM303AGR_OUT_TEMP_H_A 0x0D /* output temperature register */
|
||||
#define LSM303AGR_IN_COUNTER_REG_A 0x0E /* register */
|
||||
/* Acceleration Registers */
|
||||
#define LSM303AGR_WHO_AM_I_ADDR 0x0F /* device identification register (0x33) */
|
||||
#define LSM303AGR_WHO_AM_I_A LSM303AGR_WHO_AM_I_ADDR
|
||||
/* Temperature sensor Registers (New vs lsm303dlhc.h) */
|
||||
#define LSM303AGR_TEMP_CFG_REG_A 0x1F /* temperature configuration register */
|
||||
/* Acceleration Registers */
|
||||
#define LSM303AGR_CTRL_REG1_A 0x20 /* Control register 1 acceleration */
|
||||
#define LSM303AGR_CTRL_REG2_A 0x21 /* Control register 2 acceleration */
|
||||
#define LSM303AGR_CTRL_REG3_A 0x22 /* Control register 3 acceleration */
|
||||
#define LSM303AGR_CTRL_REG4_A 0x23 /* Control register 4 acceleration */
|
||||
#define LSM303AGR_CTRL_REG5_A 0x24 /* Control register 5 acceleration */
|
||||
#define LSM303AGR_CTRL_REG6_A 0x25 /* Control register 6 acceleration */
|
||||
#define LSM303AGR_REFERENCE_A 0x26 /* Reference register acceleration */
|
||||
#define LSM303AGR_STATUS_REG_A 0x27 /* Status register acceleration */
|
||||
#define LSM303AGR_OUT_X_L_A 0x28 /* Output Register X acceleration */
|
||||
#define LSM303AGR_OUT_X_H_A 0x29 /* Output Register X acceleration */
|
||||
#define LSM303AGR_OUT_Y_L_A 0x2A /* Output Register Y acceleration */
|
||||
#define LSM303AGR_OUT_Y_H_A 0x2B /* Output Register Y acceleration */
|
||||
#define LSM303AGR_OUT_Z_L_A 0x2C /* Output Register Z acceleration */
|
||||
#define LSM303AGR_OUT_Z_H_A 0x2D /* Output Register Z acceleration */
|
||||
#define LSM303AGR_FIFO_CTRL_REG_A 0x2E /* Fifo control Register acceleration */
|
||||
#define LSM303AGR_FIFO_SRC_REG_A 0x2F /* Fifo src Register acceleration */
|
||||
|
||||
#define LSM303AGR_INT1_CFG_A 0x30 /* Interrupt 1 configuration Register acceleration */
|
||||
#define LSM303AGR_INT1_SOURCE_A 0x31 /* Interrupt 1 source Register acceleration */
|
||||
#define LSM303AGR_INT1_THS_A 0x32 /* Interrupt 1 Threshold register acceleration */
|
||||
#define LSM303AGR_INT1_DURATION_A 0x33 /* Interrupt 1 DURATION register acceleration */
|
||||
|
||||
#define LSM303AGR_INT2_CFG_A 0x34 /* Interrupt 2 configuration Register acceleration */
|
||||
#define LSM303AGR_INT2_SOURCE_A 0x35 /* Interrupt 2 source Register acceleration */
|
||||
#define LSM303AGR_INT2_THS_A 0x36 /* Interrupt 2 Threshold register acceleration */
|
||||
#define LSM303AGR_INT2_DURATION_A 0x37 /* Interrupt 2 DURATION register acceleration */
|
||||
|
||||
#define LSM303AGR_CLICK_CFG_A 0x38 /* Click configuration Register acceleration */
|
||||
#define LSM303AGR_CLICK_SOURCE_A 0x39 /* Click 2 source Register acceleration */
|
||||
#define LSM303AGR_CLICK_THS_A 0x3A /* Click 2 Threshold register acceleration */
|
||||
|
||||
#define LSM303AGR_TIME_LIMIT_A 0x3B /* Time Limit Register acceleration */
|
||||
#define LSM303AGR_TIME_LATENCY_A 0x3C /* Time Latency Register acceleration */
|
||||
#define LSM303AGR_TIME_WINDOW_A 0x3D /* Time window register acceleration */
|
||||
|
||||
/* System Registers(New vs lsm303dlhc.h) */
|
||||
#define LSM303AGR_Act_THS_A 0x3E /* return to sleep activation threshold register */
|
||||
#define LSM303AGR_Act_DUR_A 0x3F /* return to sleep duration register */
|
||||
/* Magnetometer */
|
||||
#define LSM303AGR_X_REG_L_M 0x45 /* Hard-iron X magnetic field */
|
||||
#define LSM303AGR_X_REG_H_M 0x46 /* Hard-iron X magnetic field */
|
||||
#define LSM303AGR_Y_REG_L_M 0x47 /* Hard-iron Y magnetic field */
|
||||
#define LSM303AGR_Y_REG_H_M 0x48 /* Hard-iron Y magnetic field */
|
||||
#define LSM303AGR_Z_REG_L_M 0x49 /* Hard-iron Z magnetic field */
|
||||
#define LSM303AGR_Z_REH_H_M 0x4A /* Hard-iron Z magnetic field */
|
||||
#define LSM303AGR_WHO_AM_I_M 0x4F /* Who am i register magnetic field (0x40) */
|
||||
#define LSM303AGR_CFG_REG_A_M 0x60 /* Configuration register A magnetic field */
|
||||
#define LSM303AGR_CFG_REG_B_M 0x61 /* Configuration register B magnetic field */
|
||||
#define LSM303AGR_CFG_REG_C_M 0x62 /* Configuration register C magnetic field */
|
||||
#define LSM303AGR_INT_CTRL_REG_M 0x63 /* interrupt control register magnetic field */
|
||||
#define LSM303AGR_INT_SOURCE_REG_M 0x64 /* interrupt source register magnetic field */
|
||||
#define LSM303AGR_INT_THS_L_REG_M 0x65 /* interrupt threshold register magnetic field */
|
||||
#define LSM303AGR_INT_THS_H_REG_M 0x66 /* interrupt threshold register magnetic field*/
|
||||
#define LSM303AGR_STATUS_REG_M 0x67 /* Status Register magnetic field */
|
||||
#define LSM303AGR_OUTX_L_REG_M 0x68 /* Output Register X magnetic field */
|
||||
#define LSM303AGR_OUTX_H_REG_M 0x69 /* Output Register X magnetic field */
|
||||
#define LSM303AGR_OUTY_L_REG_M 0x6A /* Output Register X magnetic field */
|
||||
#define LSM303AGR_OUTY_H_REG_M 0x6B /* Output Register X magnetic field */
|
||||
#define LSM303AGR_OUTZ_L_REG_M 0x6C /* Output Register X magnetic field */
|
||||
#define LSM303AGR_OUTZ_H_REG_M 0x6D /* Output Register X magnetic field */
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** END REGISTER MAPPING ***************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define I_AM_LSM303AGR ((uint8_t)0x33)
|
||||
|
||||
/** @defgroup Acc_Power_Mode_selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_NORMAL_MODE ((uint8_t)0x00)
|
||||
#define LSM303AGR_LOWPOWER_MODE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_OutPut_DataRate_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_ODR_1_HZ ((uint8_t)0x10) /*!< Output Data Rate = 1 Hz */
|
||||
#define LSM303AGR_ODR_10_HZ ((uint8_t)0x20) /*!< Output Data Rate = 10 Hz */
|
||||
#define LSM303AGR_ODR_25_HZ ((uint8_t)0x30) /*!< Output Data Rate = 25 Hz */
|
||||
#define LSM303AGR_ODR_50_HZ ((uint8_t)0x40) /*!< Output Data Rate = 50 Hz */
|
||||
#define LSM303AGR_ODR_100_HZ ((uint8_t)0x50) /*!< Output Data Rate = 100 Hz */
|
||||
#define LSM303AGR_ODR_200_HZ ((uint8_t)0x60) /*!< Output Data Rate = 200 Hz */
|
||||
#define LSM303AGR_ODR_400_HZ ((uint8_t)0x70) /*!< Output Data Rate = 400 Hz */
|
||||
#define LSM303AGR_ODR_1620_HZ_LP ((uint8_t)0x80) /*!< Output Data Rate = 1620 Hz only in Low Power Mode */
|
||||
#define LSM303AGR_ODR_1344_HZ ((uint8_t)0x90) /*!< Output Data Rate = 1344 Hz in Normal mode and 5376 Hz in Low Power Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Axes_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_X_ENABLE ((uint8_t)0x01)
|
||||
#define LSM303AGR_Y_ENABLE ((uint8_t)0x02)
|
||||
#define LSM303AGR_Z_ENABLE ((uint8_t)0x04)
|
||||
#define LSM303AGR_AXES_ENABLE ((uint8_t)0x07)
|
||||
#define LSM303AGR_AXES_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Resolution
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_HR_ENABLE ((uint8_t)0x08)
|
||||
#define LSM303AGR_HR_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Full_Scale_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_FULLSCALE_2G ((uint8_t)0x00) /*!< <20>2 g */
|
||||
#define LSM303AGR_FULLSCALE_4G ((uint8_t)0x10) /*!< <20>4 g */
|
||||
#define LSM303AGR_FULLSCALE_8G ((uint8_t)0x20) /*!< <20>8 g */
|
||||
#define LSM303AGR_FULLSCALE_16G ((uint8_t)0x30) /*!< <20>16 g */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Full_Scale_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_ACC_SENSITIVITY_2G ((uint8_t)1) /*!< accelerometer sensitivity with 2 g full scale [mg/LSB] */
|
||||
#define LSM303AGR_ACC_SENSITIVITY_4G ((uint8_t)2) /*!< accelerometer sensitivity with 4 g full scale [mg/LSB] */
|
||||
#define LSM303AGR_ACC_SENSITIVITY_8G ((uint8_t)4) /*!< accelerometer sensitivity with 8 g full scale [mg/LSB] */
|
||||
#define LSM303AGR_ACC_SENSITIVITY_16G ((uint8_t)12) /*!< accelerometer sensitivity with 12 g full scale [mg/LSB] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Block_Data_Update
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_BlockUpdate_Continous ((uint8_t)0x00) /*!< Continuos Update */
|
||||
#define LSM303AGR_BlockUpdate_Single ((uint8_t)0x80) /*!< Single Update: output registers not updated until MSB and LSB reading */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Endian_Data_selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_BLE_LSB ((uint8_t)0x00) /*!< Little Endian: data LSB @ lower address */
|
||||
#define LSM303AGR_BLE_MSB ((uint8_t)0x40) /*!< Big Endian: data MSB @ lower address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Boot_Mode_selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_BOOT_NORMALMODE ((uint8_t)0x00)
|
||||
#define LSM303AGR_BOOT_REBOOTMEMORY ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_Mode
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_HPM_NORMAL_MODE_RES ((uint8_t)0x00)
|
||||
#define LSM303AGR_HPM_REF_SIGNAL ((uint8_t)0x40)
|
||||
#define LSM303AGR_HPM_NORMAL_MODE ((uint8_t)0x80)
|
||||
#define LSM303AGR_HPM_AUTORESET_INT ((uint8_t)0xC0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_CUT OFF_Frequency
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_HPFCF_8 ((uint8_t)0x00)
|
||||
#define LSM303AGR_HPFCF_16 ((uint8_t)0x10)
|
||||
#define LSM303AGR_HPFCF_32 ((uint8_t)0x20)
|
||||
#define LSM303AGR_HPFCF_64 ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_HIGHPASSFILTER_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303AGR_HIGHPASSFILTER_ENABLE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_Click_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_HPF_CLICK_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303AGR_HPF_CLICK_ENABLE ((uint8_t)0x04)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_AOI1_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_HPF_AOI1_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303AGR_HPF_AOI1_ENABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_AOI2_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_HPF_AOI2_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303AGR_HPF_AOI2_ENABLE ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Interrupt1_Configuration_definition
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_IT1_CLICK ((uint8_t)0x80)
|
||||
#define LSM303AGR_IT1_AOI1 ((uint8_t)0x40)
|
||||
#define LSM303AGR_IT1_AOI2 ((uint8_t)0x20)
|
||||
#define LSM303AGR_IT1_DRY1 ((uint8_t)0x10)
|
||||
#define LSM303AGR_IT1_DRY2 ((uint8_t)0x08)
|
||||
#define LSM303AGR_IT1_WTM ((uint8_t)0x04)
|
||||
#define LSM303AGR_IT1_OVERRUN ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Interrupt2_Configuration_definition
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_IT2_CLICK ((uint8_t)0x80)
|
||||
#define LSM303AGR_IT2_INT1 ((uint8_t)0x40)
|
||||
#define LSM303AGR_IT2_INT2 ((uint8_t)0x20)
|
||||
#define LSM303AGR_IT2_BOOT ((uint8_t)0x10)
|
||||
#define LSM303AGR_IT2_ACT ((uint8_t)0x08)
|
||||
#define LSM303AGR_IT2_HLACTIVE ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT_Combination_Status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_OR_COMBINATION ((uint8_t)0x00) /*!< OR combination of enabled IRQs */
|
||||
#define LSM303AGR_AND_COMBINATION ((uint8_t)0x80) /*!< AND combination of enabled IRQs */
|
||||
#define LSM303AGR_MOV_RECOGNITION ((uint8_t)0x40) /*!< 6D movement recognition */
|
||||
#define LSM303AGR_POS_RECOGNITION ((uint8_t)0xC0) /*!< 6D position recognition */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT_Axes
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_Z_HIGH ((uint8_t)0x20) /*!< Z High enabled IRQs */
|
||||
#define LSM303AGR_Z_LOW ((uint8_t)0x10) /*!< Z low enabled IRQs */
|
||||
#define LSM303AGR_Y_HIGH ((uint8_t)0x08) /*!< Y High enabled IRQs */
|
||||
#define LSM303AGR_Y_LOW ((uint8_t)0x04) /*!< Y low enabled IRQs */
|
||||
#define LSM303AGR_X_HIGH ((uint8_t)0x02) /*!< X High enabled IRQs */
|
||||
#define LSM303AGR_X_LOW ((uint8_t)0x01) /*!< X low enabled IRQs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT_Click
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_Z_DOUBLE_CLICK ((uint8_t)0x20) /*!< Z double click IRQs */
|
||||
#define LSM303AGR_Z_SINGLE_CLICK ((uint8_t)0x10) /*!< Z single click IRQs */
|
||||
#define LSM303AGR_Y_DOUBLE_CLICK ((uint8_t)0x08) /*!< Y double click IRQs */
|
||||
#define LSM303AGR_Y_SINGLE_CLICK ((uint8_t)0x04) /*!< Y single click IRQs */
|
||||
#define LSM303AGR_X_DOUBLE_CLICK ((uint8_t)0x02) /*!< X double click IRQs */
|
||||
#define LSM303AGR_X_SINGLE_CLICK ((uint8_t)0x01) /*!< X single click IRQs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT1_Interrupt_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_INT1INTERRUPT_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303AGR_INT1INTERRUPT_ENABLE ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT1_Interrupt_ActiveEdge
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_INT1INTERRUPT_LOW_EDGE ((uint8_t)0x20)
|
||||
#define LSM303AGR_INT1INTERRUPT_HIGH_EDGE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Data_Rate
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_ODR_0_75_HZ ((uint8_t) 0x00) /*!< Output Data Rate = 0.75 Hz */
|
||||
#define LSM303AGR_ODR_1_5_HZ ((uint8_t) 0x04) /*!< Output Data Rate = 1.5 Hz */
|
||||
#define LSM303AGR_ODR_3_0_HZ ((uint8_t) 0x08) /*!< Output Data Rate = 3 Hz */
|
||||
#define LSM303AGR_ODR_7_5_HZ ((uint8_t) 0x0C) /*!< Output Data Rate = 7.5 Hz */
|
||||
#define LSM303AGR_ODR_15_HZ ((uint8_t) 0x10) /*!< Output Data Rate = 15 Hz */
|
||||
#define LSM303AGR_ODR_30_HZ ((uint8_t) 0x14) /*!< Output Data Rate = 30 Hz */
|
||||
#define LSM303AGR_ODR_75_HZ ((uint8_t) 0x18) /*!< Output Data Rate = 75 Hz */
|
||||
#define LSM303AGR_ODR_220_HZ ((uint8_t) 0x1C) /*!< Output Data Rate = 220 Hz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Full_Scale
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_FS_1_3_GA ((uint8_t) 0x20) /*!< Full scale = <20>1.3 Gauss */
|
||||
#define LSM303AGR_FS_1_9_GA ((uint8_t) 0x40) /*!< Full scale = <20>1.9 Gauss */
|
||||
#define LSM303AGR_FS_2_5_GA ((uint8_t) 0x60) /*!< Full scale = <20>2.5 Gauss */
|
||||
#define LSM303AGR_FS_4_0_GA ((uint8_t) 0x80) /*!< Full scale = <20>4.0 Gauss */
|
||||
#define LSM303AGR_FS_4_7_GA ((uint8_t) 0xA0) /*!< Full scale = <20>4.7 Gauss */
|
||||
#define LSM303AGR_FS_5_6_GA ((uint8_t) 0xC0) /*!< Full scale = <20>5.6 Gauss */
|
||||
#define LSM303AGR_FS_8_1_GA ((uint8_t) 0xE0) /*!< Full scale = <20>8.1 Gauss */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Magnetometer_Sensitivity
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_M_SENSITIVITY_XY_1_3Ga 1100 /*!< magnetometer X Y axes sensitivity for 1.3 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_XY_1_9Ga 855 /*!< magnetometer X Y axes sensitivity for 1.9 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_XY_2_5Ga 670 /*!< magnetometer X Y axes sensitivity for 2.5 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_XY_4Ga 450 /*!< magnetometer X Y axes sensitivity for 4 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_XY_4_7Ga 400 /*!< magnetometer X Y axes sensitivity for 4.7 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_XY_5_6Ga 330 /*!< magnetometer X Y axes sensitivity for 5.6 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_XY_8_1Ga 230 /*!< magnetometer X Y axes sensitivity for 8.1 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_Z_1_3Ga 980 /*!< magnetometer Z axis sensitivity for 1.3 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_Z_1_9Ga 760 /*!< magnetometer Z axis sensitivity for 1.9 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_Z_2_5Ga 600 /*!< magnetometer Z axis sensitivity for 2.5 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_Z_4Ga 400 /*!< magnetometer Z axis sensitivity for 4 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_Z_4_7Ga 355 /*!< magnetometer Z axis sensitivity for 4.7 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_Z_5_6Ga 295 /*!< magnetometer Z axis sensitivity for 5.6 Ga full scale [LSB/Ga] */
|
||||
#define LSM303AGR_M_SENSITIVITY_Z_8_1Ga 205 /*!< magnetometer Z axis sensitivity for 8.1 Ga full scale [LSB/Ga] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Working_Mode
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_CONTINUOS_CONVERSION ((uint8_t) 0x00) /*!< Continuous-Conversion Mode */
|
||||
#define LSM303AGR_SINGLE_CONVERSION ((uint8_t) 0x01) /*!< Single-Conversion Mode */
|
||||
#define LSM303AGR_SLEEP ((uint8_t) 0x02) /*!< Sleep Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Temperature_Sensor
|
||||
* @{
|
||||
*/
|
||||
#define LSM303AGR_TEMPSENSOR_ENABLE ((uint8_t) 0x80) /*!< Temp sensor Enable */
|
||||
#define LSM303AGR_TEMPSENSOR_DISABLE ((uint8_t) 0x00) /*!< Temp sensor Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303AGR_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* ACC functions */
|
||||
void LSM303AGR_AccInit(uint16_t InitStruct);
|
||||
void LSM303AGR_AccDeInit(void);
|
||||
uint8_t LSM303AGR_AccReadID(void);
|
||||
void LSM303AGR_AccRebootCmd(void);
|
||||
void LSM303AGR_AccFilterConfig(uint8_t FilterStruct);
|
||||
void LSM303AGR_AccFilterCmd(uint8_t HighPassFilterState);
|
||||
void LSM303AGR_AccReadXYZ(int16_t* pData);
|
||||
void LSM303AGR_AccFilterClickCmd(uint8_t HighPassFilterClickState);
|
||||
void LSM303AGR_AccIT1Enable(uint8_t LSM303AGR_IT);
|
||||
void LSM303AGR_AccIT1Disable(uint8_t LSM303AGR_IT);
|
||||
void LSM303AGR_AccIT2Enable(uint8_t LSM303AGR_IT);
|
||||
void LSM303AGR_AccIT2Disable(uint8_t LSM303AGR_IT);
|
||||
void LSM303AGR_AccINT1InterruptEnable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303AGR_AccINT1InterruptDisable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303AGR_AccINT2InterruptEnable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303AGR_AccINT2InterruptDisable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303AGR_AccClickITEnable(uint8_t ITClick);
|
||||
void LSM303AGR_AccClickITDisable(uint8_t ITClick);
|
||||
void LSM303AGR_AccZClickITConfig(void);
|
||||
|
||||
#if 0
|
||||
/* MAG functions */
|
||||
void LSM303AGR_MagInit(LSM303AGRMag_InitTypeDef *LSM303AGR_InitStruct);
|
||||
uint8_t LSM303AGR_MagGetDataStatus(void);
|
||||
void LSM303AGR_CompassReadAcc(int16_t* pData);
|
||||
#endif
|
||||
|
||||
/* COMPASS / ACCELERO IO functions */
|
||||
void COMPASSACCELERO_IO_Init(void);
|
||||
void COMPASSACCELERO_IO_ITConfig(void);
|
||||
void COMPASSACCELERO_IO_Write(uint16_t DeviceAddr, uint8_t RegisterAddr, uint8_t Value);
|
||||
uint8_t COMPASSACCELERO_IO_Read(uint16_t DeviceAddr, uint8_t RegisterAddr);
|
||||
|
||||
/* ACC driver structure */
|
||||
extern ACCELERO_DrvTypeDef Lsm303agrDrv;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LSM303AGR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,365 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
|
||||
|
||||
|
||||
<link rel="File-List" href="Library_files/filelist.xml">
|
||||
|
||||
|
||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for LSM303DLHC Component Driver</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{mso-style-parent:"";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
h2
|
||||
{mso-style-next:Normal;
|
||||
margin-top:12.0pt;
|
||||
margin-right:0in;
|
||||
margin-bottom:3.0pt;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
|
||||
font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
font-weight:bold;
|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
a:visited, span.MsoHyperlinkFollowed
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
p
|
||||
{mso-margin-top-alt:auto;
|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
@page Section1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
|
||||
<meta content="MCD Application Team" name="author"></head>
|
||||
<body link="blue" vlink="blue">
|
||||
<div class="Section1">
|
||||
<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
||||
</o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="vertical-align: top;">
|
||||
<p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
|
||||
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||||
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||||
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|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for LSM303DLHC Component Driver</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
||||
2015 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
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|
||||
<td style="padding: 0cm;" valign="top"><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2>
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<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 24-June-2015 <o:p></o:p></span></h3>
|
||||
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||||
|
||||
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||||
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|
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|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">lsm303dlhc.c: </span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Add accelerometer de-initialization function: LSM303DLHC_AccDeInit()</span></li></ul><ul><li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">NOTE:</span> This release must be used with BSP Common
|
||||
driver V4.0.0</span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 20-November-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;">
|
||||
<li><span style="font-size: 10pt; font-family: Verdana;">lsm303dlhc.h: change "\" by "/" in the include path to fix compilation issue under Linux</span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span></li>
|
||||
<li><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous comments update</span></li>
|
||||
</ul>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Arial; color: white;"><o:p></o:p></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span><br></h2><div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:</span><br>
|
||||
</font>
|
||||
<ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
||||
in binary form must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
|
||||
</font>
|
||||
</li></ol>
|
||||
<font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";"></span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
|
||||
|
||||
</div>
|
||||
|
||||
<b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
|
||||
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<div style="margin-left: 160px;"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span></div>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
|
||||
</body></html>
|
||||
@@ -0,0 +1,578 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file lsm303dlhc.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 24-June-2015
|
||||
* @brief This file provides a set of functions needed to manage the lsm303dlhc
|
||||
* MEMS accelerometer.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "lsm303dlhc.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LSM303DLHC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303DLHC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303DLHC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303DLHC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303DLHC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
ACCELERO_DrvTypeDef Lsm303dlhcDrv =
|
||||
{
|
||||
LSM303DLHC_AccInit,
|
||||
LSM303DLHC_AccDeInit,
|
||||
LSM303DLHC_AccReadID,
|
||||
LSM303DLHC_AccRebootCmd,
|
||||
0,
|
||||
LSM303DLHC_AccZClickITConfig,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
LSM303DLHC_AccFilterConfig,
|
||||
LSM303DLHC_AccFilterCmd,
|
||||
LSM303DLHC_AccReadXYZ
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303DLHC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set LSM303DLHC Initialization.
|
||||
* @param InitStruct: Init parameters
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccInit(uint16_t InitStruct)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Low level init */
|
||||
COMPASSACCELERO_IO_Init();
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG1 register */
|
||||
ctrl = (uint8_t) InitStruct;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG1_A, ctrl);
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG4 register */
|
||||
ctrl = (uint8_t) (InitStruct << 8);
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG4_A, ctrl);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LSM303DLHC De-initialization.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccDeInit(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read LSM303DLHC ID.
|
||||
* @param None
|
||||
* @retval ID
|
||||
*/
|
||||
uint8_t LSM303DLHC_AccReadID(void)
|
||||
{
|
||||
uint8_t ctrl = 0x00;
|
||||
|
||||
/* Low level init */
|
||||
COMPASSACCELERO_IO_Init();
|
||||
|
||||
/* Read value at Who am I register address */
|
||||
ctrl = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_WHO_AM_I_ADDR);
|
||||
|
||||
return ctrl;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reboot memory content of LSM303DLHC
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccRebootCmd(void)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG5 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG5_A);
|
||||
|
||||
/* Enable or Disable the reboot memory */
|
||||
tmpreg |= LSM303DLHC_BOOT_REBOOTMEMORY;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG5 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG5_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set High Pass Filter Modality
|
||||
* @param FilterStruct: contains data for filter config
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccFilterConfig(uint8_t FilterStruct)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG2_A);
|
||||
|
||||
tmpreg &= 0x0C;
|
||||
tmpreg |= FilterStruct;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG2 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG2_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable High Pass Filter
|
||||
* @param HighPassFilterState: new state of the High Pass Filter feature.
|
||||
* This parameter can be:
|
||||
* @arg: LSM303DLHC_HIGHPASSFILTER_DISABLE
|
||||
* @arg: LSM303DLHC_HIGHPASSFILTER_ENABLE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccFilterCmd(uint8_t HighPassFilterState)
|
||||
{
|
||||
uint8_t tmpreg;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG2_A);
|
||||
|
||||
tmpreg &= 0xF7;
|
||||
|
||||
tmpreg |= HighPassFilterState;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG2 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG2_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read X, Y & Z Acceleration values
|
||||
* @param pData: Data out pointer
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccReadXYZ(int16_t* pData)
|
||||
{
|
||||
int16_t pnRawData[3];
|
||||
uint8_t ctrlx[2]={0,0};
|
||||
int8_t buffer[6];
|
||||
uint8_t i = 0;
|
||||
uint8_t sensitivity = LSM303DLHC_ACC_SENSITIVITY_2G;
|
||||
|
||||
/* Read the acceleration control register content */
|
||||
ctrlx[0] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG4_A);
|
||||
ctrlx[1] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG5_A);
|
||||
|
||||
/* Read output register X, Y & Z acceleration */
|
||||
buffer[0] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_OUT_X_L_A);
|
||||
buffer[1] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_OUT_X_H_A);
|
||||
buffer[2] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_OUT_Y_L_A);
|
||||
buffer[3] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_OUT_Y_H_A);
|
||||
buffer[4] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_OUT_Z_L_A);
|
||||
buffer[5] = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_OUT_Z_H_A);
|
||||
|
||||
/* Check in the control register4 the data alignment*/
|
||||
if(!(ctrlx[0] & LSM303DLHC_BLE_MSB))
|
||||
{
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
pnRawData[i]=((int16_t)((uint16_t)buffer[2*i+1] << 8) + buffer[2*i]);
|
||||
}
|
||||
}
|
||||
else /* Big Endian Mode */
|
||||
{
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
pnRawData[i]=((int16_t)((uint16_t)buffer[2*i] << 8) + buffer[2*i+1]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Normal mode */
|
||||
/* Switch the sensitivity value set in the CRTL4 */
|
||||
switch(ctrlx[0] & LSM303DLHC_FULLSCALE_16G)
|
||||
{
|
||||
case LSM303DLHC_FULLSCALE_2G:
|
||||
sensitivity = LSM303DLHC_ACC_SENSITIVITY_2G;
|
||||
break;
|
||||
case LSM303DLHC_FULLSCALE_4G:
|
||||
sensitivity = LSM303DLHC_ACC_SENSITIVITY_4G;
|
||||
break;
|
||||
case LSM303DLHC_FULLSCALE_8G:
|
||||
sensitivity = LSM303DLHC_ACC_SENSITIVITY_8G;
|
||||
break;
|
||||
case LSM303DLHC_FULLSCALE_16G:
|
||||
sensitivity = LSM303DLHC_ACC_SENSITIVITY_16G;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Obtain the mg value for the three axis */
|
||||
for(i=0; i<3; i++)
|
||||
{
|
||||
pData[i]=(pnRawData[i] * sensitivity);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or Disable High Pass Filter on CLick
|
||||
* @param HighPassFilterState: new state of the High Pass Filter feature.
|
||||
* This parameter can be:
|
||||
* @arg: LSM303DLHC_HPF_CLICK_DISABLE
|
||||
* @arg: LSM303DLHC_HPF_CLICK_ENABLE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccFilterClickCmd(uint8_t HighPassFilterClickState)
|
||||
{
|
||||
uint8_t tmpreg = 0x00;
|
||||
|
||||
/* Read CTRL_REG2 register */
|
||||
tmpreg = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG2_A);
|
||||
|
||||
tmpreg &= ~(LSM303DLHC_HPF_CLICK_ENABLE);
|
||||
|
||||
tmpreg |= HighPassFilterClickState;
|
||||
|
||||
/* Write value to ACC MEMS CTRL_REG2 regsister */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG2_A, tmpreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable LSM303DLHC Interrupt1
|
||||
* @param LSM303DLHC_IT: specifies the LSM303DLHC interrupt source to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303DLHC_IT1_CLICK
|
||||
* @arg LSM303DLHC_IT1_AOI1
|
||||
* @arg LSM303DLHC_IT1_AOI2
|
||||
* @arg LSM303DLHC_IT1_DRY1
|
||||
* @arg LSM303DLHC_IT1_DRY2
|
||||
* @arg LSM303DLHC_IT1_WTM
|
||||
* @arg LSM303DLHC_IT1_OVERRUN
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccIT1Enable(uint8_t LSM303DLHC_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG3_A);
|
||||
|
||||
/* Enable IT1 */
|
||||
tmpval |= LSM303DLHC_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG3_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable LSM303DLHC Interrupt1
|
||||
* @param LSM303DLHC_IT: specifies the LSM303DLHC interrupt source to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303DLHC_IT1_CLICK
|
||||
* @arg LSM303DLHC_IT1_AOI1
|
||||
* @arg LSM303DLHC_IT1_AOI2
|
||||
* @arg LSM303DLHC_IT1_DRY1
|
||||
* @arg LSM303DLHC_IT1_DRY2
|
||||
* @arg LSM303DLHC_IT1_WTM
|
||||
* @arg LSM303DLHC_IT1_OVERRUN
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccIT1Disable(uint8_t LSM303DLHC_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG3_A);
|
||||
|
||||
/* Disable IT1 */
|
||||
tmpval &= ~LSM303DLHC_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG3_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable LSM303DLHC Interrupt2
|
||||
* @param LSM303DLHC_IT: specifies the LSM303DLHC interrupt source to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303DLHC_IT2_CLICK
|
||||
* @arg LSM303DLHC_IT2_INT1
|
||||
* @arg LSM303DLHC_IT2_INT2
|
||||
* @arg LSM303DLHC_IT2_BOOT
|
||||
* @arg LSM303DLHC_IT2_ACT
|
||||
* @arg LSM303DLHC_IT2_HLACTIVE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccIT2Enable(uint8_t LSM303DLHC_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG6_A);
|
||||
|
||||
/* Enable IT2 */
|
||||
tmpval |= LSM303DLHC_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG6_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable LSM303DLHC Interrupt2
|
||||
* @param LSM303DLHC_IT: specifies the LSM303DLHC interrupt source to be disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LSM303DLHC_IT2_CLICK
|
||||
* @arg LSM303DLHC_IT2_INT1
|
||||
* @arg LSM303DLHC_IT2_INT2
|
||||
* @arg LSM303DLHC_IT2_BOOT
|
||||
* @arg LSM303DLHC_IT2_ACT
|
||||
* @arg LSM303DLHC_IT2_HLACTIVE
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccIT2Disable(uint8_t LSM303DLHC_IT)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CTRL_REG3 register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG6_A);
|
||||
|
||||
/* Disable IT2 */
|
||||
tmpval &= ~LSM303DLHC_IT;
|
||||
|
||||
/* Write value to MEMS CTRL_REG3 register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CTRL_REG6_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT1 interrupt enable
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: Axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccINT1InterruptEnable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT1_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_INT1_CFG_A);
|
||||
|
||||
/* Enable the selected interrupt */
|
||||
tmpval |= (ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT1_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_INT1_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT1 interrupt disable
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: Axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccINT1InterruptDisable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT1_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_INT1_CFG_A);
|
||||
|
||||
/* Disable the selected interrupt */
|
||||
tmpval &= ~(ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT1_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_INT1_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT2 interrupt enable
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccINT2InterruptEnable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT2_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_INT2_CFG_A);
|
||||
|
||||
/* Enable the selected interrupt */
|
||||
tmpval |= (ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT2_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_INT2_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief INT2 interrupt config
|
||||
* @param ITCombination: Or or And combination
|
||||
* ITAxes: axes to be enabled
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccINT2InterruptDisable(uint8_t ITCombination, uint8_t ITAxes)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read INT2_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_INT2_CFG_A);
|
||||
|
||||
/* Disable the selected interrupt */
|
||||
tmpval &= ~(ITAxes | ITCombination);
|
||||
|
||||
/* Write value to MEMS INT2_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_INT2_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Click interrupt enable
|
||||
* @param ITClick: the selected interrupt to enable
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccClickITEnable(uint8_t ITClick)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CLICK_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CLICK_CFG_A);
|
||||
|
||||
/* Enable the selected interrupt */
|
||||
tmpval |= ITClick;
|
||||
|
||||
/* Write value to MEMS CLICK CFG register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CLICK_CFG_A, tmpval);
|
||||
|
||||
/* Configure Click Threshold on Z axis */
|
||||
tmpval = 0x0A;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CLICK_THS_A, tmpval);
|
||||
|
||||
/* Configure Time Limit */
|
||||
tmpval = 0x05;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_TIME_LIMIT_A, tmpval);
|
||||
|
||||
/* Configure Latency */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_TIME_LATENCY_A, tmpval);
|
||||
|
||||
/* Configure Click Window */
|
||||
tmpval = 0x32;
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_TIME_WINDOW_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Click interrupt disable
|
||||
* @param ITClick: the selected click interrupt to disable
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccClickITDisable(uint8_t ITClick)
|
||||
{
|
||||
uint8_t tmpval = 0x00;
|
||||
|
||||
/* Read CLICK_CFR register */
|
||||
tmpval = COMPASSACCELERO_IO_Read(ACC_I2C_ADDRESS, LSM303DLHC_CLICK_CFG_A);
|
||||
|
||||
/* Disable the selected interrupt */
|
||||
tmpval &= ~ITClick;
|
||||
|
||||
/* Write value to MEMS CLICK_CFR register */
|
||||
COMPASSACCELERO_IO_Write(ACC_I2C_ADDRESS, LSM303DLHC_CLICK_CFG_A, tmpval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Click on Z axis interrupt config
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LSM303DLHC_AccZClickITConfig(void)
|
||||
{
|
||||
/* Configure low level IT config */
|
||||
COMPASSACCELERO_IO_ITConfig();
|
||||
|
||||
/* Select click IT as INT1 interrupt */
|
||||
LSM303DLHC_AccIT1Enable(LSM303DLHC_IT1_CLICK);
|
||||
|
||||
/* Enable High pass filter for click IT */
|
||||
LSM303DLHC_AccFilterClickCmd(LSM303DLHC_HPF_CLICK_ENABLE);
|
||||
|
||||
/* Enable simple click IT on Z axis, */
|
||||
LSM303DLHC_AccClickITEnable(LSM303DLHC_Z_SINGLE_CLICK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,498 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file lsm303dlhc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 24-June-2015
|
||||
* @brief This file contains all the functions prototypes for the lsm303dlhc.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __LSM303DLHC_H
|
||||
#define __LSM303DLHC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "../Common/accelero.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Components
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LSM303DLHC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303DLHC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** START REGISTER MAPPING **************************/
|
||||
/******************************************************************************/
|
||||
/* Exported constant IO ------------------------------------------------------*/
|
||||
#define ACC_I2C_ADDRESS 0x32
|
||||
#define MAG_I2C_ADDRESS 0x3C
|
||||
|
||||
/* Acceleration Registers */
|
||||
#define LSM303DLHC_WHO_AM_I_ADDR 0x0F /* device identification register */
|
||||
#define LSM303DLHC_CTRL_REG1_A 0x20 /* Control register 1 acceleration */
|
||||
#define LSM303DLHC_CTRL_REG2_A 0x21 /* Control register 2 acceleration */
|
||||
#define LSM303DLHC_CTRL_REG3_A 0x22 /* Control register 3 acceleration */
|
||||
#define LSM303DLHC_CTRL_REG4_A 0x23 /* Control register 4 acceleration */
|
||||
#define LSM303DLHC_CTRL_REG5_A 0x24 /* Control register 5 acceleration */
|
||||
#define LSM303DLHC_CTRL_REG6_A 0x25 /* Control register 6 acceleration */
|
||||
#define LSM303DLHC_REFERENCE_A 0x26 /* Reference register acceleration */
|
||||
#define LSM303DLHC_STATUS_REG_A 0x27 /* Status register acceleration */
|
||||
#define LSM303DLHC_OUT_X_L_A 0x28 /* Output Register X acceleration */
|
||||
#define LSM303DLHC_OUT_X_H_A 0x29 /* Output Register X acceleration */
|
||||
#define LSM303DLHC_OUT_Y_L_A 0x2A /* Output Register Y acceleration */
|
||||
#define LSM303DLHC_OUT_Y_H_A 0x2B /* Output Register Y acceleration */
|
||||
#define LSM303DLHC_OUT_Z_L_A 0x2C /* Output Register Z acceleration */
|
||||
#define LSM303DLHC_OUT_Z_H_A 0x2D /* Output Register Z acceleration */
|
||||
#define LSM303DLHC_FIFO_CTRL_REG_A 0x2E /* Fifo control Register acceleration */
|
||||
#define LSM303DLHC_FIFO_SRC_REG_A 0x2F /* Fifo src Register acceleration */
|
||||
|
||||
#define LSM303DLHC_INT1_CFG_A 0x30 /* Interrupt 1 configuration Register acceleration */
|
||||
#define LSM303DLHC_INT1_SOURCE_A 0x31 /* Interrupt 1 source Register acceleration */
|
||||
#define LSM303DLHC_INT1_THS_A 0x32 /* Interrupt 1 Threshold register acceleration */
|
||||
#define LSM303DLHC_INT1_DURATION_A 0x33 /* Interrupt 1 DURATION register acceleration */
|
||||
|
||||
#define LSM303DLHC_INT2_CFG_A 0x34 /* Interrupt 2 configuration Register acceleration */
|
||||
#define LSM303DLHC_INT2_SOURCE_A 0x35 /* Interrupt 2 source Register acceleration */
|
||||
#define LSM303DLHC_INT2_THS_A 0x36 /* Interrupt 2 Threshold register acceleration */
|
||||
#define LSM303DLHC_INT2_DURATION_A 0x37 /* Interrupt 2 DURATION register acceleration */
|
||||
|
||||
#define LSM303DLHC_CLICK_CFG_A 0x38 /* Click configuration Register acceleration */
|
||||
#define LSM303DLHC_CLICK_SOURCE_A 0x39 /* Click 2 source Register acceleration */
|
||||
#define LSM303DLHC_CLICK_THS_A 0x3A /* Click 2 Threshold register acceleration */
|
||||
|
||||
#define LSM303DLHC_TIME_LIMIT_A 0x3B /* Time Limit Register acceleration */
|
||||
#define LSM303DLHC_TIME_LATENCY_A 0x3C /* Time Latency Register acceleration */
|
||||
#define LSM303DLHC_TIME_WINDOW_A 0x3D /* Time window register acceleration */
|
||||
|
||||
/* Magnetic field Registers */
|
||||
#define LSM303DLHC_CRA_REG_M 0x00 /* Control register A magnetic field */
|
||||
#define LSM303DLHC_CRB_REG_M 0x01 /* Control register B magnetic field */
|
||||
#define LSM303DLHC_MR_REG_M 0x02 /* Control register MR magnetic field */
|
||||
#define LSM303DLHC_OUT_X_H_M 0x03 /* Output Register X magnetic field */
|
||||
#define LSM303DLHC_OUT_X_L_M 0x04 /* Output Register X magnetic field */
|
||||
#define LSM303DLHC_OUT_Z_H_M 0x05 /* Output Register Z magnetic field */
|
||||
#define LSM303DLHC_OUT_Z_L_M 0x06 /* Output Register Z magnetic field */
|
||||
#define LSM303DLHC_OUT_Y_H_M 0x07 /* Output Register Y magnetic field */
|
||||
#define LSM303DLHC_OUT_Y_L_M 0x08 /* Output Register Y magnetic field */
|
||||
|
||||
#define LSM303DLHC_SR_REG_M 0x09 /* Status Register magnetic field */
|
||||
#define LSM303DLHC_IRA_REG_M 0x0A /* IRA Register magnetic field */
|
||||
#define LSM303DLHC_IRB_REG_M 0x0B /* IRB Register magnetic field */
|
||||
#define LSM303DLHC_IRC_REG_M 0x0C /* IRC Register magnetic field */
|
||||
|
||||
#define LSM303DLHC_TEMP_OUT_H_M 0x31 /* Temperature Register magnetic field */
|
||||
#define LSM303DLHC_TEMP_OUT_L_M 0x32 /* Temperature Register magnetic field */
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** END REGISTER MAPPING ***************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define I_AM_LMS303DLHC ((uint8_t)0x33)
|
||||
|
||||
/** @defgroup Acc_Power_Mode_selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_NORMAL_MODE ((uint8_t)0x00)
|
||||
#define LSM303DLHC_LOWPOWER_MODE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_OutPut_DataRate_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_ODR_1_HZ ((uint8_t)0x10) /*!< Output Data Rate = 1 Hz */
|
||||
#define LSM303DLHC_ODR_10_HZ ((uint8_t)0x20) /*!< Output Data Rate = 10 Hz */
|
||||
#define LSM303DLHC_ODR_25_HZ ((uint8_t)0x30) /*!< Output Data Rate = 25 Hz */
|
||||
#define LSM303DLHC_ODR_50_HZ ((uint8_t)0x40) /*!< Output Data Rate = 50 Hz */
|
||||
#define LSM303DLHC_ODR_100_HZ ((uint8_t)0x50) /*!< Output Data Rate = 100 Hz */
|
||||
#define LSM303DLHC_ODR_200_HZ ((uint8_t)0x60) /*!< Output Data Rate = 200 Hz */
|
||||
#define LSM303DLHC_ODR_400_HZ ((uint8_t)0x70) /*!< Output Data Rate = 400 Hz */
|
||||
#define LSM303DLHC_ODR_1620_HZ_LP ((uint8_t)0x80) /*!< Output Data Rate = 1620 Hz only in Low Power Mode */
|
||||
#define LSM303DLHC_ODR_1344_HZ ((uint8_t)0x90) /*!< Output Data Rate = 1344 Hz in Normal mode and 5376 Hz in Low Power Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Axes_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_X_ENABLE ((uint8_t)0x01)
|
||||
#define LSM303DLHC_Y_ENABLE ((uint8_t)0x02)
|
||||
#define LSM303DLHC_Z_ENABLE ((uint8_t)0x04)
|
||||
#define LSM303DLHC_AXES_ENABLE ((uint8_t)0x07)
|
||||
#define LSM303DLHC_AXES_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Resolution
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_HR_ENABLE ((uint8_t)0x08)
|
||||
#define LSM303DLHC_HR_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Full_Scale_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_FULLSCALE_2G ((uint8_t)0x00) /*!< <20>2 g */
|
||||
#define LSM303DLHC_FULLSCALE_4G ((uint8_t)0x10) /*!< <20>4 g */
|
||||
#define LSM303DLHC_FULLSCALE_8G ((uint8_t)0x20) /*!< <20>8 g */
|
||||
#define LSM303DLHC_FULLSCALE_16G ((uint8_t)0x30) /*!< <20>16 g */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Full_Scale_Selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_ACC_SENSITIVITY_2G ((uint8_t)1) /*!< accelerometer sensitivity with 2 g full scale [mg/LSB] */
|
||||
#define LSM303DLHC_ACC_SENSITIVITY_4G ((uint8_t)2) /*!< accelerometer sensitivity with 4 g full scale [mg/LSB] */
|
||||
#define LSM303DLHC_ACC_SENSITIVITY_8G ((uint8_t)4) /*!< accelerometer sensitivity with 8 g full scale [mg/LSB] */
|
||||
#define LSM303DLHC_ACC_SENSITIVITY_16G ((uint8_t)12) /*!< accelerometer sensitivity with 12 g full scale [mg/LSB] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Block_Data_Update
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_BlockUpdate_Continous ((uint8_t)0x00) /*!< Continuos Update */
|
||||
#define LSM303DLHC_BlockUpdate_Single ((uint8_t)0x80) /*!< Single Update: output registers not updated until MSB and LSB reading */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Endian_Data_selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_BLE_LSB ((uint8_t)0x00) /*!< Little Endian: data LSB @ lower address */
|
||||
#define LSM303DLHC_BLE_MSB ((uint8_t)0x40) /*!< Big Endian: data MSB @ lower address */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Boot_Mode_selection
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_BOOT_NORMALMODE ((uint8_t)0x00)
|
||||
#define LSM303DLHC_BOOT_REBOOTMEMORY ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_Mode
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_HPM_NORMAL_MODE_RES ((uint8_t)0x00)
|
||||
#define LSM303DLHC_HPM_REF_SIGNAL ((uint8_t)0x40)
|
||||
#define LSM303DLHC_HPM_NORMAL_MODE ((uint8_t)0x80)
|
||||
#define LSM303DLHC_HPM_AUTORESET_INT ((uint8_t)0xC0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_CUT OFF_Frequency
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_HPFCF_8 ((uint8_t)0x00)
|
||||
#define LSM303DLHC_HPFCF_16 ((uint8_t)0x10)
|
||||
#define LSM303DLHC_HPFCF_32 ((uint8_t)0x20)
|
||||
#define LSM303DLHC_HPFCF_64 ((uint8_t)0x30)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_HIGHPASSFILTER_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303DLHC_HIGHPASSFILTER_ENABLE ((uint8_t)0x08)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_Click_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_HPF_CLICK_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303DLHC_HPF_CLICK_ENABLE ((uint8_t)0x04)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_AOI1_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_HPF_AOI1_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303DLHC_HPF_AOI1_ENABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_High_Pass_Filter_AOI2_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_HPF_AOI2_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303DLHC_HPF_AOI2_ENABLE ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Interrupt1_Configuration_definition
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_IT1_CLICK ((uint8_t)0x80)
|
||||
#define LSM303DLHC_IT1_AOI1 ((uint8_t)0x40)
|
||||
#define LSM303DLHC_IT1_AOI2 ((uint8_t)0x20)
|
||||
#define LSM303DLHC_IT1_DRY1 ((uint8_t)0x10)
|
||||
#define LSM303DLHC_IT1_DRY2 ((uint8_t)0x08)
|
||||
#define LSM303DLHC_IT1_WTM ((uint8_t)0x04)
|
||||
#define LSM303DLHC_IT1_OVERRUN ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_Interrupt2_Configuration_definition
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_IT2_CLICK ((uint8_t)0x80)
|
||||
#define LSM303DLHC_IT2_INT1 ((uint8_t)0x40)
|
||||
#define LSM303DLHC_IT2_INT2 ((uint8_t)0x20)
|
||||
#define LSM303DLHC_IT2_BOOT ((uint8_t)0x10)
|
||||
#define LSM303DLHC_IT2_ACT ((uint8_t)0x08)
|
||||
#define LSM303DLHC_IT2_HLACTIVE ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT_Combination_Status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_OR_COMBINATION ((uint8_t)0x00) /*!< OR combination of enabled IRQs */
|
||||
#define LSM303DLHC_AND_COMBINATION ((uint8_t)0x80) /*!< AND combination of enabled IRQs */
|
||||
#define LSM303DLHC_MOV_RECOGNITION ((uint8_t)0x40) /*!< 6D movement recognition */
|
||||
#define LSM303DLHC_POS_RECOGNITION ((uint8_t)0xC0) /*!< 6D position recognition */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT_Axes
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_Z_HIGH ((uint8_t)0x20) /*!< Z High enabled IRQs */
|
||||
#define LSM303DLHC_Z_LOW ((uint8_t)0x10) /*!< Z low enabled IRQs */
|
||||
#define LSM303DLHC_Y_HIGH ((uint8_t)0x08) /*!< Y High enabled IRQs */
|
||||
#define LSM303DLHC_Y_LOW ((uint8_t)0x04) /*!< Y low enabled IRQs */
|
||||
#define LSM303DLHC_X_HIGH ((uint8_t)0x02) /*!< X High enabled IRQs */
|
||||
#define LSM303DLHC_X_LOW ((uint8_t)0x01) /*!< X low enabled IRQs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT_Click
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_Z_DOUBLE_CLICK ((uint8_t)0x20) /*!< Z double click IRQs */
|
||||
#define LSM303DLHC_Z_SINGLE_CLICK ((uint8_t)0x10) /*!< Z single click IRQs */
|
||||
#define LSM303DLHC_Y_DOUBLE_CLICK ((uint8_t)0x08) /*!< Y double click IRQs */
|
||||
#define LSM303DLHC_Y_SINGLE_CLICK ((uint8_t)0x04) /*!< Y single click IRQs */
|
||||
#define LSM303DLHC_X_DOUBLE_CLICK ((uint8_t)0x02) /*!< X double click IRQs */
|
||||
#define LSM303DLHC_X_SINGLE_CLICK ((uint8_t)0x01) /*!< X single click IRQs */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT1_Interrupt_status
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_INT1INTERRUPT_DISABLE ((uint8_t)0x00)
|
||||
#define LSM303DLHC_INT1INTERRUPT_ENABLE ((uint8_t)0x80)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Acc_INT1_Interrupt_ActiveEdge
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_INT1INTERRUPT_LOW_EDGE ((uint8_t)0x20)
|
||||
#define LSM303DLHC_INT1INTERRUPT_HIGH_EDGE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Data_Rate
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_ODR_0_75_HZ ((uint8_t) 0x00) /*!< Output Data Rate = 0.75 Hz */
|
||||
#define LSM303DLHC_ODR_1_5_HZ ((uint8_t) 0x04) /*!< Output Data Rate = 1.5 Hz */
|
||||
#define LSM303DLHC_ODR_3_0_HZ ((uint8_t) 0x08) /*!< Output Data Rate = 3 Hz */
|
||||
#define LSM303DLHC_ODR_7_5_HZ ((uint8_t) 0x0C) /*!< Output Data Rate = 7.5 Hz */
|
||||
#define LSM303DLHC_ODR_15_HZ ((uint8_t) 0x10) /*!< Output Data Rate = 15 Hz */
|
||||
#define LSM303DLHC_ODR_30_HZ ((uint8_t) 0x14) /*!< Output Data Rate = 30 Hz */
|
||||
#define LSM303DLHC_ODR_75_HZ ((uint8_t) 0x18) /*!< Output Data Rate = 75 Hz */
|
||||
#define LSM303DLHC_ODR_220_HZ ((uint8_t) 0x1C) /*!< Output Data Rate = 220 Hz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Full_Scale
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_FS_1_3_GA ((uint8_t) 0x20) /*!< Full scale = <20>1.3 Gauss */
|
||||
#define LSM303DLHC_FS_1_9_GA ((uint8_t) 0x40) /*!< Full scale = <20>1.9 Gauss */
|
||||
#define LSM303DLHC_FS_2_5_GA ((uint8_t) 0x60) /*!< Full scale = <20>2.5 Gauss */
|
||||
#define LSM303DLHC_FS_4_0_GA ((uint8_t) 0x80) /*!< Full scale = <20>4.0 Gauss */
|
||||
#define LSM303DLHC_FS_4_7_GA ((uint8_t) 0xA0) /*!< Full scale = <20>4.7 Gauss */
|
||||
#define LSM303DLHC_FS_5_6_GA ((uint8_t) 0xC0) /*!< Full scale = <20>5.6 Gauss */
|
||||
#define LSM303DLHC_FS_8_1_GA ((uint8_t) 0xE0) /*!< Full scale = <20>8.1 Gauss */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup Magnetometer_Sensitivity
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_M_SENSITIVITY_XY_1_3Ga 1100 /*!< magnetometer X Y axes sensitivity for 1.3 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_XY_1_9Ga 855 /*!< magnetometer X Y axes sensitivity for 1.9 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_XY_2_5Ga 670 /*!< magnetometer X Y axes sensitivity for 2.5 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_XY_4Ga 450 /*!< magnetometer X Y axes sensitivity for 4 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_XY_4_7Ga 400 /*!< magnetometer X Y axes sensitivity for 4.7 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_XY_5_6Ga 330 /*!< magnetometer X Y axes sensitivity for 5.6 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_XY_8_1Ga 230 /*!< magnetometer X Y axes sensitivity for 8.1 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_Z_1_3Ga 980 /*!< magnetometer Z axis sensitivity for 1.3 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_Z_1_9Ga 760 /*!< magnetometer Z axis sensitivity for 1.9 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_Z_2_5Ga 600 /*!< magnetometer Z axis sensitivity for 2.5 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_Z_4Ga 400 /*!< magnetometer Z axis sensitivity for 4 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_Z_4_7Ga 355 /*!< magnetometer Z axis sensitivity for 4.7 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_Z_5_6Ga 295 /*!< magnetometer Z axis sensitivity for 5.6 Ga full scale [LSB/Ga] */
|
||||
#define LSM303DLHC_M_SENSITIVITY_Z_8_1Ga 205 /*!< magnetometer Z axis sensitivity for 8.1 Ga full scale [LSB/Ga] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Working_Mode
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_CONTINUOS_CONVERSION ((uint8_t) 0x00) /*!< Continuous-Conversion Mode */
|
||||
#define LSM303DLHC_SINGLE_CONVERSION ((uint8_t) 0x01) /*!< Single-Conversion Mode */
|
||||
#define LSM303DLHC_SLEEP ((uint8_t) 0x02) /*!< Sleep Mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Mag_Temperature_Sensor
|
||||
* @{
|
||||
*/
|
||||
#define LSM303DLHC_TEMPSENSOR_ENABLE ((uint8_t) 0x80) /*!< Temp sensor Enable */
|
||||
#define LSM303DLHC_TEMPSENSOR_DISABLE ((uint8_t) 0x00) /*!< Temp sensor Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LSM303DLHC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* ACC functions */
|
||||
void LSM303DLHC_AccInit(uint16_t InitStruct);
|
||||
void LSM303DLHC_AccDeInit(void);
|
||||
uint8_t LSM303DLHC_AccReadID(void);
|
||||
void LSM303DLHC_AccRebootCmd(void);
|
||||
void LSM303DLHC_AccFilterConfig(uint8_t FilterStruct);
|
||||
void LSM303DLHC_AccFilterCmd(uint8_t HighPassFilterState);
|
||||
void LSM303DLHC_AccReadXYZ(int16_t* pData);
|
||||
void LSM303DLHC_AccFilterClickCmd(uint8_t HighPassFilterClickState);
|
||||
void LSM303DLHC_AccIT1Enable(uint8_t LSM303DLHC_IT);
|
||||
void LSM303DLHC_AccIT1Disable(uint8_t LSM303DLHC_IT);
|
||||
void LSM303DLHC_AccIT2Enable(uint8_t LSM303DLHC_IT);
|
||||
void LSM303DLHC_AccIT2Disable(uint8_t LSM303DLHC_IT);
|
||||
void LSM303DLHC_AccINT1InterruptEnable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303DLHC_AccINT1InterruptDisable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303DLHC_AccINT2InterruptEnable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303DLHC_AccINT2InterruptDisable(uint8_t ITCombination, uint8_t ITAxes);
|
||||
void LSM303DLHC_AccClickITEnable(uint8_t ITClick);
|
||||
void LSM303DLHC_AccClickITDisable(uint8_t ITClick);
|
||||
void LSM303DLHC_AccZClickITConfig(void);
|
||||
|
||||
/* COMPASS / ACCELERO IO functions */
|
||||
void COMPASSACCELERO_IO_Init(void);
|
||||
void COMPASSACCELERO_IO_ITConfig(void);
|
||||
void COMPASSACCELERO_IO_Write(uint16_t DeviceAddr, uint8_t RegisterAddr, uint8_t Value);
|
||||
uint8_t COMPASSACCELERO_IO_Read(uint16_t DeviceAddr, uint8_t RegisterAddr);
|
||||
|
||||
/* ACC driver structure */
|
||||
extern ACCELERO_DrvTypeDef Lsm303dlhcDrv;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LSM303DLHC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,348 @@
|
||||
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
|
||||
<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
|
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|
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|
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|
||||
<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
|
||||
|
||||
|
||||
<link rel="File-List" href="Library_files/filelist.xml">
|
||||
|
||||
|
||||
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32F401-Discovery Board Drivers</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<style>
|
||||
<!--
|
||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{mso-style-parent:"";
|
||||
margin:0in;
|
||||
margin-bottom:.0001pt;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
h2
|
||||
{mso-style-next:Normal;
|
||||
margin-top:12.0pt;
|
||||
margin-right:0in;
|
||||
margin-bottom:3.0pt;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
page-break-after:avoid;
|
||||
mso-outline-level:2;
|
||||
font-size:14.0pt;
|
||||
font-family:Arial;
|
||||
font-weight:bold;
|
||||
font-style:italic;}
|
||||
a:link, span.MsoHyperlink
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
a:visited, span.MsoHyperlinkFollowed
|
||||
{color:blue;
|
||||
text-decoration:underline;
|
||||
text-underline:single;}
|
||||
p
|
||||
{mso-margin-top-alt:auto;
|
||||
margin-right:0in;
|
||||
mso-margin-bottom-alt:auto;
|
||||
margin-left:0in;
|
||||
mso-pagination:widow-orphan;
|
||||
font-size:12.0pt;
|
||||
font-family:"Times New Roman";
|
||||
mso-fareast-font-family:"Times New Roman";}
|
||||
@page Section1
|
||||
{size:8.5in 11.0in;
|
||||
margin:1.0in 1.25in 1.0in 1.25in;
|
||||
mso-header-margin:.5in;
|
||||
mso-footer-margin:.5in;
|
||||
mso-paper-source:0;}
|
||||
div.Section1
|
||||
{page:Section1;}
|
||||
-->
|
||||
</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]-->
|
||||
<meta content="MCD Application Team" name="author"></head><body link="blue" vlink="blue">
|
||||
<div class="Section1">
|
||||
<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
|
||||
</o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="vertical-align: top;">
|
||||
<p class="MsoNormal"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../Release_Notes.html">Back to Release page</a><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for STM32F411E-Discovery Board Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
|
||||
<p class="MsoNormal" style="line-height: normal;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
||||
</span><span style="font-size: 10pt;"><EFBFBD> </span><span style="font-size: 10pt; font-family: Arial; color: black;">2017 STMicroelectronics</span></p>
|
||||
|
||||
|
||||
<p class="MsoNormal" align="center"> <img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_rnc_img0" src="../../../_htmresc/st_logo.png"> </p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
<tr>
|
||||
<td style="padding: 0cm;" valign="top"><span style="font-family: Arial;"><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span><p class="MsoListParagraph" style="text-align: left;"><span style="font-family: "Arial",sans-serif; font-size: 11pt;">The
|
||||
BSP (Board Specific Package) drivers are parts of the STM32Cube package
|
||||
based on the HAL drivers and provide a set of high level APIs relative
|
||||
to the hardware components and features in the evaluation boards,
|
||||
discovery kits and nucleo boards coming with the STM32Cube package for
|
||||
a given STM32 serie.</span></p><p class="MsoListParagraph" style="text-align: left;"><span style="font-family: "Arial",sans-serif; font-size: 11pt;">The
|
||||
BSP drivers allow a quick access to the boards’ services using high
|
||||
level APIs and without any specific configuration as the link with the
|
||||
HAL and the external components is done in intrinsic within the
|
||||
drivers. <br></span></p><p class="MsoListParagraph" style="text-align: left;"><span style="font-family: "Arial",sans-serif; font-size: 11pt;">From
|
||||
project settings points of view, user has only to add the necessary
|
||||
driver’s files in the workspace and call the needed functions from
|
||||
examples. However some low level configuration functions are weak and
|
||||
can be overridden by the applications if user wants to change some BSP
|
||||
drivers default behavior.</span></p><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Update History</span></h2>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 215px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.4 / 19-January-2021 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<ul style="list-style-type: square;">
|
||||
<li><span style="font-size: 10pt; font-family: Verdana;">Update accelerometer and gyroscope drivers to support new I2G4250D and LSM303AGR compenents.</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"></span></li>
|
||||
</ul>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 215px;"><span style="font-size: 10pt; font-family: Arial; color: white;">1.0.3 / 21-September-2017 <o:p></o:p></span></h3>
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span>
|
||||
|
||||
|
||||
<ul style="list-style-type: square;"><li><span style="font-size: 10pt; font-family: Verdana;">Remove date & version</span></li><li><span style="font-family: Verdana; font-size: 10pt;">Add general description of BSP drivers</span></li><li><span style="font-size: 10pt; font-family: Verdana;">stm32f411e_</span><span style="font-size: 10pt; font-family: Verdana;">discovery</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">_audio.c/.h:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Aligned with PDM library v3.0.0 </span></li></ul><li><span style="font-family: Verdana; font-size: 10pt;"><span style="font-style: italic; font-weight: bold; text-decoration: underline;">Notes:</span> <br>
|
||||
</span></li><ul><li><span style="font-family: Verdana; font-size: 10pt;">This version must be used with v3.0.0 of PDM library</span></li></ul></ul>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 206px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2 / 27-January-2017 <o:p></o:p></span></h3>
|
||||
|
||||
|
||||
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; list-style-type: square;"><span style="font-size: 10pt; font-family: Verdana;">Replace __PPP_CLK_ENABLE/DISABLE with __HAL_RCC_PPP</span><span style="font-size: 10pt; font-family: Verdana;">_ENABLE/DISABLE</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; list-style-type: square;"><span style="font-size: 10pt; font-family: Verdana;">Align audio drivers to the BSP spec:<br>
|
||||
</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add BSP_AUDIO_OUT_ClockConfig, BSP_AUDIO_OUT_MspInit and BSP_AUDIO_OUT_MspDeInit as weak functions</span></li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add BSP_AUDIO_IN_ClockConfig, BSP_AUDIO_IN_MspInit and BSP_AUDIO_IN_MspDeInit as weak functions</span></li>
|
||||
</ul>
|
||||
</ul>
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 212px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 12-January-2016</span></h3>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes</span></u></b><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"><o:p></o:p></span></u></b></p>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">General updates to fix doxygen errors</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add STM32F4-Discovery_BSP_User_Manual.chm file</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f411e_discovery_audio.c</span><span style="font-size: 10pt; font-family: Verdana;"> </span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">BSP_AUDIO_OUT_Init() update to configure correctly the PLL I2S parameters</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 500pt; width: 217px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 12-November-2015</span></h3>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">First official version of the<span style="font-weight: bold; font-style: italic;"> STM32F411E-Discovery Board Drivers</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
|
||||
<div style="text-align: justify;">
|
||||
<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are
|
||||
met:</span><br>
|
||||
</font>
|
||||
<ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
|
||||
in binary form must reproduce the above copyright notice, this list of
|
||||
conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
|
||||
</font>
|
||||
</li></ol>
|
||||
<font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";"></span><br>
|
||||
<span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
|
||||
|
||||
</div>
|
||||
<span style="font-family: "Verdana","sans-serif";"></span></div>
|
||||
<span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span> <b><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></b>
|
||||
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<div style="margin-left: 160px;"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span></div>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
|
||||
</body></html>
|
||||
Binary file not shown.
@@ -0,0 +1,746 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f411e_discovery.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides set of firmware functions to manage LEDs and
|
||||
* push-button available on STM32F411-Discovery Kit from STMicroelectronics.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f411e_discovery.h"
|
||||
|
||||
/** @defgroup BSP BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY STM32F411E discovery
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_discovery_LOW_LEVEL STM32F411E discovery LOW LEVEL
|
||||
* @brief This file provides set of firmware functions to manage Leds and push-button
|
||||
* available on STM32F411-Discovery Kit from STMicroelectronics.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_discovery_LOW_LEVEL_Private_TypesDefinitions STM32F411E discovery LOW LEVEL Privat TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_discovery_LOW_LEVEL_Private_Defines STM32F411E discovery LOW LEVEL Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32F411E DISCO BSP Driver version number V1.0.4
|
||||
*/
|
||||
#define __STM32F411E_DISCO_BSP_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F411E_DISCO_BSP_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32F411E_DISCO_BSP_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
|
||||
#define __STM32F411E_DISCO_BSP_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F411E_DISCO_BSP_VERSION ((__STM32F411E_DISCO_BSP_VERSION_MAIN << 24)\
|
||||
|(__STM32F411E_DISCO_BSP_VERSION_SUB1 << 16)\
|
||||
|(__STM32F411E_DISCO_BSP_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F411E_DISCO_BSP_VERSION_RC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_discovery_LOW_LEVEL_Private_Macros STM32F411E discovery LOW LEVEL Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_discovery_LOW_LEVEL_Private_Variables STM32F411E discovery LOW LEVEL Private Variables
|
||||
* @{
|
||||
*/
|
||||
GPIO_TypeDef* GPIO_PORT[LEDn] = {LED4_GPIO_PORT,
|
||||
LED3_GPIO_PORT,
|
||||
LED5_GPIO_PORT,
|
||||
LED6_GPIO_PORT};
|
||||
|
||||
const uint16_t GPIO_PIN[LEDn] = {LED4_PIN,
|
||||
LED3_PIN,
|
||||
LED5_PIN,
|
||||
LED6_PIN};
|
||||
|
||||
GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {KEY_BUTTON_GPIO_PORT};
|
||||
const uint16_t BUTTON_PIN[BUTTONn] = {KEY_BUTTON_PIN};
|
||||
const uint8_t BUTTON_IRQn[BUTTONn] = {KEY_BUTTON_EXTI_IRQn};
|
||||
|
||||
uint32_t I2cxTimeout = I2Cx_TIMEOUT_MAX; /*<! Value of Timeout when I2C communication fails */
|
||||
uint32_t SpixTimeout = SPIx_TIMEOUT_MAX; /*<! Value of Timeout when SPI communication fails */
|
||||
|
||||
static I2C_HandleTypeDef I2cHandle;
|
||||
static SPI_HandleTypeDef SpiHandle;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_discovery_LOW_LEVEL_Private_FunctionPrototypes STM32F411E discovery LOW LEVEL Private FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/* I2Cx bus function */
|
||||
static void I2Cx_Init(void);
|
||||
static void I2Cx_WriteData(uint16_t Addr, uint8_t Reg, uint8_t Value);
|
||||
static uint8_t I2Cx_ReadData(uint16_t Addr, uint8_t Reg);
|
||||
static void I2Cx_Error (void);
|
||||
static void I2Cx_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* SPIx bus function */
|
||||
static void SPIx_Init(void);
|
||||
static uint8_t SPIx_WriteRead(uint8_t byte);
|
||||
static void SPIx_Error (void);
|
||||
static void SPIx_MspInit(SPI_HandleTypeDef *hspi);
|
||||
|
||||
/* Link function for GYRO peripheral */
|
||||
void GYRO_IO_Init(void);
|
||||
void GYRO_IO_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
|
||||
void GYRO_IO_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);
|
||||
|
||||
/* Link functions for AUDIO */
|
||||
void AUDIO_IO_Init(void);
|
||||
void AUDIO_IO_DeInit(void);
|
||||
void AUDIO_IO_Write(uint8_t Addr, uint8_t Reg, uint8_t Value);
|
||||
uint8_t AUDIO_IO_Read(uint8_t Addr, uint8_t Reg);
|
||||
|
||||
/* Link function for COMPASS / ACCELERO peripheral */
|
||||
void COMPASSACCELERO_IO_Init(void);
|
||||
void COMPASSACCELERO_IO_ITConfig(void);
|
||||
void COMPASSACCELERO_IO_Write(uint16_t DeviceAddr, uint8_t RegisterAddr, uint8_t Value);
|
||||
uint8_t COMPASSACCELERO_IO_Read(uint16_t DeviceAddr, uint8_t RegisterAddr);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_discovery_LOW_LEVEL_Private_Functions STM32F411E discovery LOW LEVEL Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This method returns the STM32F411 DISCO BSP Driver revision
|
||||
* @retval version: 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t BSP_GetVersion(void)
|
||||
{
|
||||
return __STM32F411E_DISCO_BSP_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures LED GPIO.
|
||||
* @param Led: Specifies the Led to be configured.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED4
|
||||
* @arg LED3
|
||||
* @arg LED5
|
||||
* @arg LED6
|
||||
*/
|
||||
void BSP_LED_Init(Led_TypeDef Led)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
/* Enable the GPIO_LED Clock */
|
||||
LEDx_GPIO_CLK_ENABLE(Led);
|
||||
|
||||
/* Configure the GPIO_LED pin */
|
||||
GPIO_InitStruct.Pin = GPIO_PIN[Led];
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
|
||||
|
||||
HAL_GPIO_Init(GPIO_PORT[Led], &GPIO_InitStruct);
|
||||
|
||||
HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED On.
|
||||
* @param Led: Specifies the Led to be set on.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED4
|
||||
* @arg LED3
|
||||
* @arg LED5
|
||||
* @arg LED6
|
||||
*/
|
||||
void BSP_LED_On(Led_TypeDef Led)
|
||||
{
|
||||
HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_SET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Turns selected LED Off.
|
||||
* @param Led: Specifies the Led to be set off.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED4
|
||||
* @arg LED3
|
||||
* @arg LED5
|
||||
* @arg LED6
|
||||
*/
|
||||
void BSP_LED_Off(Led_TypeDef Led)
|
||||
{
|
||||
HAL_GPIO_WritePin(GPIO_PORT[Led], GPIO_PIN[Led], GPIO_PIN_RESET);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the selected LED.
|
||||
* @param Led: Specifies the Led to be toggled.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg LED4
|
||||
* @arg LED3
|
||||
* @arg LED5
|
||||
* @arg LED6
|
||||
*/
|
||||
void BSP_LED_Toggle(Led_TypeDef Led)
|
||||
{
|
||||
HAL_GPIO_TogglePin(GPIO_PORT[Led], GPIO_PIN[Led]);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures Button GPIO and EXTI Line.
|
||||
* @param Button: Specifies the Button to be configured.
|
||||
* This parameter should be: BUTTON_KEY
|
||||
* @param ButtonMode: Specifies Button mode.
|
||||
* This parameter can be one of following parameters:
|
||||
* @arg BUTTON_MODE_GPIO: Button will be used as simple IO
|
||||
* @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt
|
||||
* generation capability
|
||||
*/
|
||||
void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
/* Enable the BUTTON Clock */
|
||||
BUTTONx_GPIO_CLK_ENABLE(Button);
|
||||
|
||||
if(ButtonMode == BUTTON_MODE_GPIO)
|
||||
{
|
||||
/* Configure Button pin as input */
|
||||
GPIO_InitStruct.Pin = BUTTON_PIN[Button];
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);
|
||||
}
|
||||
|
||||
if(ButtonMode == BUTTON_MODE_EXTI)
|
||||
{
|
||||
/* Configure Button pin as input with External interrupt */
|
||||
GPIO_InitStruct.Pin = BUTTON_PIN[Button];
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
||||
HAL_GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStruct);
|
||||
|
||||
/* Enable and set Button EXTI Interrupt to the lowest priority */
|
||||
HAL_NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F, 0x00);
|
||||
HAL_NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button]));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the selected Button state.
|
||||
* @param Button: Specifies the Button to be checked.
|
||||
* This parameter should be: BUTTON_KEY
|
||||
* @retval The Button GPIO pin value.
|
||||
*/
|
||||
uint32_t BSP_PB_GetState(Button_TypeDef Button)
|
||||
{
|
||||
return HAL_GPIO_ReadPin(BUTTON_PORT[Button], BUTTON_PIN[Button]);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
BUS OPERATIONS
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************* I2C Routines *********************************/
|
||||
|
||||
/**
|
||||
* @brief I2Cx Bus initialization.
|
||||
*/
|
||||
static void I2Cx_Init(void)
|
||||
{
|
||||
if(HAL_I2C_GetState(&I2cHandle) == HAL_I2C_STATE_RESET)
|
||||
{
|
||||
I2cHandle.Instance = DISCOVERY_I2Cx;
|
||||
I2cHandle.Init.OwnAddress1 = 0x43;
|
||||
I2cHandle.Init.ClockSpeed = I2Cx_MAX_COMMUNICATION_FREQ;
|
||||
I2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
||||
I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
||||
I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
|
||||
I2cHandle.Init.OwnAddress2 = 0x00;
|
||||
I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
|
||||
I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED;
|
||||
|
||||
/* Init the I2C */
|
||||
I2Cx_MspInit(&I2cHandle);
|
||||
HAL_I2C_Init(&I2cHandle);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a value in a register of the device through BUS.
|
||||
* @param Addr: Device address on BUS Bus.
|
||||
* @param Reg: The target register address to write
|
||||
* @param Value: The target register value to be written
|
||||
*/
|
||||
static void I2Cx_WriteData(uint16_t Addr, uint8_t Reg, uint8_t Value)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
status = HAL_I2C_Mem_Write(&I2cHandle, Addr, (uint16_t)Reg, I2C_MEMADD_SIZE_8BIT, &Value, 1, I2cxTimeout);
|
||||
|
||||
/* Check the communication status */
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* Execute user timeout callback */
|
||||
I2Cx_Error();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a register of the device through BUS.
|
||||
* @param Addr: Device address on BUS Bus.
|
||||
* @param Reg: The target register address to write
|
||||
* @retval Data read at register address
|
||||
*/
|
||||
static uint8_t I2Cx_ReadData(uint16_t Addr, uint8_t Reg)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint8_t value = 0;
|
||||
|
||||
status = HAL_I2C_Mem_Read(&I2cHandle, Addr, Reg, I2C_MEMADD_SIZE_8BIT, &value, 1, I2cxTimeout);
|
||||
|
||||
/* Check the communication status */
|
||||
if(status != HAL_OK)
|
||||
{
|
||||
/* Execute user timeout callback */
|
||||
I2Cx_Error();
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief I2Cx error treatment function.
|
||||
*/
|
||||
static void I2Cx_Error(void)
|
||||
{
|
||||
/* De-initialize the I2C comunication BUS */
|
||||
HAL_I2C_DeInit(&I2cHandle);
|
||||
|
||||
/* Re- Initiaize the I2C comunication BUS */
|
||||
I2Cx_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief I2Cx MSP Init.
|
||||
* @param hi2c: I2C handle
|
||||
*/
|
||||
static void I2Cx_MspInit(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Enable the I2C peripheral */
|
||||
DISCOVERY_I2Cx_CLOCK_ENABLE();
|
||||
|
||||
/* Enable SCK and SDA GPIO clocks */
|
||||
DISCOVERY_I2Cx_GPIO_CLK_ENABLE();
|
||||
|
||||
/* I2Cx SD1 & SCK pin configuration */
|
||||
GPIO_InitStructure.Pin = DISCOVERY_I2Cx_SDA_PIN | DISCOVERY_I2Cx_SCL_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_OD;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
|
||||
GPIO_InitStructure.Alternate = DISCOVERY_I2Cx_AF;
|
||||
|
||||
HAL_GPIO_Init(DISCOVERY_I2Cx_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
/* Force the I2C peripheral clock reset */
|
||||
DISCOVERY_I2Cx_FORCE_RESET();
|
||||
|
||||
/* Release the I2C peripheral clock reset */
|
||||
DISCOVERY_I2Cx_RELEASE_RESET();
|
||||
|
||||
/* Enable and set I2Cx Interrupt to the lowest priority */
|
||||
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_EV_IRQn, 0x0F, 0);
|
||||
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_EV_IRQn);
|
||||
|
||||
/* Enable and set I2Cx Interrupt to the lowest priority */
|
||||
HAL_NVIC_SetPriority(DISCOVERY_I2Cx_ER_IRQn, 0x0F, 0);
|
||||
HAL_NVIC_EnableIRQ(DISCOVERY_I2Cx_ER_IRQn);
|
||||
}
|
||||
|
||||
/******************************* SPI Routines**********************************/
|
||||
|
||||
/**
|
||||
* @brief SPIx Bus initialization.
|
||||
*/
|
||||
static void SPIx_Init(void)
|
||||
{
|
||||
if(HAL_SPI_GetState(&SpiHandle) == HAL_SPI_STATE_RESET)
|
||||
{
|
||||
/* SPI Configuration */
|
||||
SpiHandle.Instance = DISCOVERY_SPIx;
|
||||
/* SPI baudrate is set to 5.6 MHz (PCLK2/SPI_BaudRatePrescaler = 90/16 = 5.625 MHz)
|
||||
to verify these constraints:
|
||||
ILI9341 LCD SPI interface max baudrate is 10MHz for write and 6.66MHz for read
|
||||
L3GD20 SPI interface max baudrate is 10MHz for write/read
|
||||
PCLK2 frequency is set to 90 MHz
|
||||
*/
|
||||
SpiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
|
||||
SpiHandle.Init.Direction = SPI_DIRECTION_2LINES;
|
||||
SpiHandle.Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||
SpiHandle.Init.CLKPolarity = SPI_POLARITY_LOW;
|
||||
SpiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
|
||||
SpiHandle.Init.CRCPolynomial = 7;
|
||||
SpiHandle.Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||||
SpiHandle.Init.NSS = SPI_NSS_SOFT;
|
||||
SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED;
|
||||
SpiHandle.Init.Mode = SPI_MODE_MASTER;
|
||||
|
||||
SPIx_MspInit(&SpiHandle);
|
||||
HAL_SPI_Init(&SpiHandle);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends a Byte through the SPI interface and return the Byte received
|
||||
* from the SPI bus.
|
||||
* @param Byte: Byte send.
|
||||
* @retval The received byte value
|
||||
*/
|
||||
static uint8_t SPIx_WriteRead(uint8_t Byte)
|
||||
{
|
||||
uint8_t receivedbyte = 0;
|
||||
|
||||
/* Send a Byte through the SPI peripheral */
|
||||
/* Read byte from the SPI bus */
|
||||
if(HAL_SPI_TransmitReceive(&SpiHandle, (uint8_t*) &Byte, (uint8_t*) &receivedbyte, 1, SpixTimeout) != HAL_OK)
|
||||
{
|
||||
SPIx_Error();
|
||||
}
|
||||
|
||||
return receivedbyte;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SPIx error treatment function.
|
||||
*/
|
||||
static void SPIx_Error (void)
|
||||
{
|
||||
/* De-initialize the SPI comunication BUS */
|
||||
HAL_SPI_DeInit(&SpiHandle);
|
||||
|
||||
/* Re-Initiaize the SPI comunication BUS */
|
||||
SPIx_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SPI MSP Init.
|
||||
* @param hspi: SPI handle
|
||||
*/
|
||||
static void SPIx_MspInit(SPI_HandleTypeDef *hspi)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Enable SPIx clock */
|
||||
DISCOVERY_SPIx_CLOCK_ENABLE();
|
||||
|
||||
/* Enable SPIx GPIO clock */
|
||||
DISCOVERY_SPIx_GPIO_CLK_ENABLE();
|
||||
|
||||
/* Configure SPIx SCK, MOSI and MISO */
|
||||
GPIO_InitStructure.Pin = (DISCOVERY_SPIx_SCK_PIN | DISCOVERY_SPIx_MOSI_PIN | DISCOVERY_SPIx_MISO_PIN);
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_PULLDOWN;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM;
|
||||
GPIO_InitStructure.Alternate = DISCOVERY_SPIx_AF;
|
||||
HAL_GPIO_Init(DISCOVERY_SPIx_GPIO_PORT, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
LINK OPERATIONS
|
||||
*******************************************************************************/
|
||||
|
||||
/********************************* LINK GYROSCOPE *****************************/
|
||||
/**
|
||||
* @brief Configures the GYRO SPI interface.
|
||||
*/
|
||||
void GYRO_IO_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Configure the Gyroscope Control pins ------------------------------------*/
|
||||
/* Enable CS GPIO clock and Configure GPIO PIN for Gyroscope Chip select */
|
||||
GYRO_CS_GPIO_CLK_ENABLE();
|
||||
GPIO_InitStructure.Pin = GYRO_CS_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_MEDIUM;
|
||||
HAL_GPIO_Init(GYRO_CS_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
/* Deselect : Chip Select high */
|
||||
GYRO_CS_HIGH();
|
||||
|
||||
/* Enable INT1, INT2 GPIO clock and Configure GPIO PINs to detect Interrupts */
|
||||
GYRO_INT_GPIO_CLK_ENABLE();
|
||||
GPIO_InitStructure.Pin = GYRO_INT1_PIN | GYRO_INT2_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
|
||||
GPIO_InitStructure.Pull= GPIO_NOPULL;
|
||||
HAL_GPIO_Init(GYRO_INT_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
SPIx_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes one byte to the GYRO.
|
||||
* @param pBuffer: pointer to the buffer containing the data to be written to the GYRO.
|
||||
* @param WriteAddr : GYRO's internal address to write to.
|
||||
* @param NumByteToWrite: Number of bytes to write.
|
||||
*/
|
||||
void GYRO_IO_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite)
|
||||
{
|
||||
/* Configure the MS bit:
|
||||
- When 0, the address will remain unchanged in multiple read/write commands.
|
||||
- When 1, the address will be auto incremented in multiple read/write commands.
|
||||
*/
|
||||
if(NumByteToWrite > 0x01)
|
||||
{
|
||||
WriteAddr |= (uint8_t)MULTIPLEBYTE_CMD;
|
||||
}
|
||||
/* Set chip select Low at the start of the transmission */
|
||||
GYRO_CS_LOW();
|
||||
|
||||
/* Send the Address of the indexed register */
|
||||
SPIx_WriteRead(WriteAddr);
|
||||
|
||||
/* Send the data that will be written into the device (MSB First) */
|
||||
while(NumByteToWrite >= 0x01)
|
||||
{
|
||||
SPIx_WriteRead(*pBuffer);
|
||||
NumByteToWrite--;
|
||||
pBuffer++;
|
||||
}
|
||||
|
||||
/* Set chip select High at the end of the transmission */
|
||||
GYRO_CS_HIGH();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a block of data from the GYRO.
|
||||
* @param pBuffer: pointer to the buffer that receives the data read from the GYRO.
|
||||
* @param ReadAddr: GYRO's internal address to read from.
|
||||
* @param NumByteToRead: Number of bytes to read from the GYRO.
|
||||
*/
|
||||
void GYRO_IO_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead)
|
||||
{
|
||||
if(NumByteToRead > 0x01)
|
||||
{
|
||||
ReadAddr |= (uint8_t)(READWRITE_CMD | MULTIPLEBYTE_CMD);
|
||||
}
|
||||
else
|
||||
{
|
||||
ReadAddr |= (uint8_t)READWRITE_CMD;
|
||||
}
|
||||
|
||||
/* Set chip select Low at the start of the transmission */
|
||||
GYRO_CS_LOW();
|
||||
|
||||
/* Send the Address of the indexed register */
|
||||
SPIx_WriteRead(ReadAddr);
|
||||
|
||||
/* Receive the data that will be read from the device (MSB First) */
|
||||
while(NumByteToRead > 0x00)
|
||||
{
|
||||
/* Send dummy byte (0x00) to generate the SPI clock to GYRO (Slave device) */
|
||||
*pBuffer = SPIx_WriteRead(DUMMY_BYTE);
|
||||
NumByteToRead--;
|
||||
pBuffer++;
|
||||
}
|
||||
|
||||
/* Set chip select High at the end of the transmission */
|
||||
GYRO_CS_HIGH();
|
||||
}
|
||||
|
||||
/********************************* LINK AUDIO *********************************/
|
||||
|
||||
/**
|
||||
* @brief Initializes Audio low level.
|
||||
*/
|
||||
void AUDIO_IO_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
/* Enable Reset GPIO Clock */
|
||||
AUDIO_RESET_GPIO_CLK_ENABLE();
|
||||
|
||||
/* Audio reset pin configuration -------------------------------------------*/
|
||||
GPIO_InitStruct.Pin = AUDIO_RESET_PIN;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
HAL_GPIO_Init(AUDIO_RESET_GPIO, &GPIO_InitStruct);
|
||||
|
||||
I2Cx_Init();
|
||||
|
||||
/* Power Down the codec */
|
||||
CODEC_AUDIO_POWER_OFF();
|
||||
|
||||
/* Wait for a delay to insure registers erasing */
|
||||
HAL_Delay(5);
|
||||
|
||||
/* Power on the codec */
|
||||
CODEC_AUDIO_POWER_ON();
|
||||
|
||||
/* Wait for a delay to insure registers erasing */
|
||||
HAL_Delay(5);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes Audio low level.
|
||||
*/
|
||||
void AUDIO_IO_DeInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes a single data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Reg address
|
||||
* @param Value: Data to be written
|
||||
*/
|
||||
void AUDIO_IO_Write (uint8_t Addr, uint8_t Reg, uint8_t Value)
|
||||
{
|
||||
I2Cx_WriteData(Addr, Reg, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a single data.
|
||||
* @param Addr: I2C address
|
||||
* @param Reg: Reg address
|
||||
* @retval Data to be read
|
||||
*/
|
||||
uint8_t AUDIO_IO_Read (uint8_t Addr, uint8_t Reg)
|
||||
{
|
||||
return I2Cx_ReadData(Addr, Reg);
|
||||
}
|
||||
|
||||
/****************************** LINK ACCELEROMETER ****************************/
|
||||
|
||||
/**
|
||||
* @brief Configures COMPASS / ACCELERO I2C interface.
|
||||
*/
|
||||
void COMPASSACCELERO_IO_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Enable DRDY clock */
|
||||
ACCELERO_DRDY_GPIO_CLK_ENABLE();
|
||||
|
||||
/* MEMS DRDY pin configuration */
|
||||
GPIO_InitStructure.Pin = ACCELERO_DRDY_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(ACCELERO_DRDY_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
I2Cx_Init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures COMPASS / ACCELERO click IT.
|
||||
*/
|
||||
void COMPASSACCELERO_IO_ITConfig(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
/* Enable INT1 and INT2 GPIO clock */
|
||||
ACCELERO_INT_GPIO_CLK_ENABLE();
|
||||
|
||||
/* Configure GPIO PINs to detect Interrupts */
|
||||
GPIO_InitStructure.Pin = ACCELERO_INT1_PIN | ACCELERO_INT2_PIN;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING;
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_FAST;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
HAL_GPIO_Init(ACCELERO_INT_GPIO_PORT, &GPIO_InitStructure);
|
||||
|
||||
/* Enable and set COMPASS / ACCELERO Interrupt to the lowest priority */
|
||||
HAL_NVIC_SetPriority(ACCELERO_INT1_EXTI_IRQn, 0x0F, 0x00);
|
||||
HAL_NVIC_EnableIRQ(ACCELERO_INT1_EXTI_IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes one byte to the COMPASS / ACCELERO.
|
||||
* @param DeviceAddr: the slave address to be programmed
|
||||
* @param RegisterAddr: the COMPASS / ACCELERO register to be written
|
||||
* @param Value: Data to be written
|
||||
*/
|
||||
void COMPASSACCELERO_IO_Write(uint16_t DeviceAddr, uint8_t RegisterAddr, uint8_t Value)
|
||||
{
|
||||
/* Call I2Cx Read data bus function */
|
||||
I2Cx_WriteData(DeviceAddr, RegisterAddr, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads a block of data from the COMPASS / ACCELERO.
|
||||
* @param DeviceAddr: the slave address to be programmed(ACC_I2C_ADDRESS or MAG_I2C_ADDRESS).
|
||||
* @param RegisterAddr: the COMPASS / ACCELERO internal address register to read from
|
||||
* @retval COMPASS / ACCELERO register value
|
||||
*/
|
||||
uint8_t COMPASSACCELERO_IO_Read(uint16_t DeviceAddr, uint8_t RegisterAddr)
|
||||
{
|
||||
/* Call I2Cx Read data bus function */
|
||||
return I2Cx_ReadData(DeviceAddr, RegisterAddr);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,311 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f411e_discovery.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains definitions for STM32F401-Discovery Kit's Leds and
|
||||
* push-button hardware resources.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F411E_DISCOVERY_H
|
||||
#define __STM32F411E_DISCOVERY_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL STM32F411E DISCOVERY HLOW LEVEL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL_Exported_Types STM32F411E DISCOVERY HLOW LEVEL Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
LED4 = 0,
|
||||
LED3 = 1,
|
||||
LED5 = 2,
|
||||
LED6 = 3
|
||||
}Led_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_KEY = 0,
|
||||
}Button_TypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUTTON_MODE_GPIO = 0,
|
||||
BUTTON_MODE_EXTI = 1
|
||||
}ButtonMode_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL_Exported_Constants STM32F411E DISCOVERY HLOW LEVEL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define for STM32F411E_DISCOVERY board
|
||||
*/
|
||||
#if !defined (USE_STM32F411E_DISCO)
|
||||
#define USE_STM32F411E_DISCO
|
||||
#endif
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL_LED STM32F411E DISCOVERY HLOW LEVEL LED
|
||||
* @{
|
||||
*/
|
||||
#define LEDn 4
|
||||
|
||||
#define LED4_PIN GPIO_PIN_12
|
||||
#define LED4_GPIO_PORT GPIOD
|
||||
#define LED4_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define LED4_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
|
||||
|
||||
|
||||
#define LED3_PIN GPIO_PIN_13
|
||||
#define LED3_GPIO_PORT GPIOD
|
||||
#define LED3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define LED3_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
|
||||
|
||||
|
||||
#define LED5_PIN GPIO_PIN_14
|
||||
#define LED5_GPIO_PORT GPIOD
|
||||
#define LED5_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define LED5_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
|
||||
|
||||
|
||||
#define LED6_PIN GPIO_PIN_15
|
||||
#define LED6_GPIO_PORT GPIOD
|
||||
#define LED6_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define LED6_GPIO_CLK_DISABLE() __HAL_RCC_GPIOD_CLK_DISABLE()
|
||||
|
||||
#define LEDx_GPIO_CLK_ENABLE(__INDEX__) do{if((__INDEX__) == 0) LED4_GPIO_CLK_ENABLE(); else \
|
||||
if((__INDEX__) == 1) LED3_GPIO_CLK_ENABLE(); else \
|
||||
if((__INDEX__) == 2) LED5_GPIO_CLK_ENABLE(); else \
|
||||
if((__INDEX__) == 3) LED6_GPIO_CLK_ENABLE(); \
|
||||
}while(0)
|
||||
|
||||
#define LEDx_GPIO_CLK_DISABLE(__INDEX__) do{if((__INDEX__) == 0) LED4_GPIO_CLK_DISABLE(); else \
|
||||
if((__INDEX__) == 1) LED3_GPIO_CLK_DISABLE(); else \
|
||||
if((__INDEX__) == 2) LED5_GPIO_CLK_DISABLE(); else \
|
||||
if((__INDEX__) == 3) LED6_GPIO_CLK_DISABLE(); \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL_BUTTON STM32F411E DISCOVERY HLOW LEVEL BUTTON
|
||||
* @{
|
||||
*/
|
||||
#define BUTTONn 1
|
||||
|
||||
/**
|
||||
* @brief Wakeup push-button
|
||||
*/
|
||||
#define KEY_BUTTON_PIN GPIO_PIN_0
|
||||
#define KEY_BUTTON_GPIO_PORT GPIOA
|
||||
#define KEY_BUTTON_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
|
||||
#define KEY_BUTTON_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
|
||||
#define KEY_BUTTON_EXTI_IRQn EXTI0_IRQn
|
||||
|
||||
#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) do{if((__INDEX__) == 0) KEY_BUTTON_GPIO_CLK_ENABLE(); \
|
||||
}while(0)
|
||||
#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) do{if((__INDEX__) == 0) KEY_BUTTON_GPIO_CLK_DISABLE(); \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL_BUS STM32F411E DISCOVERY HLOW LEVEL BUS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*############################### I2Cx #######################################*/
|
||||
#define DISCOVERY_I2Cx I2C1
|
||||
#define DISCOVERY_I2Cx_CLOCK_ENABLE() __HAL_RCC_I2C1_CLK_ENABLE()
|
||||
#define DISCOVERY_I2Cx_GPIO_PORT GPIOB /* GPIOB */
|
||||
#define DISCOVERY_I2Cx_SCL_PIN GPIO_PIN_6 /* PB.06 */
|
||||
#define DISCOVERY_I2Cx_SDA_PIN GPIO_PIN_9 /* PB.09 */
|
||||
#define DISCOVERY_I2Cx_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
|
||||
#define DISCOVERY_I2Cx_GPIO_CLK_DISABLE() __HAL_RCC_GPIOB_CLK_DISABLE()
|
||||
#define DISCOVERY_I2Cx_AF GPIO_AF4_I2C1
|
||||
|
||||
#define DISCOVERY_I2Cx_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define DISCOVERY_I2Cx_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
/* I2C interrupt requests */
|
||||
#define DISCOVERY_I2Cx_EV_IRQn I2C1_EV_IRQn
|
||||
#define DISCOVERY_I2Cx_ER_IRQn I2C1_ER_IRQn
|
||||
|
||||
/* I2C speed and timeout max */
|
||||
#define I2Cx_TIMEOUT_MAX 0xA000 /*<! The value of the maximal timeout for I2C waiting loops */
|
||||
#define I2Cx_MAX_COMMUNICATION_FREQ ((uint32_t) 100000)
|
||||
|
||||
/*################################# SPI1 #####################################*/
|
||||
#define DISCOVERY_SPIx SPI1
|
||||
#define DISCOVERY_SPIx_CLOCK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE()
|
||||
#define DISCOVERY_SPIx_GPIO_PORT GPIOA /* GPIOA */
|
||||
#define DISCOVERY_SPIx_AF GPIO_AF5_SPI1
|
||||
#define DISCOVERY_SPIx_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
|
||||
#define DISCOVERY_SPIx_GPIO_CLK_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE()
|
||||
#define DISCOVERY_SPIx_SCK_PIN GPIO_PIN_5 /* PA.05 */
|
||||
#define DISCOVERY_SPIx_MISO_PIN GPIO_PIN_6 /* PA.06 */
|
||||
#define DISCOVERY_SPIx_MOSI_PIN GPIO_PIN_7 /* PA.07 */
|
||||
/* Maximum Timeout values for flags waiting loops. These timeouts are not based
|
||||
on accurate values, they just guarantee that the application will not remain
|
||||
stuck if the SPI communication is corrupted.
|
||||
You may modify these timeout values depending on CPU frequency and application
|
||||
conditions (interrupts routines ...). */
|
||||
#define SPIx_TIMEOUT_MAX ((uint32_t)0x1000)
|
||||
|
||||
/*################################ GYROSCOPE #################################*/
|
||||
/* Read/Write command */
|
||||
#define READWRITE_CMD ((uint8_t)0x80)
|
||||
/* Multiple byte read/write command */
|
||||
#define MULTIPLEBYTE_CMD ((uint8_t)0x40)
|
||||
/* Dummy Byte Send by the SPI Master device in order to generate the Clock to the Slave device */
|
||||
#define DUMMY_BYTE ((uint8_t)0x00)
|
||||
|
||||
/* Chip Select macro definition */
|
||||
#define GYRO_CS_LOW() HAL_GPIO_WritePin(GYRO_CS_GPIO_PORT, GYRO_CS_PIN, GPIO_PIN_RESET)
|
||||
#define GYRO_CS_HIGH() HAL_GPIO_WritePin(GYRO_CS_GPIO_PORT, GYRO_CS_PIN, GPIO_PIN_SET)
|
||||
|
||||
/**
|
||||
* @brief GYRO SPI Interface pins
|
||||
*/
|
||||
#define GYRO_CS_GPIO_PORT GPIOE /* GPIOE */
|
||||
#define GYRO_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
|
||||
#define GYRO_CS_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE()
|
||||
#define GYRO_CS_PIN GPIO_PIN_3 /* PE.03 */
|
||||
|
||||
#define GYRO_INT_GPIO_PORT GPIOE /* GPIOE */
|
||||
#define GYRO_INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
|
||||
#define GYRO_INT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE()
|
||||
#define GYRO_INT1_PIN GPIO_PIN_0 /* PE.00 */
|
||||
#define GYRO_INT1_EXTI_IRQn EXTI0_IRQn
|
||||
#define GYRO_INT2_PIN GPIO_PIN_1 /* PE.01 */
|
||||
#define GYRO_INT2_EXTI_IRQn EXTI1_IRQn
|
||||
|
||||
/*################################### AUDIO ##################################*/
|
||||
/**
|
||||
* @brief AUDIO I2C Interface pins
|
||||
*/
|
||||
/* Device I2C address */
|
||||
#define AUDIO_I2C_ADDRESS 0x94
|
||||
|
||||
/* Audio codec power on/off macro definition */
|
||||
#define CODEC_AUDIO_POWER_OFF() HAL_GPIO_WritePin(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, GPIO_PIN_RESET)
|
||||
#define CODEC_AUDIO_POWER_ON() HAL_GPIO_WritePin(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, GPIO_PIN_SET)
|
||||
|
||||
/* Audio Reset Pin definition */
|
||||
#define AUDIO_RESET_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
|
||||
#define AUDIO_RESET_PIN GPIO_PIN_4
|
||||
#define AUDIO_RESET_GPIO GPIOD
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*############################### ACCELEROMETER ##############################*/
|
||||
/**
|
||||
* @brief ACCELERO I2C1 Interface pins
|
||||
*/
|
||||
#define ACCELERO_DRDY_GPIO_PORT GPIOE /* GPIOE */
|
||||
#define ACCELERO_DRDY_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
|
||||
#define ACCELERO_DRDY_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE()
|
||||
#define ACCELERO_DRDY_PIN GPIO_PIN_2 /* PE.02 */
|
||||
#define ACCELERO_DRDY_EXTI_IRQn TAMP_STAMP_IRQn
|
||||
|
||||
#define ACCELERO_INT_GPIO_PORT GPIOE /* GPIOE */
|
||||
#define ACCELERO_INT_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
|
||||
#define ACCELERO_INT_GPIO_CLK_DISABLE() __HAL_RCC_GPIOE_CLK_DISABLE()
|
||||
#define ACCELERO_INT1_PIN GPIO_PIN_4 /* PE.04 */
|
||||
#define ACCELERO_INT1_EXTI_IRQn EXTI4_IRQn
|
||||
#define ACCELERO_INT2_PIN GPIO_PIN_5 /* PE.05 */
|
||||
#define ACCELERO_INT2_EXTI_IRQn EXTI9_5_IRQn
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL_Exported_Macros STM32F411E DISCOVERY HLOW LEVEL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup __STM32F411E_DISCOVERY_HLOW_LEVEL_Exported_Functions STM32F411E DISCOVERY HLOW LEVEL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t BSP_GetVersion(void);
|
||||
void BSP_LED_Init(Led_TypeDef Led);
|
||||
void BSP_LED_On(Led_TypeDef Led);
|
||||
void BSP_LED_Off(Led_TypeDef Led);
|
||||
void BSP_LED_Toggle(Led_TypeDef Led);
|
||||
void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode);
|
||||
uint32_t BSP_PB_GetState(Button_TypeDef Button);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F411E_DISCOVERY_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,254 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f411e_discovery_accelerometer.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides a set of functions needed to manage the
|
||||
* MEMS accelerometer available on STM32F411E-Discovery Kit.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f411e_discovery_accelerometer.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER STM32F411E DISCOVERY ACCELEROMETER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Private_TypesDefinitions STM32F411E DISCOVERY ACCELEROMETER Private TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Private_Defines STM32F411E DISCOVERY ACCELEROMETER Private Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Private_Macros STM32F411E DISCOVERY ACCELEROMETER Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Private_Variables STM32F411E DISCOVERY ACCELEROMETER Private Variables
|
||||
* @{
|
||||
*/
|
||||
static ACCELERO_DrvTypeDef *AccelerometerDrv;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Private_FunctionPrototypes STM32F411E DISCOVERY ACCELEROMETER Private FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Private_Functions STM32F411E DISCOVERY ACCELEROMETER Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set accelerometer Initialization.
|
||||
* @retval ACCELERO_OK if no problem during initialization
|
||||
*/
|
||||
uint8_t BSP_ACCELERO_Init(void)
|
||||
{
|
||||
uint8_t ret = ACCELERO_ERROR;
|
||||
uint16_t ctrl = 0x0000;
|
||||
ACCELERO_InitTypeDef Accelero_InitStructure;
|
||||
ACCELERO_FilterConfigTypeDef Accelero_FilterStructure = {0,0,0,0};
|
||||
|
||||
if(Lsm303dlhcDrv.ReadID() == I_AM_LMS303DLHC)
|
||||
{
|
||||
/* Initialize the accelerometer driver structure */
|
||||
AccelerometerDrv = &Lsm303dlhcDrv;
|
||||
|
||||
/* MEMS configuration ----------------------------------------------------*/
|
||||
/* Fill the accelerometer structure */
|
||||
Accelero_InitStructure.Power_Mode = LSM303DLHC_NORMAL_MODE;
|
||||
Accelero_InitStructure.AccOutput_DataRate = LSM303DLHC_ODR_50_HZ;
|
||||
Accelero_InitStructure.Axes_Enable = LSM303DLHC_AXES_ENABLE;
|
||||
Accelero_InitStructure.AccFull_Scale = LSM303DLHC_FULLSCALE_2G;
|
||||
Accelero_InitStructure.BlockData_Update = LSM303DLHC_BlockUpdate_Continous;
|
||||
Accelero_InitStructure.Endianness = LSM303DLHC_BLE_LSB;
|
||||
Accelero_InitStructure.High_Resolution = LSM303DLHC_HR_ENABLE;
|
||||
|
||||
/* Configure MEMS: data rate, power mode, full scale and axes */
|
||||
ctrl |= (Accelero_InitStructure.Power_Mode | Accelero_InitStructure.AccOutput_DataRate | \
|
||||
Accelero_InitStructure.Axes_Enable);
|
||||
|
||||
ctrl |= ((Accelero_InitStructure.BlockData_Update | Accelero_InitStructure.Endianness | \
|
||||
Accelero_InitStructure.AccFull_Scale | Accelero_InitStructure.High_Resolution) << 8);
|
||||
|
||||
/* Configure the accelerometer main parameters */
|
||||
AccelerometerDrv->Init(ctrl);
|
||||
|
||||
/* Fill the accelerometer LPF structure */
|
||||
Accelero_FilterStructure.HighPassFilter_Mode_Selection = LSM303DLHC_HPM_NORMAL_MODE;
|
||||
Accelero_FilterStructure.HighPassFilter_CutOff_Frequency = LSM303DLHC_HPFCF_16;
|
||||
Accelero_FilterStructure.HighPassFilter_AOI1 = LSM303DLHC_HPF_AOI1_DISABLE;
|
||||
Accelero_FilterStructure.HighPassFilter_AOI2 = LSM303DLHC_HPF_AOI2_DISABLE;
|
||||
|
||||
/* Configure MEMS: mode, cutoff frquency, Filter status, Click, AOI1 and AOI2 */
|
||||
ctrl = (uint8_t) (Accelero_FilterStructure.HighPassFilter_Mode_Selection |\
|
||||
Accelero_FilterStructure.HighPassFilter_CutOff_Frequency |\
|
||||
Accelero_FilterStructure.HighPassFilter_AOI1 |\
|
||||
Accelero_FilterStructure.HighPassFilter_AOI2);
|
||||
|
||||
/* Configure the accelerometer LPF main parameters */
|
||||
AccelerometerDrv->FilterConfig(ctrl);
|
||||
|
||||
ret = ACCELERO_OK;
|
||||
}
|
||||
else if(Lsm303agrDrv.ReadID() == I_AM_LSM303AGR)
|
||||
{
|
||||
/* Initialize the accelerometer driver structure */
|
||||
AccelerometerDrv = &Lsm303agrDrv;
|
||||
|
||||
/* MEMS configuration ----------------------------------------------------*/
|
||||
/* Fill the accelerometer structure */
|
||||
Accelero_InitStructure.Power_Mode = LSM303AGR_NORMAL_MODE;
|
||||
Accelero_InitStructure.AccOutput_DataRate = LSM303AGR_ODR_50_HZ;
|
||||
Accelero_InitStructure.Axes_Enable = LSM303AGR_AXES_ENABLE;
|
||||
Accelero_InitStructure.AccFull_Scale = LSM303AGR_FULLSCALE_2G;
|
||||
Accelero_InitStructure.BlockData_Update = LSM303AGR_BlockUpdate_Continous;
|
||||
Accelero_InitStructure.Endianness = LSM303AGR_BLE_LSB;
|
||||
Accelero_InitStructure.High_Resolution = LSM303AGR_HR_ENABLE;
|
||||
|
||||
/* Configure MEMS: data rate, power mode, full scale and axes */
|
||||
ctrl |= (Accelero_InitStructure.Power_Mode | Accelero_InitStructure.AccOutput_DataRate | \
|
||||
Accelero_InitStructure.Axes_Enable);
|
||||
|
||||
ctrl |= ((Accelero_InitStructure.BlockData_Update | Accelero_InitStructure.Endianness | \
|
||||
Accelero_InitStructure.AccFull_Scale | Accelero_InitStructure.High_Resolution) << 8);
|
||||
|
||||
/* Configure the accelerometer main parameters */
|
||||
AccelerometerDrv->Init(ctrl);
|
||||
|
||||
/* Fill the accelerometer LPF structure */
|
||||
Accelero_FilterStructure.HighPassFilter_Mode_Selection = LSM303AGR_HPM_NORMAL_MODE;
|
||||
Accelero_FilterStructure.HighPassFilter_CutOff_Frequency = LSM303AGR_HPFCF_16;
|
||||
Accelero_FilterStructure.HighPassFilter_AOI1 = LSM303AGR_HPF_AOI1_DISABLE;
|
||||
Accelero_FilterStructure.HighPassFilter_AOI2 = LSM303AGR_HPF_AOI2_DISABLE;
|
||||
|
||||
/* Configure MEMS: mode, cutoff frquency, Filter status, Click, AOI1 and AOI2 */
|
||||
ctrl = (uint8_t) (Accelero_FilterStructure.HighPassFilter_Mode_Selection |\
|
||||
Accelero_FilterStructure.HighPassFilter_CutOff_Frequency |\
|
||||
Accelero_FilterStructure.HighPassFilter_AOI1 |\
|
||||
Accelero_FilterStructure.HighPassFilter_AOI2);
|
||||
|
||||
/* Configure the accelerometer LPF main parameters */
|
||||
AccelerometerDrv->FilterConfig(ctrl);
|
||||
|
||||
ret = ACCELERO_OK;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reboot memory content of Accelerometer.
|
||||
*/
|
||||
void BSP_ACCELERO_Reset(void)
|
||||
{
|
||||
if(AccelerometerDrv->Reset != NULL)
|
||||
{
|
||||
AccelerometerDrv->Reset();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure accelerometer click IT.
|
||||
*/
|
||||
void BSP_ACCELERO_Click_ITConfig(void)
|
||||
{
|
||||
if(AccelerometerDrv->ConfigIT!= NULL)
|
||||
{
|
||||
AccelerometerDrv->ConfigIT();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get XYZ axes acceleration.
|
||||
* @param pDataXYZ: Pointer to 3 angular acceleration axes.
|
||||
* pDataXYZ[0] = X axis, pDataXYZ[1] = Y axis, pDataXYZ[2] = Z axis
|
||||
*/
|
||||
void BSP_ACCELERO_GetXYZ(int16_t *pDataXYZ)
|
||||
{
|
||||
int16_t SwitchXY = 0;
|
||||
|
||||
if(AccelerometerDrv->GetXYZ!= NULL)
|
||||
{
|
||||
AccelerometerDrv->GetXYZ(pDataXYZ);
|
||||
|
||||
/* Switch X and Y Axes in case of LSM303DLHC MEMS */
|
||||
if(AccelerometerDrv == &Lsm303dlhcDrv)
|
||||
{
|
||||
SwitchXY = pDataXYZ[0];
|
||||
pDataXYZ[0] = pDataXYZ[1];
|
||||
|
||||
/* Invert Y Axis to be conpliant with LIS3DSH */
|
||||
pDataXYZ[1] = -SwitchXY;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,117 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f411e_discovery_accelerometer.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the
|
||||
* stm32f411e_discovery_accelerometer.c firmware driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F411E_DISCOVERY_ACCELEROMETER_H
|
||||
#define __STM32F411E_DISCOVERY_ACCELEROMETER_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f411e_discovery.h"
|
||||
|
||||
/* Include Accelerometer component driver */
|
||||
#include "../Components/lsm303dlhc/lsm303dlhc.h"
|
||||
#include "../Components/lsm303agr/lsm303agr.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY_ACCELEROMETER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Exported_Types STM32F411E DISCOVERY ACCELEROMETER Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ACCELERO_OK = 0,
|
||||
ACCELERO_ERROR = 1,
|
||||
ACCELERO_TIMEOUT = 2
|
||||
}ACCELERO_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Exported_Constants STM32F411E DISCOVERY ACCELEROMETER Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_ACCELEROMETER_Exported_Functions STM32F411E DISCOVERY ACCELEROMETER Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/* Accelerometer functions */
|
||||
uint8_t BSP_ACCELERO_Init(void);
|
||||
void BSP_ACCELERO_Reset(void);
|
||||
void BSP_ACCELERO_Click_ITConfig(void);
|
||||
void BSP_ACCELERO_GetXYZ(int16_t *pDataXYZ);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F411E_DISCOVERY_ACCELEROMETER_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,272 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f411e_discovery_audio.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains the common defines and functions prototypes for
|
||||
* stm32f411e_discovery_audio.c driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F411E_DISCOVERY_AUDIO_H
|
||||
#define __STM32F411E_DISCOVERY_AUDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Include audio component Driver */
|
||||
#include "../Components/cs43l22/cs43l22.h"
|
||||
#include "stm32f411e_discovery.h"
|
||||
#include "../../../Middlewares/ST/STM32_Audio/Addons/PDM/Inc/pdm2pcm_glo.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY_AUDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_AUDIO_Exported_Types STM32F411E DISCOVERY AUDIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_AUDIO_OUT_Exported_Constants STM32F411E DISCOVERY AUDIO OUT Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
AUDIO OUT CONFIGURATION
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
/* I2S peripheral configuration defines */
|
||||
#define I2S3 SPI3
|
||||
#define I2S3_CLK_ENABLE() __HAL_RCC_SPI3_CLK_ENABLE()
|
||||
#define I2S3_CLK_DISABLE() __HAL_RCC_SPI3_CLK_DISABLE()
|
||||
#define I2S3_SCK_SD_WS_AF GPIO_AF6_SPI3
|
||||
#define I2S3_SCK_SD_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
|
||||
#define I2S3_MCK_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
|
||||
#define I2S3_WS_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
|
||||
#define I2S3_WS_PIN GPIO_PIN_4
|
||||
#define I2S3_SCK_PIN GPIO_PIN_10
|
||||
#define I2S3_SD_PIN GPIO_PIN_12
|
||||
#define I2S3_MCK_PIN GPIO_PIN_7
|
||||
#define I2S3_SCK_SD_GPIO_PORT GPIOC
|
||||
#define I2S3_WS_GPIO_PORT GPIOA
|
||||
#define I2S3_MCK_GPIO_PORT GPIOC
|
||||
|
||||
/* I2S DMA Stream definitions */
|
||||
#define I2S3_DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
|
||||
#define I2S3_DMAx_CLK_DISABLE() __HAL_RCC_DMA1_CLK_DISABLE()
|
||||
#define I2S3_DMAx_STREAM DMA1_Stream7
|
||||
#define I2S3_DMAx_CHANNEL DMA_CHANNEL_0
|
||||
#define I2S3_DMAx_IRQ DMA1_Stream7_IRQn
|
||||
#define I2S3_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD
|
||||
#define I2S3_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD
|
||||
#define DMA_MAX_SZE 0xFFFF
|
||||
|
||||
#define I2S3_IRQHandler DMA1_Stream7_IRQHandler
|
||||
|
||||
/* Select the interrupt preemption priority and subpriority for the DMA interrupt */
|
||||
#define AUDIO_OUT_IRQ_PREPRIO 0x0E /* Select the preemption priority level(0 is the highest) */
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
AUDIO IN CONFIGURATION
|
||||
------------------------------------------------------------------------------*/
|
||||
/* SPI Configuration defines */
|
||||
#define I2S2 SPI2
|
||||
#define I2S2_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
|
||||
#define I2S2_CLK_DISABLE() __HAL_RCC_SPI2_CLK_DISABLE()
|
||||
#define I2S2_SCK_PIN GPIO_PIN_10
|
||||
#define I2S2_SCK_GPIO_PORT GPIOB
|
||||
#define I2S2_SCK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
|
||||
#define I2S2_SCK_AF GPIO_AF5_SPI2
|
||||
|
||||
#define I2S2_MOSI_PIN GPIO_PIN_3
|
||||
#define I2S2_MOSI_GPIO_PORT GPIOC
|
||||
#define I2S2_MOSI_GPIO_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
|
||||
#define I2S2_MOSI_AF GPIO_AF5_SPI2
|
||||
|
||||
/* I2S DMA Stream Rx definitions */
|
||||
#define I2S2_DMAx_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
|
||||
#define I2S2_DMAx_CLK_DISABLE() __HAL_RCC_DMA1_CLK_DISABLE()
|
||||
#define I2S2_DMAx_STREAM DMA1_Stream3
|
||||
#define I2S2_DMAx_CHANNEL DMA_CHANNEL_0
|
||||
#define I2S2_DMAx_IRQ DMA1_Stream3_IRQn
|
||||
#define I2S2_DMAx_PERIPH_DATA_SIZE DMA_PDATAALIGN_HALFWORD
|
||||
#define I2S2_DMAx_MEM_DATA_SIZE DMA_MDATAALIGN_HALFWORD
|
||||
|
||||
#define I2S2_IRQHandler DMA1_Stream3_IRQHandler
|
||||
|
||||
/* Select the interrupt preemption priority and subpriority for the IT/DMA interrupt */
|
||||
#define AUDIO_IN_IRQ_PREPRIO 0x0F /* Select the preemption priority level(0 is the highest) */
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
CONFIGURATION: Audio Driver Configuration parameters
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
#define AUDIODATA_SIZE 2 /* 16-bits audio data size */
|
||||
|
||||
/* Audio status definition */
|
||||
#define AUDIO_OK 0
|
||||
#define AUDIO_ERROR 1
|
||||
#define AUDIO_TIMEOUT 2
|
||||
|
||||
/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */
|
||||
#define DEFAULT_AUDIO_IN_FREQ I2S_AUDIOFREQ_16K
|
||||
#define DEFAULT_AUDIO_IN_BIT_RESOLUTION 16
|
||||
#define DEFAULT_AUDIO_IN_CHANNEL_NBR 1 /* Mono = 1, Stereo = 2 */
|
||||
#define DEFAULT_AUDIO_IN_VOLUME 64
|
||||
|
||||
/* PDM buffer input size */
|
||||
#define INTERNAL_BUFF_SIZE 128*DEFAULT_AUDIO_IN_FREQ/16000*DEFAULT_AUDIO_IN_CHANNEL_NBR
|
||||
/* PCM buffer output size */
|
||||
#define PCM_OUT_SIZE DEFAULT_AUDIO_IN_FREQ/1000
|
||||
#define CHANNEL_DEMUX_MASK 0x55
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
OPTIONAL Configuration defines parameters
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_AUDIO_Exported_Variables STM32F411E DISCOVERY AUDIO Exported Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint16_t AudioInVolume;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_AUDIO_Exported_Macros STM32F411E DISCOVERY AUDIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MAX(_X_) (((_X_) <= DMA_MAX_SZE)? (_X_):DMA_MAX_SZE)
|
||||
#define HTONS(A) ((((uint16_t)(A) & 0xff00) >> 8) | (((uint16_t)(A) & 0x00ff) << 8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_AUDIO_OUT_Exported_Functions STM32F411E DISCOVERY AUDIO OUT Exported Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_AUDIO_OUT_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq);
|
||||
uint8_t BSP_AUDIO_OUT_Play(uint16_t *pBuffer, uint32_t Size);
|
||||
void BSP_AUDIO_OUT_ChangeBuffer(uint16_t *pData, uint16_t Size);
|
||||
uint8_t BSP_AUDIO_OUT_Pause(void);
|
||||
uint8_t BSP_AUDIO_OUT_Resume(void);
|
||||
uint8_t BSP_AUDIO_OUT_Stop(uint32_t Option);
|
||||
uint8_t BSP_AUDIO_OUT_SetVolume(uint8_t Volume);
|
||||
void BSP_AUDIO_OUT_SetFrequency(uint32_t AudioFreq);
|
||||
uint8_t BSP_AUDIO_OUT_SetMute(uint32_t Cmd);
|
||||
uint8_t BSP_AUDIO_OUT_SetOutputMode(uint8_t Output);
|
||||
|
||||
/* User Callbacks: user has to implement these functions in his code if they are needed. */
|
||||
/* This function is called when the requested data has been completely transferred. */
|
||||
void BSP_AUDIO_OUT_TransferComplete_CallBack(void);
|
||||
|
||||
/* This function is called when half of the requested buffer has been transferred. */
|
||||
void BSP_AUDIO_OUT_HalfTransfer_CallBack(void);
|
||||
|
||||
/* This function is called when an Interrupt due to transfer error on or peripheral
|
||||
error occurs. */
|
||||
void BSP_AUDIO_OUT_Error_CallBack(void);
|
||||
|
||||
/* These function can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_AUDIO_OUT_ClockConfig(I2S_HandleTypeDef *hi2s, uint32_t AudioFreq, void *Params);
|
||||
void BSP_AUDIO_OUT_MspInit(I2S_HandleTypeDef *hi2s, void *Params);
|
||||
void BSP_AUDIO_OUT_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_AUDIO_IN_Exported_Functions STM32F411E DISCOVERY AUDIO IN Exported Functions
|
||||
* @{
|
||||
*/
|
||||
uint8_t BSP_AUDIO_IN_Init(uint32_t AudioFreq, uint32_t BitRes, uint32_t ChnlNbr);
|
||||
uint8_t BSP_AUDIO_IN_Record(uint16_t *pData, uint32_t Size);
|
||||
uint8_t BSP_AUDIO_IN_Stop(void);
|
||||
uint8_t BSP_AUDIO_IN_Pause(void);
|
||||
uint8_t BSP_AUDIO_IN_Resume(void);
|
||||
uint8_t BSP_AUDIO_IN_SetVolume(uint8_t Volume);
|
||||
uint8_t BSP_AUDIO_IN_PDMToPCM(uint16_t *PDMBuf, uint16_t *PCMBuf);
|
||||
/* User Callbacks: user has to implement these functions in his code if they are needed. */
|
||||
/* This function should be implemented by the user application.
|
||||
It is called into this driver when the current buffer is filled to prepare the next
|
||||
buffer pointer and its size. */
|
||||
void BSP_AUDIO_IN_TransferComplete_CallBack(void);
|
||||
void BSP_AUDIO_IN_HalfTransfer_CallBack(void);
|
||||
|
||||
/* This function is called when an Interrupt due to transfer error on or peripheral
|
||||
error occurs. */
|
||||
void BSP_AUDIO_IN_Error_Callback(void);
|
||||
|
||||
/* These function can be modified in case the current settings (e.g. DMA stream)
|
||||
need to be changed for specific application needs */
|
||||
void BSP_AUDIO_IN_ClockConfig(I2S_HandleTypeDef *hi2s, uint32_t AudioFreq, void *Params);
|
||||
void BSP_AUDIO_IN_MspInit(I2S_HandleTypeDef *hi2s, void *Params);
|
||||
void BSP_AUDIO_IN_MspDeInit(I2S_HandleTypeDef *hi2s, void *Params);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F411E_DISCOVERY_AUDIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,291 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f411e_discovery_gyroscope.c
|
||||
* @author MCD Application Team
|
||||
* @brief This file provides a set of functions needed to manage the
|
||||
* MEMS gyroscope available on STM32F411E-Discovery Kit.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f411e_discovery_gyroscope.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE STM32F411E DISCOVERY GYROSCOPE
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Private_TypesDefinitions STM32F411E DISCOVERY GYROSCOPE Private TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Private_Defines STM32F411E DISCOVERY GYROSCOPE Private Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Private_Macros STM32F411E DISCOVERY GYROSCOPE Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Private_Variables STM32F411E DISCOVERY GYROSCOPE Private Variables
|
||||
* @{
|
||||
*/
|
||||
static GYRO_DrvTypeDef *GyroscopeDrv;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Private_FunctionPrototypes STM32F411E DISCOVERY GYROSCOPE Private FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Private_Functions STM32F411E DISCOVERY GYROSCOPE Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set gyroscope Initialization.
|
||||
* @retval GYRO_OK if no problem during initialization
|
||||
*/
|
||||
uint8_t BSP_GYRO_Init(void)
|
||||
{
|
||||
uint8_t ret = GYRO_ERROR;
|
||||
uint16_t ctrl = 0x0000;
|
||||
GYRO_InitTypeDef Gyro_InitStructure;
|
||||
GYRO_FilterConfigTypeDef Gyro_FilterStructure = {0,0};
|
||||
|
||||
if((L3gd20Drv.ReadID() == I_AM_L3GD20) || (L3gd20Drv.ReadID() == I_AM_L3GD20_TR))
|
||||
{
|
||||
/* Initialize the gyroscope driver structure */
|
||||
GyroscopeDrv = &L3gd20Drv;
|
||||
|
||||
/* MEMS configuration ----------------------------------------------------*/
|
||||
/* Fill the gyroscope structure */
|
||||
Gyro_InitStructure.Power_Mode = L3GD20_MODE_ACTIVE;
|
||||
Gyro_InitStructure.Output_DataRate = L3GD20_OUTPUT_DATARATE_1;
|
||||
Gyro_InitStructure.Axes_Enable = L3GD20_AXES_ENABLE;
|
||||
Gyro_InitStructure.Band_Width = L3GD20_BANDWIDTH_4;
|
||||
Gyro_InitStructure.BlockData_Update = L3GD20_BlockDataUpdate_Continous;
|
||||
Gyro_InitStructure.Endianness = L3GD20_BLE_LSB;
|
||||
Gyro_InitStructure.Full_Scale = L3GD20_FULLSCALE_500;
|
||||
|
||||
/* Configure MEMS: data rate, power mode, full scale and axes */
|
||||
ctrl = (uint16_t) (Gyro_InitStructure.Power_Mode | Gyro_InitStructure.Output_DataRate | \
|
||||
Gyro_InitStructure.Axes_Enable | Gyro_InitStructure.Band_Width);
|
||||
|
||||
ctrl |= (uint16_t) ((Gyro_InitStructure.BlockData_Update | Gyro_InitStructure.Endianness | \
|
||||
Gyro_InitStructure.Full_Scale) << 8);
|
||||
|
||||
/* Initialize the gyroscope */
|
||||
GyroscopeDrv->Init(ctrl);
|
||||
|
||||
Gyro_FilterStructure.HighPassFilter_Mode_Selection = L3GD20_HPM_NORMAL_MODE_RES;
|
||||
Gyro_FilterStructure.HighPassFilter_CutOff_Frequency = L3GD20_HPFCF_0;
|
||||
|
||||
ctrl = (uint8_t) ((Gyro_FilterStructure.HighPassFilter_Mode_Selection |\
|
||||
Gyro_FilterStructure.HighPassFilter_CutOff_Frequency));
|
||||
|
||||
/* Configure the gyroscope main parameters */
|
||||
GyroscopeDrv->FilterConfig(ctrl);
|
||||
|
||||
GyroscopeDrv->FilterCmd(L3GD20_HIGHPASSFILTER_ENABLE);
|
||||
|
||||
ret = GYRO_OK;
|
||||
}
|
||||
else if (I3g4250Drv.ReadID() == I_AM_I3G4250D)
|
||||
{
|
||||
/* Initialize the gyroscope driver structure */
|
||||
GyroscopeDrv = &I3g4250Drv;
|
||||
|
||||
/* Configure Mems : data rate, power mode, full scale and axes */
|
||||
Gyro_InitStructure.Power_Mode = I3G4250D_MODE_ACTIVE;
|
||||
Gyro_InitStructure.Output_DataRate = I3G4250D_OUTPUT_DATARATE_1;
|
||||
Gyro_InitStructure.Axes_Enable = I3G4250D_AXES_ENABLE;
|
||||
Gyro_InitStructure.Band_Width = I3G4250D_BANDWIDTH_4;
|
||||
Gyro_InitStructure.BlockData_Update = I3G4250D_BlockDataUpdate_Continous;
|
||||
Gyro_InitStructure.Endianness = I3G4250D_BLE_LSB;
|
||||
Gyro_InitStructure.Full_Scale = I3G4250D_FULLSCALE_500;
|
||||
|
||||
/* Configure MEMS: data rate, power mode, full scale and axes */
|
||||
ctrl = (uint16_t) (Gyro_InitStructure.Power_Mode | Gyro_InitStructure.Output_DataRate | \
|
||||
Gyro_InitStructure.Axes_Enable | Gyro_InitStructure.Band_Width);
|
||||
|
||||
ctrl |= (uint16_t) ((Gyro_InitStructure.BlockData_Update | Gyro_InitStructure.Endianness | \
|
||||
Gyro_InitStructure.Full_Scale) << 8);
|
||||
|
||||
/* Initialize the gyroscope */
|
||||
GyroscopeDrv->Init(ctrl);
|
||||
|
||||
Gyro_FilterStructure.HighPassFilter_Mode_Selection = I3G4250D_HPM_NORMAL_MODE_RES;
|
||||
Gyro_FilterStructure.HighPassFilter_CutOff_Frequency = I3G4250D_HPFCF_0;
|
||||
|
||||
ctrl = (uint8_t) ((Gyro_FilterStructure.HighPassFilter_Mode_Selection |\
|
||||
Gyro_FilterStructure.HighPassFilter_CutOff_Frequency));
|
||||
|
||||
/* Configure the gyroscope main parameters */
|
||||
GyroscopeDrv->FilterConfig(ctrl);
|
||||
|
||||
GyroscopeDrv->FilterCmd(I3G4250D_HIGHPASSFILTER_ENABLE);
|
||||
|
||||
ret = GYRO_OK;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read ID of gyroscope component.
|
||||
* @retval ID
|
||||
*/
|
||||
uint8_t BSP_GYRO_ReadID(void)
|
||||
{
|
||||
uint8_t id = 0x00;
|
||||
|
||||
if(GyroscopeDrv->ReadID != NULL)
|
||||
{
|
||||
id = GyroscopeDrv->ReadID();
|
||||
}
|
||||
return id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reboot memory content of Gyroscope.
|
||||
*/
|
||||
void BSP_GYRO_Reset(void)
|
||||
{
|
||||
if(GyroscopeDrv->Reset != NULL)
|
||||
{
|
||||
GyroscopeDrv->Reset();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures INT1 interrupt.
|
||||
* @param pIntConfig: pointer to a L3GD20_InterruptConfig_TypeDef
|
||||
* structure that contains the configuration setting for the L3GD20 Interrupt.
|
||||
*/
|
||||
void BSP_GYRO_ITConfig(GYRO_InterruptConfigTypeDef *pIntConfig)
|
||||
{
|
||||
uint16_t interruptconfig = 0x0000;
|
||||
|
||||
if(GyroscopeDrv->ConfigIT != NULL)
|
||||
{
|
||||
/* Configure latch Interrupt request and axe interrupts */
|
||||
interruptconfig |= ((uint8_t)(pIntConfig->Latch_Request| \
|
||||
pIntConfig->Interrupt_Axes) << 8);
|
||||
|
||||
interruptconfig |= (uint8_t)(pIntConfig->Interrupt_ActiveEdge);
|
||||
|
||||
GyroscopeDrv->ConfigIT(interruptconfig);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables INT1 or INT2 interrupt.
|
||||
* @param IntPin: Interrupt pin
|
||||
* This parameter can be:
|
||||
* @arg L3GD20_INT1
|
||||
* @arg L3GD20_INT2
|
||||
* @arg I3G4250D_INT1
|
||||
* @arg I3G4250D_INT2
|
||||
*/
|
||||
void BSP_GYRO_EnableIT(uint8_t IntPin)
|
||||
{
|
||||
if(GyroscopeDrv->EnableIT != NULL)
|
||||
{
|
||||
GyroscopeDrv->EnableIT(IntPin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables INT1 or INT2 interrupt.
|
||||
* @param IntPin: Interrupt pin
|
||||
* This parameter can be:
|
||||
* @arg L3GD20_INT1
|
||||
* @arg L3GD20_INT2
|
||||
* @arg I3G4250D_INT1
|
||||
* @arg I3G4250D_INT2
|
||||
*/
|
||||
void BSP_GYRO_DisableIT(uint8_t IntPin)
|
||||
{
|
||||
if(GyroscopeDrv->DisableIT != NULL)
|
||||
{
|
||||
GyroscopeDrv->DisableIT(IntPin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get XYZ angular acceleration.
|
||||
* @param pfData: pointer on floating array
|
||||
*/
|
||||
void BSP_GYRO_GetXYZ(float *pfData)
|
||||
{
|
||||
if(GyroscopeDrv->GetXYZ!= NULL)
|
||||
{
|
||||
GyroscopeDrv->GetXYZ(pfData);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,126 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f411e_discovery_gyroscope.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains definitions for stm32f411e_discovery_gyroscope.c
|
||||
* firmware driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F411E_DISCOVERY_GYROSCOPE_H
|
||||
#define __STM32F411E_DISCOVERY_GYROSCOPE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f411e_discovery.h"
|
||||
|
||||
/* Include Gyroscope component driver */
|
||||
#include "../Components/l3gd20/l3gd20.h"
|
||||
#include "../Components/i3g4250d/i3g4250d.h"
|
||||
|
||||
/** @addtogroup BSP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F411E_DISCOVERY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE STM32F411E DISCOVERY GYROSCOPE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Exported_Types STM32F411E DISCOVERY GYROSCOPE Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GYRO_OK = 0,
|
||||
GYRO_ERROR = 1,
|
||||
GYRO_TIMEOUT = 2
|
||||
}GYRO_StatusTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Exported_Constants STM32F411E DISCOVERY GYROSCOPE Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Exported_Macros STM32F411E DISCOVERY GYROSCOPE Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup STM32F411E_DISCOVERY_GYROSCOPE_Exported_Functions STM32F411E DISCOVERY GYROSCOPE Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/* Gyroscope Functions */
|
||||
uint8_t BSP_GYRO_Init(void);
|
||||
void BSP_GYRO_Reset(void);
|
||||
uint8_t BSP_GYRO_ReadID(void);
|
||||
void BSP_GYRO_ITConfig(GYRO_InterruptConfigTypeDef *pIntConfigStruct);
|
||||
void BSP_GYRO_EnableIT(uint8_t IntPin);
|
||||
void BSP_GYRO_DisableIT(uint8_t IntPin);
|
||||
void BSP_GYRO_GetXYZ(float *pfData);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F411E_DISCOVERY_GYROSCOPE_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,253 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F4xx device used in the target application
|
||||
* - To use or not the peripheral<61>s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral<61>s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F4xx_H
|
||||
#define __STM32F4xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32F4)
|
||||
#define STM32F4
|
||||
#endif /* STM32F4 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
|
||||
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
|
||||
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
|
||||
!defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
|
||||
!defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
|
||||
!defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
|
||||
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
|
||||
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
|
||||
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
|
||||
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
|
||||
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
|
||||
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
|
||||
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
|
||||
STM32F439NI, STM32F429IG and STM32F429II Devices */
|
||||
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
|
||||
STM32F439NI, STM32F439IG and STM32F439II Devices */
|
||||
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
|
||||
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
|
||||
/* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
|
||||
/* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
|
||||
/* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
|
||||
/* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
|
||||
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
|
||||
and STM32F446ZE Devices */
|
||||
/* #define STM32F469xx */ /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG,
|
||||
STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
|
||||
/* #define STM32F479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG
|
||||
and STM32F479NG Devices */
|
||||
/* #define STM32F412Cx */ /*!< STM32F412CEU and STM32F412CGU Devices */
|
||||
/* #define STM32F412Zx */ /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
|
||||
/* #define STM32F412Vx */ /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
|
||||
/* #define STM32F412Rx */ /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
|
||||
/* #define STM32F413xx */ /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
|
||||
STM32F413RG, STM32F413VG and STM32F413ZG Devices */
|
||||
/* #define STM32F423xx */ /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS version number V2.6.6
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F4xx_CMSIS_VERSION))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F405xx)
|
||||
#include "stm32f405xx.h"
|
||||
#elif defined(STM32F415xx)
|
||||
#include "stm32f415xx.h"
|
||||
#elif defined(STM32F407xx)
|
||||
#include "stm32f407xx.h"
|
||||
#elif defined(STM32F417xx)
|
||||
#include "stm32f417xx.h"
|
||||
#elif defined(STM32F427xx)
|
||||
#include "stm32f427xx.h"
|
||||
#elif defined(STM32F437xx)
|
||||
#include "stm32f437xx.h"
|
||||
#elif defined(STM32F429xx)
|
||||
#include "stm32f429xx.h"
|
||||
#elif defined(STM32F439xx)
|
||||
#include "stm32f439xx.h"
|
||||
#elif defined(STM32F401xC)
|
||||
#include "stm32f401xc.h"
|
||||
#elif defined(STM32F401xE)
|
||||
#include "stm32f401xe.h"
|
||||
#elif defined(STM32F410Tx)
|
||||
#include "stm32f410tx.h"
|
||||
#elif defined(STM32F410Cx)
|
||||
#include "stm32f410cx.h"
|
||||
#elif defined(STM32F410Rx)
|
||||
#include "stm32f410rx.h"
|
||||
#elif defined(STM32F411xE)
|
||||
#include "stm32f411xe.h"
|
||||
#elif defined(STM32F446xx)
|
||||
#include "stm32f446xx.h"
|
||||
#elif defined(STM32F469xx)
|
||||
#include "stm32f469xx.h"
|
||||
#elif defined(STM32F479xx)
|
||||
#include "stm32f479xx.h"
|
||||
#elif defined(STM32F412Cx)
|
||||
#include "stm32f412cx.h"
|
||||
#elif defined(STM32F412Zx)
|
||||
#include "stm32f412zx.h"
|
||||
#elif defined(STM32F412Rx)
|
||||
#include "stm32f412rx.h"
|
||||
#elif defined(STM32F412Vx)
|
||||
#include "stm32f412vx.h"
|
||||
#elif defined(STM32F413xx)
|
||||
#include "stm32f413xx.h"
|
||||
#elif defined(STM32F423xx)
|
||||
#include "stm32f423xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0U,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0U,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SUCCESS = 0U,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32f4xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F4xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,122 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F4XX_H
|
||||
#define __SYSTEM_STM32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F4XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,865 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,266 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,935 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.0.7
|
||||
* @date 19. June 2018
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,949 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.5
|
||||
* @date 28. May 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,976 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.0.0
|
||||
* @date 23. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
#define __CORE_CM1_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M1
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT
|
||||
#define __CORE_CM1_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM1_REV
|
||||
#define __CM1_REV 0x0100U
|
||||
#warning "__CM1_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M1 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M1 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
1941
STM32Cube/Audio_playback_and_record/Drivers/CMSIS/Include/core_cm3.h
Normal file
1941
STM32Cube/Audio_playback_and_record/Drivers/CMSIS/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
2129
STM32Cube/Audio_playback_and_record/Drivers/CMSIS/Include/core_cm4.h
Normal file
2129
STM32Cube/Audio_playback_and_record/Drivers/CMSIS/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2671
STM32Cube/Audio_playback_and_record/Drivers/CMSIS/Include/core_cm7.h
Normal file
2671
STM32Cube/Audio_playback_and_record/Drivers/CMSIS/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,270 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,333 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
@@ -0,0 +1,57 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32_ASSERT_H
|
||||
#define __STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32_ASSERT_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,298 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_H
|
||||
#define __STM32F4xx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_conf.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TICK_FREQ_10HZ = 100U,
|
||||
HAL_TICK_FREQ_100HZ = 10U,
|
||||
HAL_TICK_FREQ_1KHZ = 1U,
|
||||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||
} HAL_TickFreqTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze/Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
|
||||
#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
|
||||
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
|
||||
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
|
||||
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
|
||||
}while(0);
|
||||
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
|
||||
}while(0);
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
|
||||
/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
|
||||
}while(0);
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
|
||||
defined(STM32F469xx) || defined(STM32F479xx)
|
||||
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
|
||||
}while(0);
|
||||
|
||||
/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
|
||||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
|
||||
}while(0);
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
|
||||
|
||||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
|
||||
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break Lockup lock
|
||||
* Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PVD_Lock_Enable PVD Lock
|
||||
* @{
|
||||
*/
|
||||
/** @brief SYSCFG Break PVD lock
|
||||
* Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
|
||||
* @note The selected configuration is locked and can be unlocked by system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
|
||||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
|
||||
}while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and Configuration functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
void HAL_EnableCompensationCell(void);
|
||||
void HAL_DisableCompensationCell(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
|
||||
defined(STM32F469xx) || defined(STM32F479xx)
|
||||
void HAL_EnableMemorySwappingBank(void);
|
||||
void HAL_DisableMemorySwappingBank(void);
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Variables HAL Private Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,900 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file containing functions prototypes of ADC HAL library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_ADC_H
|
||||
#define __STM32F4xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/* Include low level driver */
|
||||
#include "stm32f4xx_ll_adc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Types ADC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC and regular group initialization
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
|
||||
* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
|
||||
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
|
||||
* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
|
||||
all the ADCs.
|
||||
This parameter can be a value of @ref ADC_ClockPrescaler */
|
||||
uint32_t Resolution; /*!< Configures the ADC resolution.
|
||||
This parameter can be a value of @ref ADC_Resolution */
|
||||
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
|
||||
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
|
||||
This parameter can be a value of @ref ADC_Data_align */
|
||||
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
|
||||
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
|
||||
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
|
||||
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
|
||||
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
|
||||
Scan direction is upward: from rank1 to rank 'n'.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
|
||||
This parameter can be a value of @ref ADC_EOCSelection.
|
||||
Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
|
||||
Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
|
||||
or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
|
||||
Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
|
||||
If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
|
||||
FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
|
||||
after the selected trigger occurred (software start or external trigger).
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
|
||||
To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
|
||||
FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
|
||||
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
|
||||
uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
|
||||
If set to ADC_SOFTWARE_START, external triggers are disabled.
|
||||
If set to external trigger source, triggering is on event rising edge by default.
|
||||
This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
|
||||
uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
|
||||
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
|
||||
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
|
||||
FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
|
||||
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
|
||||
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC channel for regular group
|
||||
* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
|
||||
* ADC can be either disabled or enabled without conversion on going on regular group.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
|
||||
This parameter can be a value of @ref ADC_channels */
|
||||
uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
|
||||
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_sampling_times
|
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
|
||||
uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
|
||||
}ADC_ChannelConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration multi-mode structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
|
||||
This parameter can be a value of @ref ADC_analog_watchdog_selection */
|
||||
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
||||
This parameter must be a 12-bit value. */
|
||||
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
|
||||
This parameter must be a 12-bit value. */
|
||||
uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
|
||||
This parameter has an effect only if watchdog mode is configured on single channel
|
||||
This parameter can be a value of @ref ADC_channels */
|
||||
FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured
|
||||
is interrupt mode or in polling mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
|
||||
}ADC_AnalogWDGConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL ADC state machine: ADC states definition (bitfields)
|
||||
*/
|
||||
/* States of ADC global scope */
|
||||
#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
|
||||
#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
|
||||
#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
|
||||
|
||||
/* States of ADC errors */
|
||||
#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
|
||||
|
||||
/* States of ADC group regular */
|
||||
#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
|
||||
#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
|
||||
|
||||
/* States of ADC group injected */
|
||||
#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
|
||||
|
||||
/* States of ADC analog watchdogs */
|
||||
#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
|
||||
#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
|
||||
#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
|
||||
|
||||
/* States of ADC multi-mode */
|
||||
#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
|
||||
|
||||
|
||||
/**
|
||||
* @brief ADC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __ADC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
ADC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
ADC_InitTypeDef Init; /*!< ADC required parameters */
|
||||
|
||||
__IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< ADC locking object */
|
||||
|
||||
__IO uint32_t State; /*!< ADC communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< ADC Error code */
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
|
||||
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
|
||||
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
|
||||
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
|
||||
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
|
||||
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
}ADC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL ADC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
|
||||
HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
|
||||
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
|
||||
HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
|
||||
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
|
||||
HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */
|
||||
HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */
|
||||
} HAL_ADC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL ADC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
|
||||
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Error_Code ADC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
|
||||
enable/disable, erroneous state */
|
||||
#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
|
||||
#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
|
||||
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
|
||||
* @{
|
||||
*/
|
||||
#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
|
||||
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
|
||||
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
|
||||
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
|
||||
#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
|
||||
#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
|
||||
#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
|
||||
#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
|
||||
#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Resolution ADC Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RESOLUTION_12B 0x00000000U
|
||||
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
|
||||
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
|
||||
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
|
||||
* @{
|
||||
*/
|
||||
/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
|
||||
/* compatibility with other STM32 devices. */
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
|
||||
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
|
||||
#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
|
||||
#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
|
||||
#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
|
||||
#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Data_align ADC Data Align
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT 0x00000000U
|
||||
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels ADC Common Channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_0 0x00000000U
|
||||
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
|
||||
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
|
||||
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
|
||||
#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
|
||||
#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
|
||||
#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
|
||||
#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
|
||||
#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
|
||||
#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
|
||||
|
||||
#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
|
||||
#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_times ADC Sampling Times
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLETIME_3CYCLES 0x00000000U
|
||||
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
|
||||
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
|
||||
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
|
||||
#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
|
||||
#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
|
||||
#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
|
||||
#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_EOCSelection ADC EOC Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EOC_SEQ_CONV 0x00000000U
|
||||
#define ADC_EOC_SINGLE_CONV 0x00000001U
|
||||
#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Event_type ADC Event Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
|
||||
#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
|
||||
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
|
||||
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
|
||||
#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
|
||||
#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
|
||||
#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition ADC Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
|
||||
#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
|
||||
#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
|
||||
#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
|
||||
#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
|
||||
#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels_type ADC Channels Type
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ALL_CHANNELS 0x00000001U
|
||||
#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
|
||||
#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset ADC handle state
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
|
||||
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC peripheral.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
|
||||
|
||||
/**
|
||||
* @brief Disable the ADC peripheral.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC end of conversion interrupt.
|
||||
* @param __HANDLE__ specifies the ADC Handle.
|
||||
* @param __INTERRUPT__ ADC Interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the ADC end of conversion interrupt.
|
||||
* @param __HANDLE__ specifies the ADC Handle.
|
||||
* @param __INTERRUPT__ ADC interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check if the specified ADC interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the ADC Handle.
|
||||
* @param __INTERRUPT__ specifies the ADC interrupt source to check.
|
||||
* @retval The new state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the ADC's pending flags.
|
||||
* @param __HANDLE__ specifies the ADC Handle.
|
||||
* @param __FLAG__ ADC flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Get the selected ADC's flag status.
|
||||
* @param __HANDLE__ specifies the ADC Handle.
|
||||
* @param __FLAG__ ADC flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include ADC HAL Extension module */
|
||||
#include "stm32f4xx_hal_adc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
|
||||
|
||||
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
|
||||
|
||||
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
|
||||
|
||||
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
|
||||
|
||||
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
|
||||
|
||||
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
|
||||
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ***************************************************/
|
||||
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Constants ADC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Delay for ADC stabilization time. */
|
||||
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
|
||||
/* Unit: us */
|
||||
#define ADC_STAB_DELAY_US 3U
|
||||
/* Delay for temperature sensor stabilization time. */
|
||||
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
|
||||
/* Unit: us */
|
||||
#define ADC_TEMPSENSOR_DELAY_US 10U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in
|
||||
code of final user */
|
||||
|
||||
/**
|
||||
* @brief Verification of ADC state: enabled or disabled
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval SET (ADC enabled) or RESET (ADC disabled)
|
||||
*/
|
||||
#define ADC_IS_ENABLE(__HANDLE__) \
|
||||
((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
|
||||
) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of regular group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval SET (software start) or RESET (external trigger)
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of injected group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval SET (software start) or RESET (external trigger)
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
|
||||
|
||||
/**
|
||||
* @brief Simultaneously clears and sets specific bits of the handle State
|
||||
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
|
||||
* the first parameter is the ADC handle State, the second parameter is the
|
||||
* bit field to clear, the third and last parameter is the bit field to set.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_STATE_CLR_SET MODIFY_REG
|
||||
|
||||
/**
|
||||
* @brief Clear ADC error code (set it to error code: "no error")
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
|
||||
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
|
||||
|
||||
|
||||
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
|
||||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
|
||||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
|
||||
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
|
||||
#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
|
||||
((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
|
||||
((RESOLUTION) == ADC_RESOLUTION_10B) || \
|
||||
((RESOLUTION) == ADC_RESOLUTION_8B) || \
|
||||
((RESOLUTION) == ADC_RESOLUTION_6B))
|
||||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
|
||||
((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
|
||||
((REGTRIG) == ADC_SOFTWARE_START))
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
|
||||
((ALIGN) == ADC_DATAALIGN_LEFT))
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_15CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_28CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_56CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_84CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_112CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_144CYCLES) || \
|
||||
((TIME) == ADC_SAMPLETIME_480CYCLES))
|
||||
#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
|
||||
((EOCSelection) == ADC_EOC_SEQ_CONV) || \
|
||||
((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
|
||||
#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
|
||||
((EVENT) == ADC_OVR_EVENT))
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
|
||||
((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
|
||||
#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
|
||||
((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
|
||||
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
|
||||
((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
|
||||
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
|
||||
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
|
||||
(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
|
||||
|
||||
/**
|
||||
* @brief Set ADC Regular channel sequence length.
|
||||
* @param _NbrOfConversion_ Regular channel sequence length.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
|
||||
|
||||
/**
|
||||
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
|
||||
* @param _SAMPLETIME_ Sample time parameter.
|
||||
* @param _CHANNELNB_ Channel number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
|
||||
|
||||
/**
|
||||
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
|
||||
* @param _SAMPLETIME_ Sample time parameter.
|
||||
* @param _CHANNELNB_ Channel number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 1 and 6.
|
||||
* @param _CHANNELNB_ Channel number.
|
||||
* @param _RANKNB_ Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 7 and 12.
|
||||
* @param _CHANNELNB_ Channel number.
|
||||
* @param _RANKNB_ Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
|
||||
|
||||
/**
|
||||
* @brief Set the selected regular channel rank for rank between 13 and 16.
|
||||
* @param _CHANNELNB_ Channel number.
|
||||
* @param _RANKNB_ Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
|
||||
|
||||
/**
|
||||
* @brief Enable ADC continuous conversion mode.
|
||||
* @param _CONTINUOUS_MODE_ Continuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
|
||||
|
||||
/**
|
||||
* @brief Configures the number of discontinuous conversions for the regular group channels.
|
||||
* @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Enable ADC scan mode.
|
||||
* @param _SCANCONV_MODE_ Scan conversion mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC end of conversion selection.
|
||||
* @param _EOCSelection_MODE_ End of conversion selection mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
|
||||
|
||||
/**
|
||||
* @brief Enable the ADC DMA continuous request.
|
||||
* @param _DMAContReq_MODE_ DMA continuous request mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
|
||||
|
||||
/**
|
||||
* @brief Return resolution bits in CR1 register.
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup ADC_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_ADC_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,409 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ADC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_ADC_EX_H
|
||||
#define __STM32F4xx_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration injected Channel structure definition
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
|
||||
* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
|
||||
* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled
|
||||
* - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
|
||||
* - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
|
||||
This parameter can be a value of @ref ADC_channels
|
||||
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
|
||||
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
|
||||
This parameter must be a value of @ref ADCEx_injected_rank
|
||||
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles
|
||||
Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_sampling_times
|
||||
Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
|
||||
If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
|
||||
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
|
||||
If set to external trigger source, triggering is on event rising edge.
|
||||
This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
||||
This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
|
||||
If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
}ADC_InjectionConfTypeDef;
|
||||
|
||||
/**
|
||||
* @brief ADC Configuration multi-mode structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
|
||||
This parameter can be a value of @ref ADCEx_Common_mode */
|
||||
uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
|
||||
This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
|
||||
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
|
||||
This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
|
||||
}ADC_MultiModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Constants ADC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Common_mode ADC Common Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_MODE_INDEPENDENT 0x00000000U
|
||||
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
|
||||
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
|
||||
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
|
||||
#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
|
||||
#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
|
||||
#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
|
||||
#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
|
||||
#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
|
||||
#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
|
||||
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
|
||||
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
|
||||
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
|
||||
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
|
||||
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_injected_rank ADC Injected Rank
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 0x00000001U
|
||||
#define ADC_INJECTED_RANK_2 0x00000002U
|
||||
#define ADC_INJECTED_RANK_3 0x00000003U
|
||||
#define ADC_INJECTED_RANK_4 0x00000004U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADCEx_channels ADC Specific Channels
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
|
||||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
|
||||
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
|
||||
defined(STM32F412Cx)
|
||||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx ||
|
||||
STM32F412Vx || STM32F412Rx || STM32F412Cx */
|
||||
|
||||
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
|
||||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
|
||||
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
|
||||
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup ADC_Exported_Macros ADC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
||||
/**
|
||||
* @brief Disable internal path of ADC channel Vbat
|
||||
* @note Use case of this macro:
|
||||
* On devices STM32F42x and STM32F43x, ADC internal channels
|
||||
* Vbat and VrefInt share the same internal path, only
|
||||
* one of them can be enabled.This macro is to be used when ADC
|
||||
* channels Vbat and VrefInt are selected, and must be called
|
||||
* before starting conversion of ADC channel VrefInt in order
|
||||
* to disable ADC channel Vbat.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE))
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* I/O operation functions ******************************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
|
||||
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* Peripheral Control functions *************************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
|
||||
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Constants ADC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Macros ADC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
|
||||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
|
||||
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
|
||||
defined(STM32F412Cx)
|
||||
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE ||
|
||||
STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
|
||||
|
||||
#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \
|
||||
defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \
|
||||
defined(STM32F469xx) || defined(STM32F479xx)
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
|
||||
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
|
||||
#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
|
||||
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
|
||||
((MODE) == ADC_DUALMODE_INJECSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_REGSIMULT) || \
|
||||
((MODE) == ADC_DUALMODE_INTERL) || \
|
||||
((MODE) == ADC_DUALMODE_ALTERTRIG) || \
|
||||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
|
||||
((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
|
||||
((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
|
||||
((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
|
||||
((MODE) == ADC_TRIPLEMODE_INTERL) || \
|
||||
((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
|
||||
#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
|
||||
((MODE) == ADC_DMAACCESSMODE_1) || \
|
||||
((MODE) == ADC_DMAACCESSMODE_2) || \
|
||||
((MODE) == ADC_DMAACCESSMODE_3))
|
||||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
|
||||
((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
|
||||
((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
|
||||
((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U))
|
||||
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
* @param _CHANNELNB_ Channel number.
|
||||
* @param _RANKNB_ Rank number.
|
||||
* @param _JSQR_JL_ Sequence length.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
|
||||
|
||||
/**
|
||||
* @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1
|
||||
* if available (ADC2, ADC3 availability depends on STM32 product)
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @retval Common control register ADC123 or ADC1
|
||||
*/
|
||||
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
#define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON
|
||||
#else
|
||||
#define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON
|
||||
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Private_Functions ADC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_ADC_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,848 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_can.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CAN HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_HAL_CAN_H
|
||||
#define STM32F4xx_HAL_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (CAN1)
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Types CAN Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
|
||||
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
|
||||
HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
|
||||
HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
|
||||
HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
|
||||
HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
|
||||
|
||||
} HAL_CAN_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of @ref CAN_operating_mode */
|
||||
|
||||
uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
|
||||
is allowed to lengthen or shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of @ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
|
||||
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
} CAN_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN filter configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
|
||||
For single CAN instance(14 dedicated filter banks),
|
||||
this parameter must be a number between Min_Data = 0 and Max_Data = 13.
|
||||
For dual CAN instances(28 filter banks shared),
|
||||
this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||
|
||||
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint32_t FilterScale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
uint32_t FilterActivation; /*!< Enable or disable the filter.
|
||||
This parameter can be a value of @ref CAN_filter_activation */
|
||||
|
||||
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
|
||||
For single CAN instances, this parameter is meaningless.
|
||||
For dual CAN instances, all filter banks with lower index are assigned to master
|
||||
CAN instance, whereas all filter banks with greater index are assigned to slave
|
||||
CAN instance.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
|
||||
|
||||
} CAN_FilterTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
|
||||
of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
|
||||
@note: Time Triggered Communication Mode must be enabled.
|
||||
@note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
} CAN_TxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message header structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
|
||||
|
||||
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_identifier_type */
|
||||
|
||||
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
|
||||
This parameter can be a value of @ref CAN_remote_transmission_request */
|
||||
|
||||
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
|
||||
|
||||
uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
|
||||
@note: Time Triggered Communication Mode must be enabled.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
|
||||
|
||||
uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
|
||||
|
||||
} CAN_RxHeaderTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CAN handle Structure definition
|
||||
*/
|
||||
typedef struct __CAN_HandleTypeDef
|
||||
{
|
||||
CAN_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CAN_InitTypeDef Init; /*!< CAN required parameters */
|
||||
|
||||
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CAN Error code.
|
||||
This parameter can be a value of @ref CAN_Error_Code */
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
|
||||
void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
|
||||
void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
|
||||
void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
|
||||
void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
|
||||
void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
|
||||
void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
|
||||
void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
|
||||
void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
|
||||
void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
|
||||
void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
|
||||
void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
|
||||
void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
} CAN_HandleTypeDef;
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/**
|
||||
* @brief HAL CAN common Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
|
||||
HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
|
||||
HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
|
||||
HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
|
||||
HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
|
||||
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
|
||||
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
|
||||
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
|
||||
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
|
||||
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
|
||||
|
||||
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
|
||||
HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
|
||||
|
||||
} HAL_CAN_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CAN Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
|
||||
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CAN_Exported_Constants CAN Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Error_Code CAN Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
|
||||
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
|
||||
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
|
||||
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
|
||||
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
|
||||
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
|
||||
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
|
||||
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
|
||||
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
|
||||
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
|
||||
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
|
||||
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
|
||||
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
|
||||
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
|
||||
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
|
||||
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
|
||||
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
|
||||
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_InitStatus CAN InitStatus
|
||||
* @{
|
||||
*/
|
||||
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
|
||||
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_operating_mode CAN Operating Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
|
||||
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
|
||||
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
|
||||
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
|
||||
* @{
|
||||
*/
|
||||
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
|
||||
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
|
||||
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
|
||||
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
|
||||
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
|
||||
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
|
||||
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
|
||||
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
|
||||
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
|
||||
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
|
||||
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
|
||||
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
|
||||
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
|
||||
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
|
||||
* @{
|
||||
*/
|
||||
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
|
||||
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
|
||||
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
|
||||
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
|
||||
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
|
||||
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
|
||||
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
|
||||
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_mode CAN Filter Mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
|
||||
#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_scale CAN Filter Scale
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
|
||||
#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_activation CAN Filter Activation
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
|
||||
#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
|
||||
#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_identifier_type CAN Identifier Type
|
||||
* @{
|
||||
*/
|
||||
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
|
||||
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
|
||||
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
|
||||
* @{
|
||||
*/
|
||||
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
|
||||
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
|
||||
* @{
|
||||
*/
|
||||
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
|
||||
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
|
||||
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags CAN Flags
|
||||
* @{
|
||||
*/
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
|
||||
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
|
||||
#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
|
||||
#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
|
||||
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
|
||||
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
|
||||
#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
|
||||
#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
|
||||
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
|
||||
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
|
||||
#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
|
||||
#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
|
||||
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
|
||||
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
|
||||
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
|
||||
#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
|
||||
#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
|
||||
#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
|
||||
#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
|
||||
#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
|
||||
#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
|
||||
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
|
||||
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
|
||||
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
|
||||
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
|
||||
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
|
||||
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_Interrupts CAN Interrupts
|
||||
* @{
|
||||
*/
|
||||
/* Transmit Interrupt */
|
||||
#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
|
||||
#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
|
||||
#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
|
||||
#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
|
||||
#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
|
||||
#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
|
||||
#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
|
||||
#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
|
||||
#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
|
||||
#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
|
||||
#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Exported_Macros CAN Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CAN handle state
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_CAN_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
|
||||
#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt sources to enable.
|
||||
* This parameter can be any combination of @arg CAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified CAN interrupts.
|
||||
* @param __HANDLE__ CAN handle.
|
||||
* @param __INTERRUPT__ CAN Interrupt sources to disable.
|
||||
* This parameter can be any combination of @arg CAN_Interrupts
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
|
||||
* This parameter can be a value of @arg CAN_Interrupts
|
||||
* @retval The state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CAN flag is set or not.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of @arg CAN_flags
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
/** @brief Clear the specified CAN pending flag.
|
||||
* @param __HANDLE__ specifies the CAN Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
|
||||
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
|
||||
* @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
|
||||
* @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
|
||||
* @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
|
||||
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
|
||||
* @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
|
||||
* @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
|
||||
* @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
|
||||
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
|
||||
* @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
|
||||
* @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
|
||||
* @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
|
||||
* @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
|
||||
* @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
|
||||
* @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
|
||||
* @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
|
||||
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
|
||||
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
|
||||
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
|
||||
|
||||
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
|
||||
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
|
||||
|
||||
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group3 Control functions
|
||||
* @brief Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Control functions **********************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
|
||||
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
|
||||
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
|
||||
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
|
||||
* @brief Interrupts management
|
||||
* @{
|
||||
*/
|
||||
/* Interrupts management ******************************************************/
|
||||
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
|
||||
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
|
||||
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
|
||||
* @brief Callback functions
|
||||
* @{
|
||||
*/
|
||||
/* Callbacks functions ********************************************************/
|
||||
|
||||
void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
|
||||
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
|
||||
* @brief CAN Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
|
||||
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
|
||||
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Types CAN Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Variables CAN Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Constants CAN Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define CAN_FLAG_MASK (0x000000FFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Macros -----------------------------------------------------------*/
|
||||
/** @defgroup CAN_Private_Macros CAN Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
|
||||
((MODE) == CAN_MODE_LOOPBACK)|| \
|
||||
((MODE) == CAN_MODE_SILENT) || \
|
||||
((MODE) == CAN_MODE_SILENT_LOOPBACK))
|
||||
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
|
||||
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
|
||||
#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
|
||||
((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
|
||||
((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
|
||||
((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
|
||||
((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
|
||||
((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
|
||||
((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
|
||||
((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
|
||||
#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
|
||||
((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
|
||||
((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
|
||||
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
|
||||
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
|
||||
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
|
||||
#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
|
||||
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
|
||||
((MODE) == CAN_FILTERMODE_IDLIST))
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
|
||||
((SCALE) == CAN_FILTERSCALE_32BIT))
|
||||
#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
|
||||
((ACTIVATION) == CAN_FILTER_ENABLE))
|
||||
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
|
||||
((FIFO) == CAN_FILTER_FIFO1))
|
||||
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
|
||||
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
|
||||
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
|
||||
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
|
||||
((IDTYPE) == CAN_ID_EXT))
|
||||
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
|
||||
#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
|
||||
#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
|
||||
CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
|
||||
CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
|
||||
CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
|
||||
CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
|
||||
CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
|
||||
CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* CAN1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F4xx_HAL_CAN_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,794 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_cec.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CEC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_HAL_CEC_H
|
||||
#define STM32F4xx_HAL_CEC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
#if defined (CEC)
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Types CEC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CEC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
|
||||
It can be one of @ref CEC_Signal_Free_Time
|
||||
and belongs to the set {0,...,7} where
|
||||
0x0 is the default configuration
|
||||
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
|
||||
|
||||
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
|
||||
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
|
||||
or CEC_EXTENDED_TOLERANCE */
|
||||
|
||||
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
|
||||
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
|
||||
CEC_RX_STOP_ON_BRE: reception is stopped. */
|
||||
|
||||
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Bit Rising Error detection.
|
||||
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
|
||||
|
||||
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
|
||||
CEC line upon Long Bit Period Error detection.
|
||||
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
|
||||
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
|
||||
|
||||
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
|
||||
upon an error detected on a broadcast message.
|
||||
|
||||
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
|
||||
|
||||
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
|
||||
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
|
||||
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
|
||||
b) LBPE detection: error-bit generation on the CEC line
|
||||
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
|
||||
|
||||
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
|
||||
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
|
||||
there is no error-bit generation in case of Short Bit Period Error detection in
|
||||
a broadcast message while LSTN bit is set. */
|
||||
|
||||
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
|
||||
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
|
||||
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
|
||||
|
||||
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
|
||||
|
||||
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
|
||||
own address (OAR). Messages addressed to different destination are ignored.
|
||||
Broadcast messages are always received.
|
||||
|
||||
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
|
||||
address (OAR) with positive acknowledge. Messages addressed to different destination
|
||||
are received, but without interfering with the CEC bus: no acknowledge sent. */
|
||||
|
||||
uint16_t OwnAddress; /*!< Own addresses configuration
|
||||
This parameter can be a value of @ref CEC_OWN_ADDRESS */
|
||||
|
||||
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
|
||||
|
||||
|
||||
} CEC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC State definition
|
||||
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
|
||||
* - gState contains CEC state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7 (not used)
|
||||
* x : Should be set to 0
|
||||
* b6 Error information
|
||||
* 0 : No Error
|
||||
* 1 : Error
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized. HAL CEC Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initialization status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_CEC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CEC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CEC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
{
|
||||
CEC_TypeDef *Instance; /*!< CEC registers base address */
|
||||
|
||||
CEC_InitTypeDef Init; /*!< CEC communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
|
||||
|
||||
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
|
||||
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
|
||||
in case error is reported */
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
|
||||
*hcec); /*!< CEC Tx Transfer completed callback */
|
||||
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
|
||||
} CEC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL CEC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
|
||||
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
|
||||
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
|
||||
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
|
||||
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
|
||||
} HAL_CEC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL CEC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
|
||||
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
|
||||
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Constants CEC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup CEC_State_Definition CEC State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup CEC_Error_Code CEC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
|
||||
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
|
||||
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
|
||||
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
|
||||
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
|
||||
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
|
||||
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
|
||||
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
|
||||
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
|
||||
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
|
||||
* @{
|
||||
*/
|
||||
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
|
||||
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
|
||||
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
|
||||
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
|
||||
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
|
||||
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
|
||||
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
|
||||
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
|
||||
* @{
|
||||
*/
|
||||
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
|
||||
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
|
||||
* @{
|
||||
*/
|
||||
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
|
||||
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
|
||||
* @{
|
||||
*/
|
||||
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
|
||||
* @{
|
||||
*/
|
||||
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
|
||||
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
|
||||
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Listening_Mode CEC Listening mode option
|
||||
* @{
|
||||
*/
|
||||
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
|
||||
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
|
||||
* @{
|
||||
*/
|
||||
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
|
||||
* @{
|
||||
*/
|
||||
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
|
||||
* @{
|
||||
*/
|
||||
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
|
||||
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
|
||||
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
|
||||
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
|
||||
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
|
||||
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
|
||||
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
|
||||
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
|
||||
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
|
||||
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
|
||||
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
|
||||
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
|
||||
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
|
||||
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
|
||||
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
|
||||
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
|
||||
#define CEC_IT_TXERR CEC_IER_TXERRIE
|
||||
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
|
||||
#define CEC_IT_TXEND CEC_IER_TXENDIE
|
||||
#define CEC_IT_TXBR CEC_IER_TXBRIE
|
||||
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
|
||||
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
|
||||
#define CEC_IT_LBPE CEC_IER_LBPEIE
|
||||
#define CEC_IT_SBPE CEC_IER_SBPEIE
|
||||
#define CEC_IT_BRE CEC_IER_BREIE
|
||||
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
|
||||
#define CEC_IT_RXEND CEC_IER_RXENDIE
|
||||
#define CEC_IT_RXBR CEC_IER_RXBRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_Flags_Definitions CEC Flags definition
|
||||
* @{
|
||||
*/
|
||||
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
|
||||
#define CEC_FLAG_TXERR CEC_ISR_TXERR
|
||||
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
|
||||
#define CEC_FLAG_TXEND CEC_ISR_TXEND
|
||||
#define CEC_FLAG_TXBR CEC_ISR_TXBR
|
||||
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
|
||||
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
|
||||
#define CEC_FLAG_LBPE CEC_ISR_LBPE
|
||||
#define CEC_FLAG_SBPE CEC_ISR_SBPE
|
||||
#define CEC_FLAG_BRE CEC_ISR_BRE
|
||||
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
|
||||
#define CEC_FLAG_RXEND CEC_ISR_RXEND
|
||||
#define CEC_FLAG_RXBR CEC_ISR_RXBR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
|
||||
* @{
|
||||
*/
|
||||
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
|
||||
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
|
||||
* @{
|
||||
*/
|
||||
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CEC_Exported_Macros CEC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CEC handle gstate & RxState
|
||||
* @param __HANDLE__ CEC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/** @brief Checks whether or not the specified CEC interrupt flag is set.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval ITStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
|
||||
|
||||
/** @brief Clears the interrupt or status flag when raised (write at 1)
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __FLAG__ specifies the interrupt/status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
|
||||
* @arg CEC_FLAG_TXERR: Tx Error.
|
||||
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
|
||||
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
|
||||
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
|
||||
* @arg CEC_FLAG_ARBLST: Arbitration Lost
|
||||
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
|
||||
* @arg CEC_FLAG_LBPE: Rx Long period Error
|
||||
* @arg CEC_FLAG_SBPE: Rx Short period Error
|
||||
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
|
||||
* @arg CEC_FLAG_RXOVR: Rx Overrun.
|
||||
* @arg CEC_FLAG_RXEND: End Of Reception.
|
||||
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
|
||||
|
||||
/** @brief Enables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disables the specified CEC interrupt.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Checks whether or not the specified CEC interrupt is enabled.
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __INTERRUPT__ specifies the CEC interrupt to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
|
||||
* @arg CEC_IT_TXERR: Tx Error IT Enable
|
||||
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
|
||||
* @arg CEC_IT_TXEND: End of transmission IT Enable
|
||||
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
|
||||
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
|
||||
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
|
||||
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
|
||||
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
|
||||
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
|
||||
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
|
||||
* @arg CEC_IT_RXEND: End Of Reception IT Enable
|
||||
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
|
||||
|
||||
/** @brief Enables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
|
||||
|
||||
/** @brief Disables the CEC device
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
|
||||
|
||||
/** @brief Set Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Set Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
|
||||
*/
|
||||
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Get Transmission Start flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
|
||||
|
||||
/** @brief Get Transmission End flag
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval FlagStatus
|
||||
*/
|
||||
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
|
||||
|
||||
/** @brief Clear OAR register
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
|
||||
|
||||
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
|
||||
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
|
||||
* @param __HANDLE__ specifies the CEC Handle.
|
||||
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CEC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
|
||||
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
|
||||
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
|
||||
|
||||
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
|
||||
pCEC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ***************************************************/
|
||||
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
|
||||
uint8_t *pData, uint32_t Size);
|
||||
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
|
||||
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
|
||||
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
|
||||
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CEC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
|
||||
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Types CEC Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Variables CEC Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Constants CEC Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Macros CEC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
|
||||
|
||||
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
|
||||
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
|
||||
|
||||
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
|
||||
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
|
||||
|
||||
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
|
||||
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
|
||||
|
||||
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
|
||||
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
|
||||
|
||||
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
|
||||
((__MODE__) == CEC_FULL_LISTENING_MODE))
|
||||
|
||||
/** @brief Check CEC message size.
|
||||
* The message size is the payload size: without counting the header,
|
||||
* it varies from 0 byte (ping operation, one header only, no payload) to
|
||||
* 15 bytes (1 opcode and up to 14 operands following the header).
|
||||
* @param __SIZE__ CEC message size.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
|
||||
|
||||
/** @brief Check CEC device Own Address Register (OAR) setting.
|
||||
* OAR address is written in a 15-bit field within CEC_CFGR register.
|
||||
* @param __ADDRESS__ CEC own address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
|
||||
|
||||
/** @brief Check CEC initiator or destination logical address setting.
|
||||
* Initiator and destination addresses are coded over 4 bits.
|
||||
* @param __ADDRESS__ CEC initiator or logical address.
|
||||
* @retval Test result (TRUE or FALSE).
|
||||
*/
|
||||
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CEC_Private_Functions CEC Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* CEC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F4xxHAL_CEC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,501 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_conf_template.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f4xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_CONF_H
|
||||
#define __STM32F4xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_PCCARD_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_I2S_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LTDC_MODULE_ENABLED
|
||||
#define HAL_DSI_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_FMPI2C_MODULE_ENABLED
|
||||
#define HAL_FMPSMBUS_MODULE_ENABLED
|
||||
#define HAL_SPDIFRX_MODULE_ENABLED
|
||||
#define HAL_DFSDM_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_MMC_MODULE_ENABLED
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define INSTRUCTION_CACHE_ENABLE 1U
|
||||
#define DATA_CACHE_ENABLE 1U
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
|
||||
#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2U
|
||||
#define MAC_ADDR1 0U
|
||||
#define MAC_ADDR2 0U
|
||||
#define MAC_ADDR3 0U
|
||||
#define MAC_ADDR4 0U
|
||||
#define MAC_ADDR5 0U
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848 PHY Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01U
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY 0x000000FFU
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY 0x00000FFFU
|
||||
|
||||
#define PHY_READ_TO 0x0000FFFFU
|
||||
#define PHY_WRITE_TO 0x0000FFFFU
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_can_legacy.h"
|
||||
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pccard.h"
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DSI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dsi.h"
|
||||
#endif /* HAL_DSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMPI2C_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_fmpi2c.h"
|
||||
#endif /* HAL_FMPI2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMPSMBUS_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_fmpsmbus.h"
|
||||
#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_dfsdm.h"
|
||||
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,410 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_CORTEX_H
|
||||
#define __STM32F4xx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
}MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
|
||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
|
||||
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
|
||||
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
|
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported Macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,184 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_HAL_CRC_H
|
||||
#define STM32F4xx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F4xx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,685 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_CRYP_H
|
||||
#define __STM32F4xx_HAL_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined (AES) || defined (CRYP)
|
||||
/** @addtogroup CRYP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
|
||||
AES Algorithm ECB/CBC/CTR/GCM or CCM
|
||||
This parameter can be a value of @ref CRYP_Algorithm_Mode */
|
||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer in word */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
|
||||
} CRYP_ConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRYP State Structure definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
|
||||
} HAL_CRYP_STATETypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRYP handle Structure definition
|
||||
*/
|
||||
|
||||
typedef struct __CRYP_HandleTypeDef
|
||||
{
|
||||
#if defined (CRYP)
|
||||
CRYP_TypeDef *Instance; /*!< CRYP registers base address */
|
||||
#else /* AES*/
|
||||
AES_TypeDef *Instance; /*!< AES Register base address */
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
|
||||
|
||||
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption.
|
||||
This parameter can be a value of ENABLE/DISABLE */
|
||||
|
||||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */
|
||||
|
||||
__IO uint16_t CrypInCount; /*!< Counter of input data */
|
||||
|
||||
__IO uint16_t CrypOutCount; /*!< Counter of output data */
|
||||
|
||||
uint16_t Size; /*!< length of input data in word */
|
||||
|
||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
||||
|
||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
||||
configuration can be skipped */
|
||||
|
||||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
||||
for a single signature computation after several
|
||||
messages processing */
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
|
||||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
|
||||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
||||
} CRYP_HandleTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
|
||||
* @brief HAL CRYP Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */
|
||||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */
|
||||
HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */
|
||||
|
||||
HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */
|
||||
HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */
|
||||
|
||||
} HAL_CRYP_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
|
||||
* @brief HAL CRYP Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
|
||||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
|
||||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
|
||||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
|
||||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
|
||||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
|
||||
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
|
||||
#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
|
||||
#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
|
||||
#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
|
||||
#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
|
||||
#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
|
||||
#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
|
||||
#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
|
||||
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
|
||||
#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
|
||||
#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
|
||||
#endif /* GCM CCM defined*/
|
||||
#else /* AES*/
|
||||
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
|
||||
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
|
||||
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
|
||||
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
|
||||
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
||||
* @{
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
#define CRYP_KEYSIZE_128B 0x00000000U
|
||||
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
|
||||
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
|
||||
#else /* AES*/
|
||||
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
|
||||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
|
||||
#endif /* End AES or CRYP */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
#define CRYP_DATATYPE_32B 0x00000000U
|
||||
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
|
||||
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
|
||||
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
|
||||
#else /* AES*/
|
||||
#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
|
||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
|
||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
|
||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Interrupt CRYP Interrupt
|
||||
* @{
|
||||
*/
|
||||
#if defined (CRYP)
|
||||
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
|
||||
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
|
||||
#else /* AES*/
|
||||
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
|
||||
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
|
||||
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
|
||||
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Flags CRYP Flags
|
||||
* @{
|
||||
*/
|
||||
#if defined (CRYP)
|
||||
/* Flags in the SR register */
|
||||
#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */
|
||||
#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */
|
||||
#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */
|
||||
#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */
|
||||
#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data
|
||||
or a key preparation (for AES decryption). */
|
||||
/* Flags in the RISR register */
|
||||
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
|
||||
#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
|
||||
#else /* AES*/
|
||||
/* status flags */
|
||||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
|
||||
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
|
||||
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
|
||||
/* clearing flags */
|
||||
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
|
||||
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
|
||||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRYP handle state
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CRYP peripheral.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
|
||||
#else /* AES*/
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/** @brief Check whether the specified CRYP status flag is set or not.
|
||||
* @param __FLAG__: specifies the flag to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
|
||||
* or a key preparation (for AES decryption).
|
||||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
|
||||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
|
||||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
|
||||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
|
||||
* @arg CRYP_FLAG_OFFU: Output FIFO is full
|
||||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define CRYP_FLAG_MASK 0x0000001FU
|
||||
#if defined(CRYP)
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
|
||||
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
|
||||
#else /* AES*/
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/** @brief Clear the CRYP pending status flag.
|
||||
* @param __FLAG__: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
|
||||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#if defined(AES)
|
||||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
||||
* @param __INTERRUPT__: CRYP interrupt source to check
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
#endif /* AES */
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
||||
* @param __INTERRUPT__: specifies the interrupt to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
|
||||
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#else /* AES*/
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
* @param __INTERRUPT__: CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
|
||||
#else /* AES*/
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP interrupt.
|
||||
* @param __INTERRUPT__: CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @param __HANDLE__: specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
|
||||
#else /* AES*/
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
|
||||
/* Include CRYP HAL Extended module */
|
||||
#include "stm32f4xx_hal_cryp_ex.h"
|
||||
#endif /* AES or GCM CCM defined*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
|
||||
pCRYP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* encryption/decryption ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
|
||||
uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt Handler functions **********************************************/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#if defined(CRYP)
|
||||
#if defined (CRYP_CR_ALGOMODE_AES_GCM)
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
|
||||
((ALGORITHM) == CRYP_DES_CBC) || \
|
||||
((ALGORITHM) == CRYP_TDES_ECB) || \
|
||||
((ALGORITHM) == CRYP_TDES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM) || \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
#else /*NO GCM CCM */
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
|
||||
((ALGORITHM) == CRYP_DES_CBC) || \
|
||||
((ALGORITHM) == CRYP_TDES_ECB) || \
|
||||
((ALGORITHM) == CRYP_TDES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR))
|
||||
#endif /* GCM CCM defined*/
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
#else /* AES*/
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
|
||||
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
#endif /* End AES or CRYP */
|
||||
|
||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_16B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_8B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_1B))
|
||||
|
||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* TinyAES or CRYP*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_CRYP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,144 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_CRYP_EX_H
|
||||
#define __STM32F4xx_HAL_CRYP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined (CRYP) || defined (AES)
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* CRYP||AES */
|
||||
|
||||
#if defined (AES)
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* AES */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_CRYP_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,482 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_HAL_DAC_H
|
||||
#define STM32F4xx_HAL_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Types DAC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
|
||||
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
|
||||
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
|
||||
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
|
||||
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
|
||||
|
||||
} HAL_DAC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __DAC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
{
|
||||
DAC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DAC locking object */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DAC Error code */
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
} DAC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DAC Configuration regular Channel structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
|
||||
} DAC_ChannelConfTypeDef;
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL DAC Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
|
||||
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
|
||||
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
|
||||
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
|
||||
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
|
||||
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
|
||||
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
|
||||
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
|
||||
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
|
||||
} HAL_DAC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DAC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants DAC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Error_Code DAC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
|
||||
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
|
||||
#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 0x00000000U
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_CHANNEL_2 0x00000010U
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment DAC data alignment
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R 0x00000000U
|
||||
#define DAC_ALIGN_12B_L 0x00000004U
|
||||
#define DAC_ALIGN_8B_R 0x00000008U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_flags_definition DAC flags definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_IT_definition DAC IT definition
|
||||
* @{
|
||||
*/
|
||||
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Macros DAC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DAC handle state.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Enable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __DAC_Channel__ specifies the DAC channel
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Disable the DAC channel.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __DAC_Channel__ specifies the DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
|
||||
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
|
||||
|
||||
/** @brief Set DHR12R1 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/** @brief Set DHR12R2 alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
/** @brief Set DHR12RD alignment.
|
||||
* @param __ALIGNMENT__ specifies the DAC alignment
|
||||
* @retval None
|
||||
*/
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
|
||||
|
||||
/** @brief Enable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the DAC interrupt.
|
||||
* @param __HANDLE__ specifies the DAC handle
|
||||
* @param __INTERRUPT__ specifies the DAC interrupt.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified DAC interrupt source is enabled or not.
|
||||
* @param __HANDLE__ DAC handle
|
||||
* @param __INTERRUPT__ DAC interrupt source to check
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
|
||||
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
|
||||
* @retval State of interruption (SET or RESET)
|
||||
*/
|
||||
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
|
||||
& (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Get the selected DAC's flag status.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to get.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the DAC's flag.
|
||||
* @param __HANDLE__ specifies the DAC handle.
|
||||
* @param __FLAG__ specifies the DAC flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
|
||||
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Macros DAC Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
|
||||
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
|
||||
((CHANNEL) == DAC_CHANNEL_2))
|
||||
#else
|
||||
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
|
||||
((ALIGN) == DAC_ALIGN_12B_L) || \
|
||||
((ALIGN) == DAC_ALIGN_8B_R))
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DAC HAL Extended module */
|
||||
#include "stm32f4xx_hal_dac_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
|
||||
uint32_t Alignment);
|
||||
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
|
||||
|
||||
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
|
||||
/* DAC callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
|
||||
pDAC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
|
||||
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
|
||||
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions DAC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32F4xx_HAL_DAC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,207 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DAC HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32F4xx_HAL_DAC_EX_H
|
||||
#define STM32F4xx_HAL_DAC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
#if defined(DAC)
|
||||
|
||||
/** @addtogroup DACEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DACEx_Private_Macros DACEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
|
||||
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
|
||||
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
|
||||
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Extended features functions ***********************************************/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#endif
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
|
||||
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
|
||||
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
|
||||
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
#endif
|
||||
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DACEx_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#if defined(DAC_CHANNEL2_SUPPORT)
|
||||
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
|
||||
/* are called by HAL_DAC_Start_DMA */
|
||||
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
|
||||
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
|
||||
#endif /* DAC_CHANNEL2_SUPPORT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* DAC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32F4xx_HAL_DAC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,567 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dcmi.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DCMI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_DCMI_H
|
||||
#define __STM32F4xx_HAL_DCMI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
|
||||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
|
||||
defined(STM32F479xx)
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
/* Include DCMI HAL Extended module */
|
||||
/* (include on top of file since DCMI structures are defined in extended file) */
|
||||
#include "stm32f4xx_hal_dcmi_ex.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI DCMI
|
||||
* @brief DCMI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Types DCMI Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DCMI Embedded Synchronisation CODE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
|
||||
uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */
|
||||
uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */
|
||||
uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */
|
||||
}DCMI_SyncUnmaskTypeDef;
|
||||
/**
|
||||
* @brief HAL DCMI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
|
||||
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
|
||||
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
|
||||
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
|
||||
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
|
||||
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
|
||||
}HAL_DCMI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI handle Structure definition
|
||||
*/
|
||||
typedef struct __DCMI_HandleTypeDef
|
||||
{
|
||||
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
|
||||
|
||||
DCMI_InitTypeDef Init; /*!< DCMI parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DCMI locking object */
|
||||
|
||||
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
|
||||
|
||||
__IO uint32_t XferCount; /*!< DMA transfer counter */
|
||||
|
||||
__IO uint32_t XferSize; /*!< DMA transfer size */
|
||||
|
||||
uint32_t XferTransferNumber; /*!< DMA transfer number */
|
||||
|
||||
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
|
||||
|
||||
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DCMI Error code */
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
void (* FrameEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */
|
||||
void (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */
|
||||
void (* LineEventCallback ) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */
|
||||
void (* ErrorCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */
|
||||
void (* MspInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */
|
||||
void (* MspDeInitCallback) ( struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
}DCMI_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
typedef enum
|
||||
{
|
||||
HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */
|
||||
HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */
|
||||
HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */
|
||||
HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */
|
||||
HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */
|
||||
HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */
|
||||
|
||||
}HAL_DCMI_CallbackIDTypeDef;
|
||||
|
||||
typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi);
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Error_Code DCMI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DCMI_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DCMI_ERROR_OVR 0x00000001U /*!< Overrun error */
|
||||
#define HAL_DCMI_ERROR_SYNC 0x00000002U /*!< Synchronization error */
|
||||
#define HAL_DCMI_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||
#define HAL_DCMI_ERROR_DMA 0x00000040U /*!< DMA error */
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid callback error */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MODE_CONTINUOUS 0x00000000U /*!< The received data are transferred continuously
|
||||
into the destination memory through the DMA */
|
||||
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
|
||||
frame and then transfers a single frame through the DMA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_SYNCHRO_HARDWARE 0x00000000U /*!< Hardware synchronization data capture (frame/line start/stop)
|
||||
is synchronized with the HSYNC/VSYNC signals */
|
||||
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
|
||||
synchronization codes embedded in the data flow */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_PCKPOLARITY_FALLING 0x00000000U /*!< Pixel clock active on Falling edge */
|
||||
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_VSPOLARITY_LOW 0x00000000U /*!< Vertical synchronization active Low */
|
||||
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_HSPOLARITY_LOW 0x00000000U /*!< Horizontal synchronization active Low */
|
||||
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_JPEG_DISABLE 0x00000000U /*!< Mode JPEG Disabled */
|
||||
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_CR_ALL_FRAME 0x00000000U /*!< All frames are captured */
|
||||
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
|
||||
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_EXTEND_DATA_8B 0x00000000U /*!< Interface captures 8-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
|
||||
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_COORDINATE 0x3FFFU /*!< Window coordinate */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Height DCMI Window Height
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_WINDOW_HEIGHT 0x1FFFU /*!< Window Height */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)DCMI_CWSIZE_VLINE_Pos /*!< Required left shift to set crop window vertical line count */
|
||||
#define DCMI_POSITION_CWSTRT_VST (uint32_t)DCMI_CWSTRT_VST_Pos /*!< Required left shift to set crop window vertical start line count */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
|
||||
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
|
||||
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
|
||||
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
|
||||
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMI_Flags DCMI Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DCMI SR register
|
||||
*/
|
||||
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
|
||||
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
|
||||
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
|
||||
/**
|
||||
* @brief DCMI RIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS) /*!< Frame capture complete interrupt flag */
|
||||
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RISR_OVR_RIS) /*!< Overrun interrupt flag */
|
||||
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS) /*!< Synchronization error interrupt flag */
|
||||
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS) /*!< VSYNC interrupt flag */
|
||||
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS) /*!< Line interrupt flag */
|
||||
/**
|
||||
* @brief DCMI MIS register
|
||||
*/
|
||||
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
|
||||
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
|
||||
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
|
||||
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
|
||||
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DCMI handle state
|
||||
* @param __HANDLE__ specifies the DCMI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_DCMI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the DCMI.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable the DCMI.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
/**
|
||||
* @brief Get the DCMI pending flag.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be one of the following values (no combination allowed)
|
||||
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
|
||||
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
|
||||
* @arg DCMI_FLAG_FNE: FIFO empty flag
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
|
||||
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
|
||||
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
|
||||
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
|
||||
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
|
||||
* @retval The state of FLAG.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
|
||||
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
|
||||
(((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DCMI pending flags.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
|
||||
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
|
||||
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
|
||||
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
|
||||
* @arg DCMI_FLAG_LINERI: Line flag mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DCMI interrupts.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVR: Overrun interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DCMI interrupts.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVR: Overrun interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DCMI interrupt has occurred or not.
|
||||
* @param __HANDLE__ DCMI handle
|
||||
* @param __INTERRUPT__ specifies the DCMI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
|
||||
* @arg DCMI_IT_OVR: Overrun interrupt mask
|
||||
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
|
||||
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
|
||||
* @arg DCMI_IT_LINE: Line interrupt mask
|
||||
* @retval The state of INTERRUPT.
|
||||
*/
|
||||
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
|
||||
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
|
||||
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
|
||||
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);
|
||||
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
|
||||
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
|
||||
HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
|
||||
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Constants DCMI Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_MIS_INDEX 0x1000U /*!< DCMI MIS register index */
|
||||
#define DCMI_SR_INDEX 0x2000U /*!< DCMI SR register index */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup DCMI_Private_Macros DCMI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
|
||||
((MODE) == DCMI_MODE_SNAPSHOT))
|
||||
|
||||
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
|
||||
((MODE) == DCMI_SYNCHRO_EMBEDDED))
|
||||
|
||||
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
|
||||
((POLARITY) == DCMI_PCKPOLARITY_RISING))
|
||||
|
||||
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_VSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
|
||||
((POLARITY) == DCMI_HSPOLARITY_HIGH))
|
||||
|
||||
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
|
||||
((JPEG_MODE) == DCMI_JPEG_ENABLE))
|
||||
|
||||
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
|
||||
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
|
||||
|
||||
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_10B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_12B) || \
|
||||
((DATA) == DCMI_EXTEND_DATA_14B))
|
||||
|
||||
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
|
||||
|
||||
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
|
||||
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
|
||||
STM32F479xx */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_DCMI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,212 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_hal_dcmi_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DCMI Extension HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_HAL_DCMI_EX_H
|
||||
#define __STM32F4xx_HAL_DCMI_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
|
||||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
|
||||
defined(STM32F479xx)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_hal_def.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32F4xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DCMIEx
|
||||
* @brief DCMI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DCMIEx_Exported_Types DCMI Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
|
||||
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
|
||||
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
|
||||
}DCMI_CodesInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DCMI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
|
||||
This parameter can be a value of @ref DCMI_Synchronization_Mode */
|
||||
|
||||
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
|
||||
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
|
||||
|
||||
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
|
||||
|
||||
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
|
||||
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
|
||||
|
||||
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
|
||||
This parameter can be a value of @ref DCMI_Capture_Rate */
|
||||
|
||||
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
|
||||
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
|
||||
|
||||
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
|
||||
|
||||
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode
|
||||
This parameter can be a value of @ref DCMI_MODE_JPEG */
|
||||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
|
||||
This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */
|
||||
|
||||
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
|
||||
This parameter can be a value of @ref DCMIEx_Byte_Select_Start */
|
||||
|
||||
uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
|
||||
This parameter can be a value of @ref DCMIEx_Line_Select_Mode */
|
||||
|
||||
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
|
||||
This parameter can be a value of @ref DCMIEx_Line_Select_Start */
|
||||
|
||||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
}DCMI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_BSM_ALL 0x00000000U /*!< Interface captures all received data */
|
||||
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
|
||||
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
|
||||
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OEBS_ODD 0x00000000U /*!< Interface captures first data from the frame/line start, second one being dropped */
|
||||
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_LSM_ALL 0x00000000U /*!< Interface captures all received lines */
|
||||
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start
|
||||
* @{
|
||||
*/
|
||||
#define DCMI_OELS_ODD 0x00000000U /*!< Interface captures first line from the frame start, second one being dropped */
|
||||
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
#define DCMI_POSITION_ESCR_LSC (uint32_t)DCMI_ESCR_LSC_Pos /*!< Required left shift to set line start delimiter */
|
||||
#define DCMI_POSITION_ESCR_LEC (uint32_t)DCMI_ESCR_LEC_Pos /*!< Required left shift to set line end delimiter */
|
||||
#define DCMI_POSITION_ESCR_FEC (uint32_t)DCMI_ESCR_FEC_Pos /*!< Required left shift to set frame end delimiter */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
|
||||
((MODE) == DCMI_BSM_OTHER) || \
|
||||
((MODE) == DCMI_BSM_ALTERNATE_4) || \
|
||||
((MODE) == DCMI_BSM_ALTERNATE_2))
|
||||
|
||||
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
|
||||
((POLARITY) == DCMI_OEBS_EVEN))
|
||||
|
||||
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
|
||||
((MODE) == DCMI_LSM_ALTERNATE_2))
|
||||
|
||||
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
|
||||
((POLARITY) == DCMI_OELS_EVEN))
|
||||
#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
#endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
|
||||
STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
|
||||
STM32F479xx */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_HAL_DCMI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user