initial pcb design 4L

This commit is contained in:
2021-08-05 16:59:16 +02:00
parent a6f8c8843e
commit 4de32d73c0
18 changed files with 5738 additions and 6538 deletions

View File

@@ -20,15 +20,9 @@ Wire Wire Line
Wire Wire Line
5350 3650 5250 3650
Wire Wire Line
6550 3950 6650 3950
Wire Wire Line
6550 3650 6650 3650
Wire Wire Line
6850 3950 7250 3950
6550 3650 6600 3650
Wire Wire Line
7250 3950 7250 4150
Wire Wire Line
6850 3650 7550 3650
Wire Wire Line
7550 3650 7550 4150
Wire Wire Line
@@ -46,28 +40,6 @@ F 3 "" H 5950 3950 50 0001 C CNN
1 5950 3950
1 0 0 -1
$EndComp
$Comp
L Leo_muziekdoos-eagle-import:FERRITE-0805NO FB4
U 1 1 60FE0C65
P 6750 3650
F 0 "FB4" H 6700 3725 42 0000 L BNN
F 1 "Ferrite" H 6700 3525 42 0000 L BNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 6750 3650 50 0001 C CNN
F 3 "" H 6750 3650 50 0001 C CNN
1 6750 3650
1 0 0 -1
$EndComp
$Comp
L Leo_muziekdoos-eagle-import:FERRITE-0805NO FB5
U 1 1 60FE0C6B
P 6750 3950
F 0 "FB5" H 6700 4025 42 0000 L BNN
F 1 "Ferrite" H 6700 3825 42 0000 L BNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 6750 3950 50 0001 C CNN
F 3 "" H 6750 3950 50 0001 C CNN
1 6750 3950
1 0 0 -1
$EndComp
Text Notes 5450 3050 0 59 ~ 0
R1 Channel Selection:\nLEFT = VDD (0 Ohm)\nRIGHT = 370K (94*VDD-100)\nLEFT/2 + RIGHT/2 = 1.011M (222.2*VDD-100)
Text Notes 6850 3350 0 59 ~ 0
@@ -326,4 +298,32 @@ Text HLabel 7950 3750 2 50 Output ~ 0
SPKOUT+
Text HLabel 7950 3850 2 50 Output ~ 0
SPK_OUT-
$Comp
L Device:R R11
U 1 1 6110B32A
P 6750 3650
F 0 "R11" V 6543 3650 50 0000 C CNN
F 1 "R" V 6634 3650 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 6680 3650 50 0001 C CNN
F 3 "~" H 6750 3650 50 0001 C CNN
1 6750 3650
0 1 1 0
$EndComp
Wire Wire Line
6900 3650 7550 3650
$Comp
L Device:R R13
U 1 1 6110D506
P 6750 3950
F 0 "R13" V 6543 3950 50 0000 C CNN
F 1 "R" V 6634 3950 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 6680 3950 50 0001 C CNN
F 3 "~" H 6750 3950 50 0001 C CNN
1 6750 3950
0 1 1 0
$EndComp
Wire Wire Line
6550 3950 6600 3950
Wire Wire Line
6900 3950 7250 3950
$EndSCHEMATC