
leo_muziekdoos.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000198  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00001074  08000198  08000198  00010198  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000010  0800120c  0800120c  0001120c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  0800121c  0800121c  0002000c  2**0
                  CONTENTS
  4 .ARM          00000008  0800121c  0800121c  0001121c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08001224  08001224  0002000c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08001224  08001224  00011224  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  08001228  08001228  00011228  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000000c  20000000  0800122c  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000020  2000000c  08001238  0002000c  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  2000002c  08001238  0002002c  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  0002000c  2**0
                  CONTENTS, READONLY
 12 .debug_info   000032ce  00000000  00000000  0002003c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 00000cbf  00000000  00000000  0002330a  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_aranges 00000390  00000000  00000000  00023fd0  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_ranges 00000318  00000000  00000000  00024360  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_macro  000140e8  00000000  00000000  00024678  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_line   00003fd2  00000000  00000000  00038760  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_str    0007e790  00000000  00000000  0003c732  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .comment      00000053  00000000  00000000  000baec2  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00000ca0  00000000  00000000  000baf18  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

08000198 <__do_global_dtors_aux>:
 8000198:	b510      	push	{r4, lr}
 800019a:	4c05      	ldr	r4, [pc, #20]	; (80001b0 <__do_global_dtors_aux+0x18>)
 800019c:	7823      	ldrb	r3, [r4, #0]
 800019e:	b933      	cbnz	r3, 80001ae <__do_global_dtors_aux+0x16>
 80001a0:	4b04      	ldr	r3, [pc, #16]	; (80001b4 <__do_global_dtors_aux+0x1c>)
 80001a2:	b113      	cbz	r3, 80001aa <__do_global_dtors_aux+0x12>
 80001a4:	4804      	ldr	r0, [pc, #16]	; (80001b8 <__do_global_dtors_aux+0x20>)
 80001a6:	f3af 8000 	nop.w
 80001aa:	2301      	movs	r3, #1
 80001ac:	7023      	strb	r3, [r4, #0]
 80001ae:	bd10      	pop	{r4, pc}
 80001b0:	2000000c 	.word	0x2000000c
 80001b4:	00000000 	.word	0x00000000
 80001b8:	080011f4 	.word	0x080011f4

080001bc <frame_dummy>:
 80001bc:	b508      	push	{r3, lr}
 80001be:	4b03      	ldr	r3, [pc, #12]	; (80001cc <frame_dummy+0x10>)
 80001c0:	b11b      	cbz	r3, 80001ca <frame_dummy+0xe>
 80001c2:	4903      	ldr	r1, [pc, #12]	; (80001d0 <frame_dummy+0x14>)
 80001c4:	4803      	ldr	r0, [pc, #12]	; (80001d4 <frame_dummy+0x18>)
 80001c6:	f3af 8000 	nop.w
 80001ca:	bd08      	pop	{r3, pc}
 80001cc:	00000000 	.word	0x00000000
 80001d0:	20000010 	.word	0x20000010
 80001d4:	080011f4 	.word	0x080011f4

080001d8 <__aeabi_uldivmod>:
 80001d8:	b953      	cbnz	r3, 80001f0 <__aeabi_uldivmod+0x18>
 80001da:	b94a      	cbnz	r2, 80001f0 <__aeabi_uldivmod+0x18>
 80001dc:	2900      	cmp	r1, #0
 80001de:	bf08      	it	eq
 80001e0:	2800      	cmpeq	r0, #0
 80001e2:	bf1c      	itt	ne
 80001e4:	f04f 31ff 	movne.w	r1, #4294967295	; 0xffffffff
 80001e8:	f04f 30ff 	movne.w	r0, #4294967295	; 0xffffffff
 80001ec:	f000 b96e 	b.w	80004cc <__aeabi_idiv0>
 80001f0:	f1ad 0c08 	sub.w	ip, sp, #8
 80001f4:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80001f8:	f000 f806 	bl	8000208 <__udivmoddi4>
 80001fc:	f8dd e004 	ldr.w	lr, [sp, #4]
 8000200:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8000204:	b004      	add	sp, #16
 8000206:	4770      	bx	lr

08000208 <__udivmoddi4>:
 8000208:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 800020c:	9d08      	ldr	r5, [sp, #32]
 800020e:	4604      	mov	r4, r0
 8000210:	468c      	mov	ip, r1
 8000212:	2b00      	cmp	r3, #0
 8000214:	f040 8083 	bne.w	800031e <__udivmoddi4+0x116>
 8000218:	428a      	cmp	r2, r1
 800021a:	4617      	mov	r7, r2
 800021c:	d947      	bls.n	80002ae <__udivmoddi4+0xa6>
 800021e:	fab2 f282 	clz	r2, r2
 8000222:	b142      	cbz	r2, 8000236 <__udivmoddi4+0x2e>
 8000224:	f1c2 0020 	rsb	r0, r2, #32
 8000228:	fa24 f000 	lsr.w	r0, r4, r0
 800022c:	4091      	lsls	r1, r2
 800022e:	4097      	lsls	r7, r2
 8000230:	ea40 0c01 	orr.w	ip, r0, r1
 8000234:	4094      	lsls	r4, r2
 8000236:	ea4f 4817 	mov.w	r8, r7, lsr #16
 800023a:	0c23      	lsrs	r3, r4, #16
 800023c:	fbbc f6f8 	udiv	r6, ip, r8
 8000240:	fa1f fe87 	uxth.w	lr, r7
 8000244:	fb08 c116 	mls	r1, r8, r6, ip
 8000248:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 800024c:	fb06 f10e 	mul.w	r1, r6, lr
 8000250:	4299      	cmp	r1, r3
 8000252:	d909      	bls.n	8000268 <__udivmoddi4+0x60>
 8000254:	18fb      	adds	r3, r7, r3
 8000256:	f106 30ff 	add.w	r0, r6, #4294967295	; 0xffffffff
 800025a:	f080 8119 	bcs.w	8000490 <__udivmoddi4+0x288>
 800025e:	4299      	cmp	r1, r3
 8000260:	f240 8116 	bls.w	8000490 <__udivmoddi4+0x288>
 8000264:	3e02      	subs	r6, #2
 8000266:	443b      	add	r3, r7
 8000268:	1a5b      	subs	r3, r3, r1
 800026a:	b2a4      	uxth	r4, r4
 800026c:	fbb3 f0f8 	udiv	r0, r3, r8
 8000270:	fb08 3310 	mls	r3, r8, r0, r3
 8000274:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 8000278:	fb00 fe0e 	mul.w	lr, r0, lr
 800027c:	45a6      	cmp	lr, r4
 800027e:	d909      	bls.n	8000294 <__udivmoddi4+0x8c>
 8000280:	193c      	adds	r4, r7, r4
 8000282:	f100 33ff 	add.w	r3, r0, #4294967295	; 0xffffffff
 8000286:	f080 8105 	bcs.w	8000494 <__udivmoddi4+0x28c>
 800028a:	45a6      	cmp	lr, r4
 800028c:	f240 8102 	bls.w	8000494 <__udivmoddi4+0x28c>
 8000290:	3802      	subs	r0, #2
 8000292:	443c      	add	r4, r7
 8000294:	ea40 4006 	orr.w	r0, r0, r6, lsl #16
 8000298:	eba4 040e 	sub.w	r4, r4, lr
 800029c:	2600      	movs	r6, #0
 800029e:	b11d      	cbz	r5, 80002a8 <__udivmoddi4+0xa0>
 80002a0:	40d4      	lsrs	r4, r2
 80002a2:	2300      	movs	r3, #0
 80002a4:	e9c5 4300 	strd	r4, r3, [r5]
 80002a8:	4631      	mov	r1, r6
 80002aa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002ae:	b902      	cbnz	r2, 80002b2 <__udivmoddi4+0xaa>
 80002b0:	deff      	udf	#255	; 0xff
 80002b2:	fab2 f282 	clz	r2, r2
 80002b6:	2a00      	cmp	r2, #0
 80002b8:	d150      	bne.n	800035c <__udivmoddi4+0x154>
 80002ba:	1bcb      	subs	r3, r1, r7
 80002bc:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 80002c0:	fa1f f887 	uxth.w	r8, r7
 80002c4:	2601      	movs	r6, #1
 80002c6:	fbb3 fcfe 	udiv	ip, r3, lr
 80002ca:	0c21      	lsrs	r1, r4, #16
 80002cc:	fb0e 331c 	mls	r3, lr, ip, r3
 80002d0:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 80002d4:	fb08 f30c 	mul.w	r3, r8, ip
 80002d8:	428b      	cmp	r3, r1
 80002da:	d907      	bls.n	80002ec <__udivmoddi4+0xe4>
 80002dc:	1879      	adds	r1, r7, r1
 80002de:	f10c 30ff 	add.w	r0, ip, #4294967295	; 0xffffffff
 80002e2:	d202      	bcs.n	80002ea <__udivmoddi4+0xe2>
 80002e4:	428b      	cmp	r3, r1
 80002e6:	f200 80e9 	bhi.w	80004bc <__udivmoddi4+0x2b4>
 80002ea:	4684      	mov	ip, r0
 80002ec:	1ac9      	subs	r1, r1, r3
 80002ee:	b2a3      	uxth	r3, r4
 80002f0:	fbb1 f0fe 	udiv	r0, r1, lr
 80002f4:	fb0e 1110 	mls	r1, lr, r0, r1
 80002f8:	ea43 4401 	orr.w	r4, r3, r1, lsl #16
 80002fc:	fb08 f800 	mul.w	r8, r8, r0
 8000300:	45a0      	cmp	r8, r4
 8000302:	d907      	bls.n	8000314 <__udivmoddi4+0x10c>
 8000304:	193c      	adds	r4, r7, r4
 8000306:	f100 33ff 	add.w	r3, r0, #4294967295	; 0xffffffff
 800030a:	d202      	bcs.n	8000312 <__udivmoddi4+0x10a>
 800030c:	45a0      	cmp	r8, r4
 800030e:	f200 80d9 	bhi.w	80004c4 <__udivmoddi4+0x2bc>
 8000312:	4618      	mov	r0, r3
 8000314:	eba4 0408 	sub.w	r4, r4, r8
 8000318:	ea40 400c 	orr.w	r0, r0, ip, lsl #16
 800031c:	e7bf      	b.n	800029e <__udivmoddi4+0x96>
 800031e:	428b      	cmp	r3, r1
 8000320:	d909      	bls.n	8000336 <__udivmoddi4+0x12e>
 8000322:	2d00      	cmp	r5, #0
 8000324:	f000 80b1 	beq.w	800048a <__udivmoddi4+0x282>
 8000328:	2600      	movs	r6, #0
 800032a:	e9c5 0100 	strd	r0, r1, [r5]
 800032e:	4630      	mov	r0, r6
 8000330:	4631      	mov	r1, r6
 8000332:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000336:	fab3 f683 	clz	r6, r3
 800033a:	2e00      	cmp	r6, #0
 800033c:	d14a      	bne.n	80003d4 <__udivmoddi4+0x1cc>
 800033e:	428b      	cmp	r3, r1
 8000340:	d302      	bcc.n	8000348 <__udivmoddi4+0x140>
 8000342:	4282      	cmp	r2, r0
 8000344:	f200 80b8 	bhi.w	80004b8 <__udivmoddi4+0x2b0>
 8000348:	1a84      	subs	r4, r0, r2
 800034a:	eb61 0103 	sbc.w	r1, r1, r3
 800034e:	2001      	movs	r0, #1
 8000350:	468c      	mov	ip, r1
 8000352:	2d00      	cmp	r5, #0
 8000354:	d0a8      	beq.n	80002a8 <__udivmoddi4+0xa0>
 8000356:	e9c5 4c00 	strd	r4, ip, [r5]
 800035a:	e7a5      	b.n	80002a8 <__udivmoddi4+0xa0>
 800035c:	f1c2 0320 	rsb	r3, r2, #32
 8000360:	fa20 f603 	lsr.w	r6, r0, r3
 8000364:	4097      	lsls	r7, r2
 8000366:	fa01 f002 	lsl.w	r0, r1, r2
 800036a:	ea4f 4e17 	mov.w	lr, r7, lsr #16
 800036e:	40d9      	lsrs	r1, r3
 8000370:	4330      	orrs	r0, r6
 8000372:	0c03      	lsrs	r3, r0, #16
 8000374:	fbb1 f6fe 	udiv	r6, r1, lr
 8000378:	fa1f f887 	uxth.w	r8, r7
 800037c:	fb0e 1116 	mls	r1, lr, r6, r1
 8000380:	ea43 4301 	orr.w	r3, r3, r1, lsl #16
 8000384:	fb06 f108 	mul.w	r1, r6, r8
 8000388:	4299      	cmp	r1, r3
 800038a:	fa04 f402 	lsl.w	r4, r4, r2
 800038e:	d909      	bls.n	80003a4 <__udivmoddi4+0x19c>
 8000390:	18fb      	adds	r3, r7, r3
 8000392:	f106 3cff 	add.w	ip, r6, #4294967295	; 0xffffffff
 8000396:	f080 808d 	bcs.w	80004b4 <__udivmoddi4+0x2ac>
 800039a:	4299      	cmp	r1, r3
 800039c:	f240 808a 	bls.w	80004b4 <__udivmoddi4+0x2ac>
 80003a0:	3e02      	subs	r6, #2
 80003a2:	443b      	add	r3, r7
 80003a4:	1a5b      	subs	r3, r3, r1
 80003a6:	b281      	uxth	r1, r0
 80003a8:	fbb3 f0fe 	udiv	r0, r3, lr
 80003ac:	fb0e 3310 	mls	r3, lr, r0, r3
 80003b0:	ea41 4103 	orr.w	r1, r1, r3, lsl #16
 80003b4:	fb00 f308 	mul.w	r3, r0, r8
 80003b8:	428b      	cmp	r3, r1
 80003ba:	d907      	bls.n	80003cc <__udivmoddi4+0x1c4>
 80003bc:	1879      	adds	r1, r7, r1
 80003be:	f100 3cff 	add.w	ip, r0, #4294967295	; 0xffffffff
 80003c2:	d273      	bcs.n	80004ac <__udivmoddi4+0x2a4>
 80003c4:	428b      	cmp	r3, r1
 80003c6:	d971      	bls.n	80004ac <__udivmoddi4+0x2a4>
 80003c8:	3802      	subs	r0, #2
 80003ca:	4439      	add	r1, r7
 80003cc:	1acb      	subs	r3, r1, r3
 80003ce:	ea40 4606 	orr.w	r6, r0, r6, lsl #16
 80003d2:	e778      	b.n	80002c6 <__udivmoddi4+0xbe>
 80003d4:	f1c6 0c20 	rsb	ip, r6, #32
 80003d8:	fa03 f406 	lsl.w	r4, r3, r6
 80003dc:	fa22 f30c 	lsr.w	r3, r2, ip
 80003e0:	431c      	orrs	r4, r3
 80003e2:	fa20 f70c 	lsr.w	r7, r0, ip
 80003e6:	fa01 f306 	lsl.w	r3, r1, r6
 80003ea:	ea4f 4e14 	mov.w	lr, r4, lsr #16
 80003ee:	fa21 f10c 	lsr.w	r1, r1, ip
 80003f2:	431f      	orrs	r7, r3
 80003f4:	0c3b      	lsrs	r3, r7, #16
 80003f6:	fbb1 f9fe 	udiv	r9, r1, lr
 80003fa:	fa1f f884 	uxth.w	r8, r4
 80003fe:	fb0e 1119 	mls	r1, lr, r9, r1
 8000402:	ea43 4101 	orr.w	r1, r3, r1, lsl #16
 8000406:	fb09 fa08 	mul.w	sl, r9, r8
 800040a:	458a      	cmp	sl, r1
 800040c:	fa02 f206 	lsl.w	r2, r2, r6
 8000410:	fa00 f306 	lsl.w	r3, r0, r6
 8000414:	d908      	bls.n	8000428 <__udivmoddi4+0x220>
 8000416:	1861      	adds	r1, r4, r1
 8000418:	f109 30ff 	add.w	r0, r9, #4294967295	; 0xffffffff
 800041c:	d248      	bcs.n	80004b0 <__udivmoddi4+0x2a8>
 800041e:	458a      	cmp	sl, r1
 8000420:	d946      	bls.n	80004b0 <__udivmoddi4+0x2a8>
 8000422:	f1a9 0902 	sub.w	r9, r9, #2
 8000426:	4421      	add	r1, r4
 8000428:	eba1 010a 	sub.w	r1, r1, sl
 800042c:	b2bf      	uxth	r7, r7
 800042e:	fbb1 f0fe 	udiv	r0, r1, lr
 8000432:	fb0e 1110 	mls	r1, lr, r0, r1
 8000436:	ea47 4701 	orr.w	r7, r7, r1, lsl #16
 800043a:	fb00 f808 	mul.w	r8, r0, r8
 800043e:	45b8      	cmp	r8, r7
 8000440:	d907      	bls.n	8000452 <__udivmoddi4+0x24a>
 8000442:	19e7      	adds	r7, r4, r7
 8000444:	f100 31ff 	add.w	r1, r0, #4294967295	; 0xffffffff
 8000448:	d22e      	bcs.n	80004a8 <__udivmoddi4+0x2a0>
 800044a:	45b8      	cmp	r8, r7
 800044c:	d92c      	bls.n	80004a8 <__udivmoddi4+0x2a0>
 800044e:	3802      	subs	r0, #2
 8000450:	4427      	add	r7, r4
 8000452:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
 8000456:	eba7 0708 	sub.w	r7, r7, r8
 800045a:	fba0 8902 	umull	r8, r9, r0, r2
 800045e:	454f      	cmp	r7, r9
 8000460:	46c6      	mov	lr, r8
 8000462:	4649      	mov	r1, r9
 8000464:	d31a      	bcc.n	800049c <__udivmoddi4+0x294>
 8000466:	d017      	beq.n	8000498 <__udivmoddi4+0x290>
 8000468:	b15d      	cbz	r5, 8000482 <__udivmoddi4+0x27a>
 800046a:	ebb3 020e 	subs.w	r2, r3, lr
 800046e:	eb67 0701 	sbc.w	r7, r7, r1
 8000472:	fa07 fc0c 	lsl.w	ip, r7, ip
 8000476:	40f2      	lsrs	r2, r6
 8000478:	ea4c 0202 	orr.w	r2, ip, r2
 800047c:	40f7      	lsrs	r7, r6
 800047e:	e9c5 2700 	strd	r2, r7, [r5]
 8000482:	2600      	movs	r6, #0
 8000484:	4631      	mov	r1, r6
 8000486:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800048a:	462e      	mov	r6, r5
 800048c:	4628      	mov	r0, r5
 800048e:	e70b      	b.n	80002a8 <__udivmoddi4+0xa0>
 8000490:	4606      	mov	r6, r0
 8000492:	e6e9      	b.n	8000268 <__udivmoddi4+0x60>
 8000494:	4618      	mov	r0, r3
 8000496:	e6fd      	b.n	8000294 <__udivmoddi4+0x8c>
 8000498:	4543      	cmp	r3, r8
 800049a:	d2e5      	bcs.n	8000468 <__udivmoddi4+0x260>
 800049c:	ebb8 0e02 	subs.w	lr, r8, r2
 80004a0:	eb69 0104 	sbc.w	r1, r9, r4
 80004a4:	3801      	subs	r0, #1
 80004a6:	e7df      	b.n	8000468 <__udivmoddi4+0x260>
 80004a8:	4608      	mov	r0, r1
 80004aa:	e7d2      	b.n	8000452 <__udivmoddi4+0x24a>
 80004ac:	4660      	mov	r0, ip
 80004ae:	e78d      	b.n	80003cc <__udivmoddi4+0x1c4>
 80004b0:	4681      	mov	r9, r0
 80004b2:	e7b9      	b.n	8000428 <__udivmoddi4+0x220>
 80004b4:	4666      	mov	r6, ip
 80004b6:	e775      	b.n	80003a4 <__udivmoddi4+0x19c>
 80004b8:	4630      	mov	r0, r6
 80004ba:	e74a      	b.n	8000352 <__udivmoddi4+0x14a>
 80004bc:	f1ac 0c02 	sub.w	ip, ip, #2
 80004c0:	4439      	add	r1, r7
 80004c2:	e713      	b.n	80002ec <__udivmoddi4+0xe4>
 80004c4:	3802      	subs	r0, #2
 80004c6:	443c      	add	r4, r7
 80004c8:	e724      	b.n	8000314 <__udivmoddi4+0x10c>
 80004ca:	bf00      	nop

080004cc <__aeabi_idiv0>:
 80004cc:	4770      	bx	lr
 80004ce:	bf00      	nop

080004d0 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 80004d0:	b580      	push	{r7, lr}
 80004d2:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 80004d4:	f000 f8f6 	bl	80006c4 <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 80004d8:	f000 f802 	bl	80004e0 <SystemClock_Config>

  /* USER CODE END 2 */

  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
 80004dc:	e7fe      	b.n	80004dc <main+0xc>
	...

080004e0 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 80004e0:	b580      	push	{r7, lr}
 80004e2:	b094      	sub	sp, #80	; 0x50
 80004e4:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80004e6:	f107 0320 	add.w	r3, r7, #32
 80004ea:	2230      	movs	r2, #48	; 0x30
 80004ec:	2100      	movs	r1, #0
 80004ee:	4618      	mov	r0, r3
 80004f0:	f000 fe78 	bl	80011e4 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80004f4:	f107 030c 	add.w	r3, r7, #12
 80004f8:	2200      	movs	r2, #0
 80004fa:	601a      	str	r2, [r3, #0]
 80004fc:	605a      	str	r2, [r3, #4]
 80004fe:	609a      	str	r2, [r3, #8]
 8000500:	60da      	str	r2, [r3, #12]
 8000502:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  __HAL_RCC_PWR_CLK_ENABLE();
 8000504:	2300      	movs	r3, #0
 8000506:	60bb      	str	r3, [r7, #8]
 8000508:	4b22      	ldr	r3, [pc, #136]	; (8000594 <SystemClock_Config+0xb4>)
 800050a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800050c:	4a21      	ldr	r2, [pc, #132]	; (8000594 <SystemClock_Config+0xb4>)
 800050e:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000512:	6413      	str	r3, [r2, #64]	; 0x40
 8000514:	4b1f      	ldr	r3, [pc, #124]	; (8000594 <SystemClock_Config+0xb4>)
 8000516:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000518:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800051c:	60bb      	str	r3, [r7, #8]
 800051e:	68bb      	ldr	r3, [r7, #8]
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 8000520:	2300      	movs	r3, #0
 8000522:	607b      	str	r3, [r7, #4]
 8000524:	4b1c      	ldr	r3, [pc, #112]	; (8000598 <SystemClock_Config+0xb8>)
 8000526:	681b      	ldr	r3, [r3, #0]
 8000528:	4a1b      	ldr	r2, [pc, #108]	; (8000598 <SystemClock_Config+0xb8>)
 800052a:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
 800052e:	6013      	str	r3, [r2, #0]
 8000530:	4b19      	ldr	r3, [pc, #100]	; (8000598 <SystemClock_Config+0xb8>)
 8000532:	681b      	ldr	r3, [r3, #0]
 8000534:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
 8000538:	607b      	str	r3, [r7, #4]
 800053a:	687b      	ldr	r3, [r7, #4]
  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 800053c:	2302      	movs	r3, #2
 800053e:	623b      	str	r3, [r7, #32]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8000540:	2301      	movs	r3, #1
 8000542:	62fb      	str	r3, [r7, #44]	; 0x2c
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8000544:	2310      	movs	r3, #16
 8000546:	633b      	str	r3, [r7, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
 8000548:	2300      	movs	r3, #0
 800054a:	63bb      	str	r3, [r7, #56]	; 0x38
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800054c:	f107 0320 	add.w	r3, r7, #32
 8000550:	4618      	mov	r0, r3
 8000552:	f000 fa0f 	bl	8000974 <HAL_RCC_OscConfig>
 8000556:	4603      	mov	r3, r0
 8000558:	2b00      	cmp	r3, #0
 800055a:	d001      	beq.n	8000560 <SystemClock_Config+0x80>
  {
    Error_Handler();
 800055c:	f000 f81e 	bl	800059c <Error_Handler>
  }
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8000560:	230f      	movs	r3, #15
 8000562:	60fb      	str	r3, [r7, #12]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
 8000564:	2300      	movs	r3, #0
 8000566:	613b      	str	r3, [r7, #16]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8000568:	2300      	movs	r3, #0
 800056a:	617b      	str	r3, [r7, #20]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 800056c:	2300      	movs	r3, #0
 800056e:	61bb      	str	r3, [r7, #24]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8000570:	2300      	movs	r3, #0
 8000572:	61fb      	str	r3, [r7, #28]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 8000574:	f107 030c 	add.w	r3, r7, #12
 8000578:	2100      	movs	r1, #0
 800057a:	4618      	mov	r0, r3
 800057c:	f000 fc72 	bl	8000e64 <HAL_RCC_ClockConfig>
 8000580:	4603      	mov	r3, r0
 8000582:	2b00      	cmp	r3, #0
 8000584:	d001      	beq.n	800058a <SystemClock_Config+0xaa>
  {
    Error_Handler();
 8000586:	f000 f809 	bl	800059c <Error_Handler>
  }
}
 800058a:	bf00      	nop
 800058c:	3750      	adds	r7, #80	; 0x50
 800058e:	46bd      	mov	sp, r7
 8000590:	bd80      	pop	{r7, pc}
 8000592:	bf00      	nop
 8000594:	40023800 	.word	0x40023800
 8000598:	40007000 	.word	0x40007000

0800059c <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 800059c:	b480      	push	{r7}
 800059e:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 80005a0:	b672      	cpsid	i
}
 80005a2:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 80005a4:	e7fe      	b.n	80005a4 <Error_Handler+0x8>
	...

080005a8 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 80005a8:	b480      	push	{r7}
 80005aa:	b083      	sub	sp, #12
 80005ac:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 80005ae:	2300      	movs	r3, #0
 80005b0:	607b      	str	r3, [r7, #4]
 80005b2:	4b10      	ldr	r3, [pc, #64]	; (80005f4 <HAL_MspInit+0x4c>)
 80005b4:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80005b6:	4a0f      	ldr	r2, [pc, #60]	; (80005f4 <HAL_MspInit+0x4c>)
 80005b8:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 80005bc:	6453      	str	r3, [r2, #68]	; 0x44
 80005be:	4b0d      	ldr	r3, [pc, #52]	; (80005f4 <HAL_MspInit+0x4c>)
 80005c0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80005c2:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 80005c6:	607b      	str	r3, [r7, #4]
 80005c8:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 80005ca:	2300      	movs	r3, #0
 80005cc:	603b      	str	r3, [r7, #0]
 80005ce:	4b09      	ldr	r3, [pc, #36]	; (80005f4 <HAL_MspInit+0x4c>)
 80005d0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80005d2:	4a08      	ldr	r2, [pc, #32]	; (80005f4 <HAL_MspInit+0x4c>)
 80005d4:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80005d8:	6413      	str	r3, [r2, #64]	; 0x40
 80005da:	4b06      	ldr	r3, [pc, #24]	; (80005f4 <HAL_MspInit+0x4c>)
 80005dc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80005de:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80005e2:	603b      	str	r3, [r7, #0]
 80005e4:	683b      	ldr	r3, [r7, #0]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 80005e6:	bf00      	nop
 80005e8:	370c      	adds	r7, #12
 80005ea:	46bd      	mov	sp, r7
 80005ec:	f85d 7b04 	ldr.w	r7, [sp], #4
 80005f0:	4770      	bx	lr
 80005f2:	bf00      	nop
 80005f4:	40023800 	.word	0x40023800

080005f8 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80005f8:	b480      	push	{r7}
 80005fa:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 80005fc:	e7fe      	b.n	80005fc <NMI_Handler+0x4>

080005fe <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80005fe:	b480      	push	{r7}
 8000600:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8000602:	e7fe      	b.n	8000602 <HardFault_Handler+0x4>

08000604 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8000604:	b480      	push	{r7}
 8000606:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8000608:	e7fe      	b.n	8000608 <MemManage_Handler+0x4>

0800060a <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 800060a:	b480      	push	{r7}
 800060c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 800060e:	e7fe      	b.n	800060e <BusFault_Handler+0x4>

08000610 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8000610:	b480      	push	{r7}
 8000612:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8000614:	e7fe      	b.n	8000614 <UsageFault_Handler+0x4>

08000616 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8000616:	b480      	push	{r7}
 8000618:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 800061a:	bf00      	nop
 800061c:	46bd      	mov	sp, r7
 800061e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000622:	4770      	bx	lr

08000624 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8000624:	b480      	push	{r7}
 8000626:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8000628:	bf00      	nop
 800062a:	46bd      	mov	sp, r7
 800062c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000630:	4770      	bx	lr

08000632 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8000632:	b480      	push	{r7}
 8000634:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8000636:	bf00      	nop
 8000638:	46bd      	mov	sp, r7
 800063a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800063e:	4770      	bx	lr

08000640 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8000640:	b580      	push	{r7, lr}
 8000642:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8000644:	f000 f890 	bl	8000768 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8000648:	bf00      	nop
 800064a:	bd80      	pop	{r7, pc}

0800064c <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
 800064c:	b480      	push	{r7}
 800064e:	af00      	add	r7, sp, #0
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 8000650:	4b06      	ldr	r3, [pc, #24]	; (800066c <SystemInit+0x20>)
 8000652:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8000656:	4a05      	ldr	r2, [pc, #20]	; (800066c <SystemInit+0x20>)
 8000658:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 800065c:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88

  /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
 8000660:	bf00      	nop
 8000662:	46bd      	mov	sp, r7
 8000664:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000668:	4770      	bx	lr
 800066a:	bf00      	nop
 800066c:	e000ed00 	.word	0xe000ed00

08000670 <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:  
  ldr   sp, =_estack    		 /* set stack pointer */
 8000670:	f8df d034 	ldr.w	sp, [pc, #52]	; 80006a8 <LoopFillZerobss+0x12>

/* Copy the data segment initializers from flash to SRAM */  
  ldr r0, =_sdata
 8000674:	480d      	ldr	r0, [pc, #52]	; (80006ac <LoopFillZerobss+0x16>)
  ldr r1, =_edata
 8000676:	490e      	ldr	r1, [pc, #56]	; (80006b0 <LoopFillZerobss+0x1a>)
  ldr r2, =_sidata
 8000678:	4a0e      	ldr	r2, [pc, #56]	; (80006b4 <LoopFillZerobss+0x1e>)
  movs r3, #0
 800067a:	2300      	movs	r3, #0
  b LoopCopyDataInit
 800067c:	e002      	b.n	8000684 <LoopCopyDataInit>

0800067e <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 800067e:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8000680:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8000682:	3304      	adds	r3, #4

08000684 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8000684:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8000686:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8000688:	d3f9      	bcc.n	800067e <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 800068a:	4a0b      	ldr	r2, [pc, #44]	; (80006b8 <LoopFillZerobss+0x22>)
  ldr r4, =_ebss
 800068c:	4c0b      	ldr	r4, [pc, #44]	; (80006bc <LoopFillZerobss+0x26>)
  movs r3, #0
 800068e:	2300      	movs	r3, #0
  b LoopFillZerobss
 8000690:	e001      	b.n	8000696 <LoopFillZerobss>

08000692 <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8000692:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8000694:	3204      	adds	r2, #4

08000696 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8000696:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8000698:	d3fb      	bcc.n	8000692 <FillZerobss>

/* Call the clock system intitialization function.*/
  bl  SystemInit   
 800069a:	f7ff ffd7 	bl	800064c <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 800069e:	f000 fd7d 	bl	800119c <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 80006a2:	f7ff ff15 	bl	80004d0 <main>
  bx  lr    
 80006a6:	4770      	bx	lr
  ldr   sp, =_estack    		 /* set stack pointer */
 80006a8:	20020000 	.word	0x20020000
  ldr r0, =_sdata
 80006ac:	20000000 	.word	0x20000000
  ldr r1, =_edata
 80006b0:	2000000c 	.word	0x2000000c
  ldr r2, =_sidata
 80006b4:	0800122c 	.word	0x0800122c
  ldr r2, =_sbss
 80006b8:	2000000c 	.word	0x2000000c
  ldr r4, =_ebss
 80006bc:	2000002c 	.word	0x2000002c

080006c0 <ADC_IRQHandler>:
 * @retval None       
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 80006c0:	e7fe      	b.n	80006c0 <ADC_IRQHandler>
	...

080006c4 <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 80006c4:	b580      	push	{r7, lr}
 80006c6:	af00      	add	r7, sp, #0
  /* Configure Flash prefetch, Instruction cache, Data cache */ 
#if (INSTRUCTION_CACHE_ENABLE != 0U)
  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 80006c8:	4b0e      	ldr	r3, [pc, #56]	; (8000704 <HAL_Init+0x40>)
 80006ca:	681b      	ldr	r3, [r3, #0]
 80006cc:	4a0d      	ldr	r2, [pc, #52]	; (8000704 <HAL_Init+0x40>)
 80006ce:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 80006d2:	6013      	str	r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */

#if (DATA_CACHE_ENABLE != 0U)
  __HAL_FLASH_DATA_CACHE_ENABLE();
 80006d4:	4b0b      	ldr	r3, [pc, #44]	; (8000704 <HAL_Init+0x40>)
 80006d6:	681b      	ldr	r3, [r3, #0]
 80006d8:	4a0a      	ldr	r2, [pc, #40]	; (8000704 <HAL_Init+0x40>)
 80006da:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
 80006de:	6013      	str	r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0U)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 80006e0:	4b08      	ldr	r3, [pc, #32]	; (8000704 <HAL_Init+0x40>)
 80006e2:	681b      	ldr	r3, [r3, #0]
 80006e4:	4a07      	ldr	r2, [pc, #28]	; (8000704 <HAL_Init+0x40>)
 80006e6:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80006ea:	6013      	str	r3, [r2, #0]
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 80006ec:	2003      	movs	r0, #3
 80006ee:	f000 f90d 	bl	800090c <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);
 80006f2:	200f      	movs	r0, #15
 80006f4:	f000 f808 	bl	8000708 <HAL_InitTick>

  /* Init the low level hardware */
  HAL_MspInit();
 80006f8:	f7ff ff56 	bl	80005a8 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 80006fc:	2300      	movs	r3, #0
}
 80006fe:	4618      	mov	r0, r3
 8000700:	bd80      	pop	{r7, pc}
 8000702:	bf00      	nop
 8000704:	40023c00 	.word	0x40023c00

08000708 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000708:	b580      	push	{r7, lr}
 800070a:	b082      	sub	sp, #8
 800070c:	af00      	add	r7, sp, #0
 800070e:	6078      	str	r0, [r7, #4]
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8000710:	4b12      	ldr	r3, [pc, #72]	; (800075c <HAL_InitTick+0x54>)
 8000712:	681a      	ldr	r2, [r3, #0]
 8000714:	4b12      	ldr	r3, [pc, #72]	; (8000760 <HAL_InitTick+0x58>)
 8000716:	781b      	ldrb	r3, [r3, #0]
 8000718:	4619      	mov	r1, r3
 800071a:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 800071e:	fbb3 f3f1 	udiv	r3, r3, r1
 8000722:	fbb2 f3f3 	udiv	r3, r2, r3
 8000726:	4618      	mov	r0, r3
 8000728:	f000 f917 	bl	800095a <HAL_SYSTICK_Config>
 800072c:	4603      	mov	r3, r0
 800072e:	2b00      	cmp	r3, #0
 8000730:	d001      	beq.n	8000736 <HAL_InitTick+0x2e>
  {
    return HAL_ERROR;
 8000732:	2301      	movs	r3, #1
 8000734:	e00e      	b.n	8000754 <HAL_InitTick+0x4c>
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000736:	687b      	ldr	r3, [r7, #4]
 8000738:	2b0f      	cmp	r3, #15
 800073a:	d80a      	bhi.n	8000752 <HAL_InitTick+0x4a>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 800073c:	2200      	movs	r2, #0
 800073e:	6879      	ldr	r1, [r7, #4]
 8000740:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8000744:	f000 f8ed 	bl	8000922 <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8000748:	4a06      	ldr	r2, [pc, #24]	; (8000764 <HAL_InitTick+0x5c>)
 800074a:	687b      	ldr	r3, [r7, #4]
 800074c:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
 800074e:	2300      	movs	r3, #0
 8000750:	e000      	b.n	8000754 <HAL_InitTick+0x4c>
    return HAL_ERROR;
 8000752:	2301      	movs	r3, #1
}
 8000754:	4618      	mov	r0, r3
 8000756:	3708      	adds	r7, #8
 8000758:	46bd      	mov	sp, r7
 800075a:	bd80      	pop	{r7, pc}
 800075c:	20000000 	.word	0x20000000
 8000760:	20000008 	.word	0x20000008
 8000764:	20000004 	.word	0x20000004

08000768 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other 
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8000768:	b480      	push	{r7}
 800076a:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 800076c:	4b06      	ldr	r3, [pc, #24]	; (8000788 <HAL_IncTick+0x20>)
 800076e:	781b      	ldrb	r3, [r3, #0]
 8000770:	461a      	mov	r2, r3
 8000772:	4b06      	ldr	r3, [pc, #24]	; (800078c <HAL_IncTick+0x24>)
 8000774:	681b      	ldr	r3, [r3, #0]
 8000776:	4413      	add	r3, r2
 8000778:	4a04      	ldr	r2, [pc, #16]	; (800078c <HAL_IncTick+0x24>)
 800077a:	6013      	str	r3, [r2, #0]
}
 800077c:	bf00      	nop
 800077e:	46bd      	mov	sp, r7
 8000780:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000784:	4770      	bx	lr
 8000786:	bf00      	nop
 8000788:	20000008 	.word	0x20000008
 800078c:	20000028 	.word	0x20000028

08000790 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other 
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8000790:	b480      	push	{r7}
 8000792:	af00      	add	r7, sp, #0
  return uwTick;
 8000794:	4b03      	ldr	r3, [pc, #12]	; (80007a4 <HAL_GetTick+0x14>)
 8000796:	681b      	ldr	r3, [r3, #0]
}
 8000798:	4618      	mov	r0, r3
 800079a:	46bd      	mov	sp, r7
 800079c:	f85d 7b04 	ldr.w	r7, [sp], #4
 80007a0:	4770      	bx	lr
 80007a2:	bf00      	nop
 80007a4:	20000028 	.word	0x20000028

080007a8 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80007a8:	b480      	push	{r7}
 80007aa:	b085      	sub	sp, #20
 80007ac:	af00      	add	r7, sp, #0
 80007ae:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 80007b0:	687b      	ldr	r3, [r7, #4]
 80007b2:	f003 0307 	and.w	r3, r3, #7
 80007b6:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80007b8:	4b0c      	ldr	r3, [pc, #48]	; (80007ec <__NVIC_SetPriorityGrouping+0x44>)
 80007ba:	68db      	ldr	r3, [r3, #12]
 80007bc:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 80007be:	68ba      	ldr	r2, [r7, #8]
 80007c0:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 80007c4:	4013      	ands	r3, r2
 80007c6:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 80007c8:	68fb      	ldr	r3, [r7, #12]
 80007ca:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 80007cc:	68bb      	ldr	r3, [r7, #8]
 80007ce:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 80007d0:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 80007d4:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 80007d8:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 80007da:	4a04      	ldr	r2, [pc, #16]	; (80007ec <__NVIC_SetPriorityGrouping+0x44>)
 80007dc:	68bb      	ldr	r3, [r7, #8]
 80007de:	60d3      	str	r3, [r2, #12]
}
 80007e0:	bf00      	nop
 80007e2:	3714      	adds	r7, #20
 80007e4:	46bd      	mov	sp, r7
 80007e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80007ea:	4770      	bx	lr
 80007ec:	e000ed00 	.word	0xe000ed00

080007f0 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 80007f0:	b480      	push	{r7}
 80007f2:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80007f4:	4b04      	ldr	r3, [pc, #16]	; (8000808 <__NVIC_GetPriorityGrouping+0x18>)
 80007f6:	68db      	ldr	r3, [r3, #12]
 80007f8:	0a1b      	lsrs	r3, r3, #8
 80007fa:	f003 0307 	and.w	r3, r3, #7
}
 80007fe:	4618      	mov	r0, r3
 8000800:	46bd      	mov	sp, r7
 8000802:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000806:	4770      	bx	lr
 8000808:	e000ed00 	.word	0xe000ed00

0800080c <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 800080c:	b480      	push	{r7}
 800080e:	b083      	sub	sp, #12
 8000810:	af00      	add	r7, sp, #0
 8000812:	4603      	mov	r3, r0
 8000814:	6039      	str	r1, [r7, #0]
 8000816:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8000818:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800081c:	2b00      	cmp	r3, #0
 800081e:	db0a      	blt.n	8000836 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000820:	683b      	ldr	r3, [r7, #0]
 8000822:	b2da      	uxtb	r2, r3
 8000824:	490c      	ldr	r1, [pc, #48]	; (8000858 <__NVIC_SetPriority+0x4c>)
 8000826:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800082a:	0112      	lsls	r2, r2, #4
 800082c:	b2d2      	uxtb	r2, r2
 800082e:	440b      	add	r3, r1
 8000830:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8000834:	e00a      	b.n	800084c <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000836:	683b      	ldr	r3, [r7, #0]
 8000838:	b2da      	uxtb	r2, r3
 800083a:	4908      	ldr	r1, [pc, #32]	; (800085c <__NVIC_SetPriority+0x50>)
 800083c:	79fb      	ldrb	r3, [r7, #7]
 800083e:	f003 030f 	and.w	r3, r3, #15
 8000842:	3b04      	subs	r3, #4
 8000844:	0112      	lsls	r2, r2, #4
 8000846:	b2d2      	uxtb	r2, r2
 8000848:	440b      	add	r3, r1
 800084a:	761a      	strb	r2, [r3, #24]
}
 800084c:	bf00      	nop
 800084e:	370c      	adds	r7, #12
 8000850:	46bd      	mov	sp, r7
 8000852:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000856:	4770      	bx	lr
 8000858:	e000e100 	.word	0xe000e100
 800085c:	e000ed00 	.word	0xe000ed00

08000860 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000860:	b480      	push	{r7}
 8000862:	b089      	sub	sp, #36	; 0x24
 8000864:	af00      	add	r7, sp, #0
 8000866:	60f8      	str	r0, [r7, #12]
 8000868:	60b9      	str	r1, [r7, #8]
 800086a:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 800086c:	68fb      	ldr	r3, [r7, #12]
 800086e:	f003 0307 	and.w	r3, r3, #7
 8000872:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000874:	69fb      	ldr	r3, [r7, #28]
 8000876:	f1c3 0307 	rsb	r3, r3, #7
 800087a:	2b04      	cmp	r3, #4
 800087c:	bf28      	it	cs
 800087e:	2304      	movcs	r3, #4
 8000880:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000882:	69fb      	ldr	r3, [r7, #28]
 8000884:	3304      	adds	r3, #4
 8000886:	2b06      	cmp	r3, #6
 8000888:	d902      	bls.n	8000890 <NVIC_EncodePriority+0x30>
 800088a:	69fb      	ldr	r3, [r7, #28]
 800088c:	3b03      	subs	r3, #3
 800088e:	e000      	b.n	8000892 <NVIC_EncodePriority+0x32>
 8000890:	2300      	movs	r3, #0
 8000892:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000894:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8000898:	69bb      	ldr	r3, [r7, #24]
 800089a:	fa02 f303 	lsl.w	r3, r2, r3
 800089e:	43da      	mvns	r2, r3
 80008a0:	68bb      	ldr	r3, [r7, #8]
 80008a2:	401a      	ands	r2, r3
 80008a4:	697b      	ldr	r3, [r7, #20]
 80008a6:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 80008a8:	f04f 31ff 	mov.w	r1, #4294967295	; 0xffffffff
 80008ac:	697b      	ldr	r3, [r7, #20]
 80008ae:	fa01 f303 	lsl.w	r3, r1, r3
 80008b2:	43d9      	mvns	r1, r3
 80008b4:	687b      	ldr	r3, [r7, #4]
 80008b6:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80008b8:	4313      	orrs	r3, r2
         );
}
 80008ba:	4618      	mov	r0, r3
 80008bc:	3724      	adds	r7, #36	; 0x24
 80008be:	46bd      	mov	sp, r7
 80008c0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80008c4:	4770      	bx	lr
	...

080008c8 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 80008c8:	b580      	push	{r7, lr}
 80008ca:	b082      	sub	sp, #8
 80008cc:	af00      	add	r7, sp, #0
 80008ce:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 80008d0:	687b      	ldr	r3, [r7, #4]
 80008d2:	3b01      	subs	r3, #1
 80008d4:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 80008d8:	d301      	bcc.n	80008de <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 80008da:	2301      	movs	r3, #1
 80008dc:	e00f      	b.n	80008fe <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 80008de:	4a0a      	ldr	r2, [pc, #40]	; (8000908 <SysTick_Config+0x40>)
 80008e0:	687b      	ldr	r3, [r7, #4]
 80008e2:	3b01      	subs	r3, #1
 80008e4:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 80008e6:	210f      	movs	r1, #15
 80008e8:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 80008ec:	f7ff ff8e 	bl	800080c <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80008f0:	4b05      	ldr	r3, [pc, #20]	; (8000908 <SysTick_Config+0x40>)
 80008f2:	2200      	movs	r2, #0
 80008f4:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80008f6:	4b04      	ldr	r3, [pc, #16]	; (8000908 <SysTick_Config+0x40>)
 80008f8:	2207      	movs	r2, #7
 80008fa:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 80008fc:	2300      	movs	r3, #0
}
 80008fe:	4618      	mov	r0, r3
 8000900:	3708      	adds	r7, #8
 8000902:	46bd      	mov	sp, r7
 8000904:	bd80      	pop	{r7, pc}
 8000906:	bf00      	nop
 8000908:	e000e010 	.word	0xe000e010

0800090c <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 800090c:	b580      	push	{r7, lr}
 800090e:	b082      	sub	sp, #8
 8000910:	af00      	add	r7, sp, #0
 8000912:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 8000914:	6878      	ldr	r0, [r7, #4]
 8000916:	f7ff ff47 	bl	80007a8 <__NVIC_SetPriorityGrouping>
}
 800091a:	bf00      	nop
 800091c:	3708      	adds	r7, #8
 800091e:	46bd      	mov	sp, r7
 8000920:	bd80      	pop	{r7, pc}

08000922 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 8000922:	b580      	push	{r7, lr}
 8000924:	b086      	sub	sp, #24
 8000926:	af00      	add	r7, sp, #0
 8000928:	4603      	mov	r3, r0
 800092a:	60b9      	str	r1, [r7, #8]
 800092c:	607a      	str	r2, [r7, #4]
 800092e:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00U;
 8000930:	2300      	movs	r3, #0
 8000932:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 8000934:	f7ff ff5c 	bl	80007f0 <__NVIC_GetPriorityGrouping>
 8000938:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 800093a:	687a      	ldr	r2, [r7, #4]
 800093c:	68b9      	ldr	r1, [r7, #8]
 800093e:	6978      	ldr	r0, [r7, #20]
 8000940:	f7ff ff8e 	bl	8000860 <NVIC_EncodePriority>
 8000944:	4602      	mov	r2, r0
 8000946:	f997 300f 	ldrsb.w	r3, [r7, #15]
 800094a:	4611      	mov	r1, r2
 800094c:	4618      	mov	r0, r3
 800094e:	f7ff ff5d 	bl	800080c <__NVIC_SetPriority>
}
 8000952:	bf00      	nop
 8000954:	3718      	adds	r7, #24
 8000956:	46bd      	mov	sp, r7
 8000958:	bd80      	pop	{r7, pc}

0800095a <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 800095a:	b580      	push	{r7, lr}
 800095c:	b082      	sub	sp, #8
 800095e:	af00      	add	r7, sp, #0
 8000960:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 8000962:	6878      	ldr	r0, [r7, #4]
 8000964:	f7ff ffb0 	bl	80008c8 <SysTick_Config>
 8000968:	4603      	mov	r3, r0
}
 800096a:	4618      	mov	r0, r3
 800096c:	3708      	adds	r7, #8
 800096e:	46bd      	mov	sp, r7
 8000970:	bd80      	pop	{r7, pc}
	...

08000974 <HAL_RCC_OscConfig>:
  *         supported by this API. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8000974:	b580      	push	{r7, lr}
 8000976:	b086      	sub	sp, #24
 8000978:	af00      	add	r7, sp, #0
 800097a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 800097c:	687b      	ldr	r3, [r7, #4]
 800097e:	2b00      	cmp	r3, #0
 8000980:	d101      	bne.n	8000986 <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 8000982:	2301      	movs	r3, #1
 8000984:	e264      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000986:	687b      	ldr	r3, [r7, #4]
 8000988:	681b      	ldr	r3, [r3, #0]
 800098a:	f003 0301 	and.w	r3, r3, #1
 800098e:	2b00      	cmp	r3, #0
 8000990:	d075      	beq.n	8000a7e <HAL_RCC_OscConfig+0x10a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 8000992:	4ba3      	ldr	r3, [pc, #652]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000994:	689b      	ldr	r3, [r3, #8]
 8000996:	f003 030c 	and.w	r3, r3, #12
 800099a:	2b04      	cmp	r3, #4
 800099c:	d00c      	beq.n	80009b8 <HAL_RCC_OscConfig+0x44>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 800099e:	4ba0      	ldr	r3, [pc, #640]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 80009a0:	689b      	ldr	r3, [r3, #8]
 80009a2:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 80009a6:	2b08      	cmp	r3, #8
 80009a8:	d112      	bne.n	80009d0 <HAL_RCC_OscConfig+0x5c>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 80009aa:	4b9d      	ldr	r3, [pc, #628]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 80009ac:	685b      	ldr	r3, [r3, #4]
 80009ae:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 80009b2:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
 80009b6:	d10b      	bne.n	80009d0 <HAL_RCC_OscConfig+0x5c>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80009b8:	4b99      	ldr	r3, [pc, #612]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 80009ba:	681b      	ldr	r3, [r3, #0]
 80009bc:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80009c0:	2b00      	cmp	r3, #0
 80009c2:	d05b      	beq.n	8000a7c <HAL_RCC_OscConfig+0x108>
 80009c4:	687b      	ldr	r3, [r7, #4]
 80009c6:	685b      	ldr	r3, [r3, #4]
 80009c8:	2b00      	cmp	r3, #0
 80009ca:	d157      	bne.n	8000a7c <HAL_RCC_OscConfig+0x108>
      {
        return HAL_ERROR;
 80009cc:	2301      	movs	r3, #1
 80009ce:	e23f      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 80009d0:	687b      	ldr	r3, [r7, #4]
 80009d2:	685b      	ldr	r3, [r3, #4]
 80009d4:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 80009d8:	d106      	bne.n	80009e8 <HAL_RCC_OscConfig+0x74>
 80009da:	4b91      	ldr	r3, [pc, #580]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 80009dc:	681b      	ldr	r3, [r3, #0]
 80009de:	4a90      	ldr	r2, [pc, #576]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 80009e0:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 80009e4:	6013      	str	r3, [r2, #0]
 80009e6:	e01d      	b.n	8000a24 <HAL_RCC_OscConfig+0xb0>
 80009e8:	687b      	ldr	r3, [r7, #4]
 80009ea:	685b      	ldr	r3, [r3, #4]
 80009ec:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 80009f0:	d10c      	bne.n	8000a0c <HAL_RCC_OscConfig+0x98>
 80009f2:	4b8b      	ldr	r3, [pc, #556]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 80009f4:	681b      	ldr	r3, [r3, #0]
 80009f6:	4a8a      	ldr	r2, [pc, #552]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 80009f8:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 80009fc:	6013      	str	r3, [r2, #0]
 80009fe:	4b88      	ldr	r3, [pc, #544]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a00:	681b      	ldr	r3, [r3, #0]
 8000a02:	4a87      	ldr	r2, [pc, #540]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a04:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8000a08:	6013      	str	r3, [r2, #0]
 8000a0a:	e00b      	b.n	8000a24 <HAL_RCC_OscConfig+0xb0>
 8000a0c:	4b84      	ldr	r3, [pc, #528]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a0e:	681b      	ldr	r3, [r3, #0]
 8000a10:	4a83      	ldr	r2, [pc, #524]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a12:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8000a16:	6013      	str	r3, [r2, #0]
 8000a18:	4b81      	ldr	r3, [pc, #516]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a1a:	681b      	ldr	r3, [r3, #0]
 8000a1c:	4a80      	ldr	r2, [pc, #512]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a1e:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8000a22:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
 8000a24:	687b      	ldr	r3, [r7, #4]
 8000a26:	685b      	ldr	r3, [r3, #4]
 8000a28:	2b00      	cmp	r3, #0
 8000a2a:	d013      	beq.n	8000a54 <HAL_RCC_OscConfig+0xe0>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000a2c:	f7ff feb0 	bl	8000790 <HAL_GetTick>
 8000a30:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000a32:	e008      	b.n	8000a46 <HAL_RCC_OscConfig+0xd2>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000a34:	f7ff feac 	bl	8000790 <HAL_GetTick>
 8000a38:	4602      	mov	r2, r0
 8000a3a:	693b      	ldr	r3, [r7, #16]
 8000a3c:	1ad3      	subs	r3, r2, r3
 8000a3e:	2b64      	cmp	r3, #100	; 0x64
 8000a40:	d901      	bls.n	8000a46 <HAL_RCC_OscConfig+0xd2>
          {
            return HAL_TIMEOUT;
 8000a42:	2303      	movs	r3, #3
 8000a44:	e204      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000a46:	4b76      	ldr	r3, [pc, #472]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a48:	681b      	ldr	r3, [r3, #0]
 8000a4a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000a4e:	2b00      	cmp	r3, #0
 8000a50:	d0f0      	beq.n	8000a34 <HAL_RCC_OscConfig+0xc0>
 8000a52:	e014      	b.n	8000a7e <HAL_RCC_OscConfig+0x10a>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000a54:	f7ff fe9c 	bl	8000790 <HAL_GetTick>
 8000a58:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is bypassed or disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8000a5a:	e008      	b.n	8000a6e <HAL_RCC_OscConfig+0xfa>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000a5c:	f7ff fe98 	bl	8000790 <HAL_GetTick>
 8000a60:	4602      	mov	r2, r0
 8000a62:	693b      	ldr	r3, [r7, #16]
 8000a64:	1ad3      	subs	r3, r2, r3
 8000a66:	2b64      	cmp	r3, #100	; 0x64
 8000a68:	d901      	bls.n	8000a6e <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 8000a6a:	2303      	movs	r3, #3
 8000a6c:	e1f0      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8000a6e:	4b6c      	ldr	r3, [pc, #432]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a70:	681b      	ldr	r3, [r3, #0]
 8000a72:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000a76:	2b00      	cmp	r3, #0
 8000a78:	d1f0      	bne.n	8000a5c <HAL_RCC_OscConfig+0xe8>
 8000a7a:	e000      	b.n	8000a7e <HAL_RCC_OscConfig+0x10a>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000a7c:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000a7e:	687b      	ldr	r3, [r7, #4]
 8000a80:	681b      	ldr	r3, [r3, #0]
 8000a82:	f003 0302 	and.w	r3, r3, #2
 8000a86:	2b00      	cmp	r3, #0
 8000a88:	d063      	beq.n	8000b52 <HAL_RCC_OscConfig+0x1de>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 8000a8a:	4b65      	ldr	r3, [pc, #404]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a8c:	689b      	ldr	r3, [r3, #8]
 8000a8e:	f003 030c 	and.w	r3, r3, #12
 8000a92:	2b00      	cmp	r3, #0
 8000a94:	d00b      	beq.n	8000aae <HAL_RCC_OscConfig+0x13a>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 8000a96:	4b62      	ldr	r3, [pc, #392]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000a98:	689b      	ldr	r3, [r3, #8]
 8000a9a:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 8000a9e:	2b08      	cmp	r3, #8
 8000aa0:	d11c      	bne.n	8000adc <HAL_RCC_OscConfig+0x168>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 8000aa2:	4b5f      	ldr	r3, [pc, #380]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000aa4:	685b      	ldr	r3, [r3, #4]
 8000aa6:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8000aaa:	2b00      	cmp	r3, #0
 8000aac:	d116      	bne.n	8000adc <HAL_RCC_OscConfig+0x168>
    {
      /* When HSI is used as system clock it will not disabled */
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8000aae:	4b5c      	ldr	r3, [pc, #368]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000ab0:	681b      	ldr	r3, [r3, #0]
 8000ab2:	f003 0302 	and.w	r3, r3, #2
 8000ab6:	2b00      	cmp	r3, #0
 8000ab8:	d005      	beq.n	8000ac6 <HAL_RCC_OscConfig+0x152>
 8000aba:	687b      	ldr	r3, [r7, #4]
 8000abc:	68db      	ldr	r3, [r3, #12]
 8000abe:	2b01      	cmp	r3, #1
 8000ac0:	d001      	beq.n	8000ac6 <HAL_RCC_OscConfig+0x152>
      {
        return HAL_ERROR;
 8000ac2:	2301      	movs	r3, #1
 8000ac4:	e1c4      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000ac6:	4b56      	ldr	r3, [pc, #344]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000ac8:	681b      	ldr	r3, [r3, #0]
 8000aca:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8000ace:	687b      	ldr	r3, [r7, #4]
 8000ad0:	691b      	ldr	r3, [r3, #16]
 8000ad2:	00db      	lsls	r3, r3, #3
 8000ad4:	4952      	ldr	r1, [pc, #328]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000ad6:	4313      	orrs	r3, r2
 8000ad8:	600b      	str	r3, [r1, #0]
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8000ada:	e03a      	b.n	8000b52 <HAL_RCC_OscConfig+0x1de>
      }
    }
    else
    {
      /* Check the HSI State */
      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
 8000adc:	687b      	ldr	r3, [r7, #4]
 8000ade:	68db      	ldr	r3, [r3, #12]
 8000ae0:	2b00      	cmp	r3, #0
 8000ae2:	d020      	beq.n	8000b26 <HAL_RCC_OscConfig+0x1b2>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 8000ae4:	4b4f      	ldr	r3, [pc, #316]	; (8000c24 <HAL_RCC_OscConfig+0x2b0>)
 8000ae6:	2201      	movs	r2, #1
 8000ae8:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8000aea:	f7ff fe51 	bl	8000790 <HAL_GetTick>
 8000aee:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000af0:	e008      	b.n	8000b04 <HAL_RCC_OscConfig+0x190>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000af2:	f7ff fe4d 	bl	8000790 <HAL_GetTick>
 8000af6:	4602      	mov	r2, r0
 8000af8:	693b      	ldr	r3, [r7, #16]
 8000afa:	1ad3      	subs	r3, r2, r3
 8000afc:	2b02      	cmp	r3, #2
 8000afe:	d901      	bls.n	8000b04 <HAL_RCC_OscConfig+0x190>
          {
            return HAL_TIMEOUT;
 8000b00:	2303      	movs	r3, #3
 8000b02:	e1a5      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000b04:	4b46      	ldr	r3, [pc, #280]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000b06:	681b      	ldr	r3, [r3, #0]
 8000b08:	f003 0302 	and.w	r3, r3, #2
 8000b0c:	2b00      	cmp	r3, #0
 8000b0e:	d0f0      	beq.n	8000af2 <HAL_RCC_OscConfig+0x17e>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000b10:	4b43      	ldr	r3, [pc, #268]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000b12:	681b      	ldr	r3, [r3, #0]
 8000b14:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8000b18:	687b      	ldr	r3, [r7, #4]
 8000b1a:	691b      	ldr	r3, [r3, #16]
 8000b1c:	00db      	lsls	r3, r3, #3
 8000b1e:	4940      	ldr	r1, [pc, #256]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000b20:	4313      	orrs	r3, r2
 8000b22:	600b      	str	r3, [r1, #0]
 8000b24:	e015      	b.n	8000b52 <HAL_RCC_OscConfig+0x1de>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 8000b26:	4b3f      	ldr	r3, [pc, #252]	; (8000c24 <HAL_RCC_OscConfig+0x2b0>)
 8000b28:	2200      	movs	r2, #0
 8000b2a:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8000b2c:	f7ff fe30 	bl	8000790 <HAL_GetTick>
 8000b30:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8000b32:	e008      	b.n	8000b46 <HAL_RCC_OscConfig+0x1d2>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000b34:	f7ff fe2c 	bl	8000790 <HAL_GetTick>
 8000b38:	4602      	mov	r2, r0
 8000b3a:	693b      	ldr	r3, [r7, #16]
 8000b3c:	1ad3      	subs	r3, r2, r3
 8000b3e:	2b02      	cmp	r3, #2
 8000b40:	d901      	bls.n	8000b46 <HAL_RCC_OscConfig+0x1d2>
          {
            return HAL_TIMEOUT;
 8000b42:	2303      	movs	r3, #3
 8000b44:	e184      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8000b46:	4b36      	ldr	r3, [pc, #216]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000b48:	681b      	ldr	r3, [r3, #0]
 8000b4a:	f003 0302 	and.w	r3, r3, #2
 8000b4e:	2b00      	cmp	r3, #0
 8000b50:	d1f0      	bne.n	8000b34 <HAL_RCC_OscConfig+0x1c0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8000b52:	687b      	ldr	r3, [r7, #4]
 8000b54:	681b      	ldr	r3, [r3, #0]
 8000b56:	f003 0308 	and.w	r3, r3, #8
 8000b5a:	2b00      	cmp	r3, #0
 8000b5c:	d030      	beq.n	8000bc0 <HAL_RCC_OscConfig+0x24c>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
 8000b5e:	687b      	ldr	r3, [r7, #4]
 8000b60:	695b      	ldr	r3, [r3, #20]
 8000b62:	2b00      	cmp	r3, #0
 8000b64:	d016      	beq.n	8000b94 <HAL_RCC_OscConfig+0x220>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8000b66:	4b30      	ldr	r3, [pc, #192]	; (8000c28 <HAL_RCC_OscConfig+0x2b4>)
 8000b68:	2201      	movs	r2, #1
 8000b6a:	601a      	str	r2, [r3, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8000b6c:	f7ff fe10 	bl	8000790 <HAL_GetTick>
 8000b70:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8000b72:	e008      	b.n	8000b86 <HAL_RCC_OscConfig+0x212>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000b74:	f7ff fe0c 	bl	8000790 <HAL_GetTick>
 8000b78:	4602      	mov	r2, r0
 8000b7a:	693b      	ldr	r3, [r7, #16]
 8000b7c:	1ad3      	subs	r3, r2, r3
 8000b7e:	2b02      	cmp	r3, #2
 8000b80:	d901      	bls.n	8000b86 <HAL_RCC_OscConfig+0x212>
        {
          return HAL_TIMEOUT;
 8000b82:	2303      	movs	r3, #3
 8000b84:	e164      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8000b86:	4b26      	ldr	r3, [pc, #152]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000b88:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 8000b8a:	f003 0302 	and.w	r3, r3, #2
 8000b8e:	2b00      	cmp	r3, #0
 8000b90:	d0f0      	beq.n	8000b74 <HAL_RCC_OscConfig+0x200>
 8000b92:	e015      	b.n	8000bc0 <HAL_RCC_OscConfig+0x24c>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8000b94:	4b24      	ldr	r3, [pc, #144]	; (8000c28 <HAL_RCC_OscConfig+0x2b4>)
 8000b96:	2200      	movs	r2, #0
 8000b98:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000b9a:	f7ff fdf9 	bl	8000790 <HAL_GetTick>
 8000b9e:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8000ba0:	e008      	b.n	8000bb4 <HAL_RCC_OscConfig+0x240>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000ba2:	f7ff fdf5 	bl	8000790 <HAL_GetTick>
 8000ba6:	4602      	mov	r2, r0
 8000ba8:	693b      	ldr	r3, [r7, #16]
 8000baa:	1ad3      	subs	r3, r2, r3
 8000bac:	2b02      	cmp	r3, #2
 8000bae:	d901      	bls.n	8000bb4 <HAL_RCC_OscConfig+0x240>
        {
          return HAL_TIMEOUT;
 8000bb0:	2303      	movs	r3, #3
 8000bb2:	e14d      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8000bb4:	4b1a      	ldr	r3, [pc, #104]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000bb6:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 8000bb8:	f003 0302 	and.w	r3, r3, #2
 8000bbc:	2b00      	cmp	r3, #0
 8000bbe:	d1f0      	bne.n	8000ba2 <HAL_RCC_OscConfig+0x22e>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8000bc0:	687b      	ldr	r3, [r7, #4]
 8000bc2:	681b      	ldr	r3, [r3, #0]
 8000bc4:	f003 0304 	and.w	r3, r3, #4
 8000bc8:	2b00      	cmp	r3, #0
 8000bca:	f000 80a0 	beq.w	8000d0e <HAL_RCC_OscConfig+0x39a>
  {
    FlagStatus       pwrclkchanged = RESET;
 8000bce:	2300      	movs	r3, #0
 8000bd0:	75fb      	strb	r3, [r7, #23]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000bd2:	4b13      	ldr	r3, [pc, #76]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000bd4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000bd6:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000bda:	2b00      	cmp	r3, #0
 8000bdc:	d10f      	bne.n	8000bfe <HAL_RCC_OscConfig+0x28a>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8000bde:	2300      	movs	r3, #0
 8000be0:	60bb      	str	r3, [r7, #8]
 8000be2:	4b0f      	ldr	r3, [pc, #60]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000be4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000be6:	4a0e      	ldr	r2, [pc, #56]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000be8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000bec:	6413      	str	r3, [r2, #64]	; 0x40
 8000bee:	4b0c      	ldr	r3, [pc, #48]	; (8000c20 <HAL_RCC_OscConfig+0x2ac>)
 8000bf0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000bf2:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000bf6:	60bb      	str	r3, [r7, #8]
 8000bf8:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8000bfa:	2301      	movs	r3, #1
 8000bfc:	75fb      	strb	r3, [r7, #23]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000bfe:	4b0b      	ldr	r3, [pc, #44]	; (8000c2c <HAL_RCC_OscConfig+0x2b8>)
 8000c00:	681b      	ldr	r3, [r3, #0]
 8000c02:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8000c06:	2b00      	cmp	r3, #0
 8000c08:	d121      	bne.n	8000c4e <HAL_RCC_OscConfig+0x2da>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8000c0a:	4b08      	ldr	r3, [pc, #32]	; (8000c2c <HAL_RCC_OscConfig+0x2b8>)
 8000c0c:	681b      	ldr	r3, [r3, #0]
 8000c0e:	4a07      	ldr	r2, [pc, #28]	; (8000c2c <HAL_RCC_OscConfig+0x2b8>)
 8000c10:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000c14:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8000c16:	f7ff fdbb 	bl	8000790 <HAL_GetTick>
 8000c1a:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000c1c:	e011      	b.n	8000c42 <HAL_RCC_OscConfig+0x2ce>
 8000c1e:	bf00      	nop
 8000c20:	40023800 	.word	0x40023800
 8000c24:	42470000 	.word	0x42470000
 8000c28:	42470e80 	.word	0x42470e80
 8000c2c:	40007000 	.word	0x40007000
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8000c30:	f7ff fdae 	bl	8000790 <HAL_GetTick>
 8000c34:	4602      	mov	r2, r0
 8000c36:	693b      	ldr	r3, [r7, #16]
 8000c38:	1ad3      	subs	r3, r2, r3
 8000c3a:	2b02      	cmp	r3, #2
 8000c3c:	d901      	bls.n	8000c42 <HAL_RCC_OscConfig+0x2ce>
        {
          return HAL_TIMEOUT;
 8000c3e:	2303      	movs	r3, #3
 8000c40:	e106      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000c42:	4b85      	ldr	r3, [pc, #532]	; (8000e58 <HAL_RCC_OscConfig+0x4e4>)
 8000c44:	681b      	ldr	r3, [r3, #0]
 8000c46:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8000c4a:	2b00      	cmp	r3, #0
 8000c4c:	d0f0      	beq.n	8000c30 <HAL_RCC_OscConfig+0x2bc>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000c4e:	687b      	ldr	r3, [r7, #4]
 8000c50:	689b      	ldr	r3, [r3, #8]
 8000c52:	2b01      	cmp	r3, #1
 8000c54:	d106      	bne.n	8000c64 <HAL_RCC_OscConfig+0x2f0>
 8000c56:	4b81      	ldr	r3, [pc, #516]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c58:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8000c5a:	4a80      	ldr	r2, [pc, #512]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c5c:	f043 0301 	orr.w	r3, r3, #1
 8000c60:	6713      	str	r3, [r2, #112]	; 0x70
 8000c62:	e01c      	b.n	8000c9e <HAL_RCC_OscConfig+0x32a>
 8000c64:	687b      	ldr	r3, [r7, #4]
 8000c66:	689b      	ldr	r3, [r3, #8]
 8000c68:	2b05      	cmp	r3, #5
 8000c6a:	d10c      	bne.n	8000c86 <HAL_RCC_OscConfig+0x312>
 8000c6c:	4b7b      	ldr	r3, [pc, #492]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c6e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8000c70:	4a7a      	ldr	r2, [pc, #488]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c72:	f043 0304 	orr.w	r3, r3, #4
 8000c76:	6713      	str	r3, [r2, #112]	; 0x70
 8000c78:	4b78      	ldr	r3, [pc, #480]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c7a:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8000c7c:	4a77      	ldr	r2, [pc, #476]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c7e:	f043 0301 	orr.w	r3, r3, #1
 8000c82:	6713      	str	r3, [r2, #112]	; 0x70
 8000c84:	e00b      	b.n	8000c9e <HAL_RCC_OscConfig+0x32a>
 8000c86:	4b75      	ldr	r3, [pc, #468]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c88:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8000c8a:	4a74      	ldr	r2, [pc, #464]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c8c:	f023 0301 	bic.w	r3, r3, #1
 8000c90:	6713      	str	r3, [r2, #112]	; 0x70
 8000c92:	4b72      	ldr	r3, [pc, #456]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c94:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8000c96:	4a71      	ldr	r2, [pc, #452]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000c98:	f023 0304 	bic.w	r3, r3, #4
 8000c9c:	6713      	str	r3, [r2, #112]	; 0x70
    /* Check the LSE State */
    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
 8000c9e:	687b      	ldr	r3, [r7, #4]
 8000ca0:	689b      	ldr	r3, [r3, #8]
 8000ca2:	2b00      	cmp	r3, #0
 8000ca4:	d015      	beq.n	8000cd2 <HAL_RCC_OscConfig+0x35e>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8000ca6:	f7ff fd73 	bl	8000790 <HAL_GetTick>
 8000caa:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8000cac:	e00a      	b.n	8000cc4 <HAL_RCC_OscConfig+0x350>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000cae:	f7ff fd6f 	bl	8000790 <HAL_GetTick>
 8000cb2:	4602      	mov	r2, r0
 8000cb4:	693b      	ldr	r3, [r7, #16]
 8000cb6:	1ad3      	subs	r3, r2, r3
 8000cb8:	f241 3288 	movw	r2, #5000	; 0x1388
 8000cbc:	4293      	cmp	r3, r2
 8000cbe:	d901      	bls.n	8000cc4 <HAL_RCC_OscConfig+0x350>
        {
          return HAL_TIMEOUT;
 8000cc0:	2303      	movs	r3, #3
 8000cc2:	e0c5      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8000cc4:	4b65      	ldr	r3, [pc, #404]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000cc6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8000cc8:	f003 0302 	and.w	r3, r3, #2
 8000ccc:	2b00      	cmp	r3, #0
 8000cce:	d0ee      	beq.n	8000cae <HAL_RCC_OscConfig+0x33a>
 8000cd0:	e014      	b.n	8000cfc <HAL_RCC_OscConfig+0x388>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000cd2:	f7ff fd5d 	bl	8000790 <HAL_GetTick>
 8000cd6:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8000cd8:	e00a      	b.n	8000cf0 <HAL_RCC_OscConfig+0x37c>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000cda:	f7ff fd59 	bl	8000790 <HAL_GetTick>
 8000cde:	4602      	mov	r2, r0
 8000ce0:	693b      	ldr	r3, [r7, #16]
 8000ce2:	1ad3      	subs	r3, r2, r3
 8000ce4:	f241 3288 	movw	r2, #5000	; 0x1388
 8000ce8:	4293      	cmp	r3, r2
 8000cea:	d901      	bls.n	8000cf0 <HAL_RCC_OscConfig+0x37c>
        {
          return HAL_TIMEOUT;
 8000cec:	2303      	movs	r3, #3
 8000cee:	e0af      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8000cf0:	4b5a      	ldr	r3, [pc, #360]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000cf2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8000cf4:	f003 0302 	and.w	r3, r3, #2
 8000cf8:	2b00      	cmp	r3, #0
 8000cfa:	d1ee      	bne.n	8000cda <HAL_RCC_OscConfig+0x366>
        }
      }
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 8000cfc:	7dfb      	ldrb	r3, [r7, #23]
 8000cfe:	2b01      	cmp	r3, #1
 8000d00:	d105      	bne.n	8000d0e <HAL_RCC_OscConfig+0x39a>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8000d02:	4b56      	ldr	r3, [pc, #344]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000d04:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000d06:	4a55      	ldr	r2, [pc, #340]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000d08:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8000d0c:	6413      	str	r3, [r2, #64]	; 0x40
    }
  }
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8000d0e:	687b      	ldr	r3, [r7, #4]
 8000d10:	699b      	ldr	r3, [r3, #24]
 8000d12:	2b00      	cmp	r3, #0
 8000d14:	f000 809b 	beq.w	8000e4e <HAL_RCC_OscConfig+0x4da>
  {
    /* Check if the PLL is used as system clock or not */
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
 8000d18:	4b50      	ldr	r3, [pc, #320]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000d1a:	689b      	ldr	r3, [r3, #8]
 8000d1c:	f003 030c 	and.w	r3, r3, #12
 8000d20:	2b08      	cmp	r3, #8
 8000d22:	d05c      	beq.n	8000dde <HAL_RCC_OscConfig+0x46a>
    {
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8000d24:	687b      	ldr	r3, [r7, #4]
 8000d26:	699b      	ldr	r3, [r3, #24]
 8000d28:	2b02      	cmp	r3, #2
 8000d2a:	d141      	bne.n	8000db0 <HAL_RCC_OscConfig+0x43c>
        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8000d2c:	4b4c      	ldr	r3, [pc, #304]	; (8000e60 <HAL_RCC_OscConfig+0x4ec>)
 8000d2e:	2200      	movs	r2, #0
 8000d30:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000d32:	f7ff fd2d 	bl	8000790 <HAL_GetTick>
 8000d36:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8000d38:	e008      	b.n	8000d4c <HAL_RCC_OscConfig+0x3d8>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000d3a:	f7ff fd29 	bl	8000790 <HAL_GetTick>
 8000d3e:	4602      	mov	r2, r0
 8000d40:	693b      	ldr	r3, [r7, #16]
 8000d42:	1ad3      	subs	r3, r2, r3
 8000d44:	2b02      	cmp	r3, #2
 8000d46:	d901      	bls.n	8000d4c <HAL_RCC_OscConfig+0x3d8>
          {
            return HAL_TIMEOUT;
 8000d48:	2303      	movs	r3, #3
 8000d4a:	e081      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8000d4c:	4b43      	ldr	r3, [pc, #268]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000d4e:	681b      	ldr	r3, [r3, #0]
 8000d50:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8000d54:	2b00      	cmp	r3, #0
 8000d56:	d1f0      	bne.n	8000d3a <HAL_RCC_OscConfig+0x3c6>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
 8000d58:	687b      	ldr	r3, [r7, #4]
 8000d5a:	69da      	ldr	r2, [r3, #28]
 8000d5c:	687b      	ldr	r3, [r7, #4]
 8000d5e:	6a1b      	ldr	r3, [r3, #32]
 8000d60:	431a      	orrs	r2, r3
 8000d62:	687b      	ldr	r3, [r7, #4]
 8000d64:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000d66:	019b      	lsls	r3, r3, #6
 8000d68:	431a      	orrs	r2, r3
 8000d6a:	687b      	ldr	r3, [r7, #4]
 8000d6c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8000d6e:	085b      	lsrs	r3, r3, #1
 8000d70:	3b01      	subs	r3, #1
 8000d72:	041b      	lsls	r3, r3, #16
 8000d74:	431a      	orrs	r2, r3
 8000d76:	687b      	ldr	r3, [r7, #4]
 8000d78:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8000d7a:	061b      	lsls	r3, r3, #24
 8000d7c:	4937      	ldr	r1, [pc, #220]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000d7e:	4313      	orrs	r3, r2
 8000d80:	604b      	str	r3, [r1, #4]
                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 8000d82:	4b37      	ldr	r3, [pc, #220]	; (8000e60 <HAL_RCC_OscConfig+0x4ec>)
 8000d84:	2201      	movs	r2, #1
 8000d86:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000d88:	f7ff fd02 	bl	8000790 <HAL_GetTick>
 8000d8c:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8000d8e:	e008      	b.n	8000da2 <HAL_RCC_OscConfig+0x42e>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000d90:	f7ff fcfe 	bl	8000790 <HAL_GetTick>
 8000d94:	4602      	mov	r2, r0
 8000d96:	693b      	ldr	r3, [r7, #16]
 8000d98:	1ad3      	subs	r3, r2, r3
 8000d9a:	2b02      	cmp	r3, #2
 8000d9c:	d901      	bls.n	8000da2 <HAL_RCC_OscConfig+0x42e>
          {
            return HAL_TIMEOUT;
 8000d9e:	2303      	movs	r3, #3
 8000da0:	e056      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8000da2:	4b2e      	ldr	r3, [pc, #184]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000da4:	681b      	ldr	r3, [r3, #0]
 8000da6:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8000daa:	2b00      	cmp	r3, #0
 8000dac:	d0f0      	beq.n	8000d90 <HAL_RCC_OscConfig+0x41c>
 8000dae:	e04e      	b.n	8000e4e <HAL_RCC_OscConfig+0x4da>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8000db0:	4b2b      	ldr	r3, [pc, #172]	; (8000e60 <HAL_RCC_OscConfig+0x4ec>)
 8000db2:	2200      	movs	r2, #0
 8000db4:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000db6:	f7ff fceb 	bl	8000790 <HAL_GetTick>
 8000dba:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8000dbc:	e008      	b.n	8000dd0 <HAL_RCC_OscConfig+0x45c>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000dbe:	f7ff fce7 	bl	8000790 <HAL_GetTick>
 8000dc2:	4602      	mov	r2, r0
 8000dc4:	693b      	ldr	r3, [r7, #16]
 8000dc6:	1ad3      	subs	r3, r2, r3
 8000dc8:	2b02      	cmp	r3, #2
 8000dca:	d901      	bls.n	8000dd0 <HAL_RCC_OscConfig+0x45c>
          {
            return HAL_TIMEOUT;
 8000dcc:	2303      	movs	r3, #3
 8000dce:	e03f      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8000dd0:	4b22      	ldr	r3, [pc, #136]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000dd2:	681b      	ldr	r3, [r3, #0]
 8000dd4:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8000dd8:	2b00      	cmp	r3, #0
 8000dda:	d1f0      	bne.n	8000dbe <HAL_RCC_OscConfig+0x44a>
 8000ddc:	e037      	b.n	8000e4e <HAL_RCC_OscConfig+0x4da>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8000dde:	687b      	ldr	r3, [r7, #4]
 8000de0:	699b      	ldr	r3, [r3, #24]
 8000de2:	2b01      	cmp	r3, #1
 8000de4:	d101      	bne.n	8000dea <HAL_RCC_OscConfig+0x476>
      {
        return HAL_ERROR;
 8000de6:	2301      	movs	r3, #1
 8000de8:	e032      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->PLLCFGR;
 8000dea:	4b1c      	ldr	r3, [pc, #112]	; (8000e5c <HAL_RCC_OscConfig+0x4e8>)
 8000dec:	685b      	ldr	r3, [r3, #4]
 8000dee:	60fb      	str	r3, [r7, #12]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 8000df0:	687b      	ldr	r3, [r7, #4]
 8000df2:	699b      	ldr	r3, [r3, #24]
 8000df4:	2b01      	cmp	r3, #1
 8000df6:	d028      	beq.n	8000e4a <HAL_RCC_OscConfig+0x4d6>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8000df8:	68fb      	ldr	r3, [r7, #12]
 8000dfa:	f403 0280 	and.w	r2, r3, #4194304	; 0x400000
 8000dfe:	687b      	ldr	r3, [r7, #4]
 8000e00:	69db      	ldr	r3, [r3, #28]
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 8000e02:	429a      	cmp	r2, r3
 8000e04:	d121      	bne.n	8000e4a <HAL_RCC_OscConfig+0x4d6>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 8000e06:	68fb      	ldr	r3, [r7, #12]
 8000e08:	f003 023f 	and.w	r2, r3, #63	; 0x3f
 8000e0c:	687b      	ldr	r3, [r7, #4]
 8000e0e:	6a1b      	ldr	r3, [r3, #32]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8000e10:	429a      	cmp	r2, r3
 8000e12:	d11a      	bne.n	8000e4a <HAL_RCC_OscConfig+0x4d6>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 8000e14:	68fa      	ldr	r2, [r7, #12]
 8000e16:	f647 73c0 	movw	r3, #32704	; 0x7fc0
 8000e1a:	4013      	ands	r3, r2
 8000e1c:	687a      	ldr	r2, [r7, #4]
 8000e1e:	6a52      	ldr	r2, [r2, #36]	; 0x24
 8000e20:	0192      	lsls	r2, r2, #6
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 8000e22:	4293      	cmp	r3, r2
 8000e24:	d111      	bne.n	8000e4a <HAL_RCC_OscConfig+0x4d6>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 8000e26:	68fb      	ldr	r3, [r7, #12]
 8000e28:	f403 3240 	and.w	r2, r3, #196608	; 0x30000
 8000e2c:	687b      	ldr	r3, [r7, #4]
 8000e2e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8000e30:	085b      	lsrs	r3, r3, #1
 8000e32:	3b01      	subs	r3, #1
 8000e34:	041b      	lsls	r3, r3, #16
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 8000e36:	429a      	cmp	r2, r3
 8000e38:	d107      	bne.n	8000e4a <HAL_RCC_OscConfig+0x4d6>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
 8000e3a:	68fb      	ldr	r3, [r7, #12]
 8000e3c:	f003 6270 	and.w	r2, r3, #251658240	; 0xf000000
 8000e40:	687b      	ldr	r3, [r7, #4]
 8000e42:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8000e44:	061b      	lsls	r3, r3, #24
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 8000e46:	429a      	cmp	r2, r3
 8000e48:	d001      	beq.n	8000e4e <HAL_RCC_OscConfig+0x4da>
#endif
        {
          return HAL_ERROR;
 8000e4a:	2301      	movs	r3, #1
 8000e4c:	e000      	b.n	8000e50 <HAL_RCC_OscConfig+0x4dc>
        }
      }
    }
  }
  return HAL_OK;
 8000e4e:	2300      	movs	r3, #0
}
 8000e50:	4618      	mov	r0, r3
 8000e52:	3718      	adds	r7, #24
 8000e54:	46bd      	mov	sp, r7
 8000e56:	bd80      	pop	{r7, pc}
 8000e58:	40007000 	.word	0x40007000
 8000e5c:	40023800 	.word	0x40023800
 8000e60:	42470060 	.word	0x42470060

08000e64 <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 8000e64:	b580      	push	{r7, lr}
 8000e66:	b084      	sub	sp, #16
 8000e68:	af00      	add	r7, sp, #0
 8000e6a:	6078      	str	r0, [r7, #4]
 8000e6c:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 8000e6e:	687b      	ldr	r3, [r7, #4]
 8000e70:	2b00      	cmp	r3, #0
 8000e72:	d101      	bne.n	8000e78 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 8000e74:	2301      	movs	r3, #1
 8000e76:	e0cc      	b.n	8001012 <HAL_RCC_ClockConfig+0x1ae>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8000e78:	4b68      	ldr	r3, [pc, #416]	; (800101c <HAL_RCC_ClockConfig+0x1b8>)
 8000e7a:	681b      	ldr	r3, [r3, #0]
 8000e7c:	f003 0307 	and.w	r3, r3, #7
 8000e80:	683a      	ldr	r2, [r7, #0]
 8000e82:	429a      	cmp	r2, r3
 8000e84:	d90c      	bls.n	8000ea0 <HAL_RCC_ClockConfig+0x3c>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8000e86:	4b65      	ldr	r3, [pc, #404]	; (800101c <HAL_RCC_ClockConfig+0x1b8>)
 8000e88:	683a      	ldr	r2, [r7, #0]
 8000e8a:	b2d2      	uxtb	r2, r2
 8000e8c:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8000e8e:	4b63      	ldr	r3, [pc, #396]	; (800101c <HAL_RCC_ClockConfig+0x1b8>)
 8000e90:	681b      	ldr	r3, [r3, #0]
 8000e92:	f003 0307 	and.w	r3, r3, #7
 8000e96:	683a      	ldr	r2, [r7, #0]
 8000e98:	429a      	cmp	r2, r3
 8000e9a:	d001      	beq.n	8000ea0 <HAL_RCC_ClockConfig+0x3c>
    {
      return HAL_ERROR;
 8000e9c:	2301      	movs	r3, #1
 8000e9e:	e0b8      	b.n	8001012 <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8000ea0:	687b      	ldr	r3, [r7, #4]
 8000ea2:	681b      	ldr	r3, [r3, #0]
 8000ea4:	f003 0302 	and.w	r3, r3, #2
 8000ea8:	2b00      	cmp	r3, #0
 8000eaa:	d020      	beq.n	8000eee <HAL_RCC_ClockConfig+0x8a>
  {
    /* Set the highest APBx dividers in order to ensure that we do not go through
       a non-spec phase whatever we decrease or increase HCLK. */
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8000eac:	687b      	ldr	r3, [r7, #4]
 8000eae:	681b      	ldr	r3, [r3, #0]
 8000eb0:	f003 0304 	and.w	r3, r3, #4
 8000eb4:	2b00      	cmp	r3, #0
 8000eb6:	d005      	beq.n	8000ec4 <HAL_RCC_ClockConfig+0x60>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8000eb8:	4b59      	ldr	r3, [pc, #356]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000eba:	689b      	ldr	r3, [r3, #8]
 8000ebc:	4a58      	ldr	r2, [pc, #352]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000ebe:	f443 53e0 	orr.w	r3, r3, #7168	; 0x1c00
 8000ec2:	6093      	str	r3, [r2, #8]
    }

    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8000ec4:	687b      	ldr	r3, [r7, #4]
 8000ec6:	681b      	ldr	r3, [r3, #0]
 8000ec8:	f003 0308 	and.w	r3, r3, #8
 8000ecc:	2b00      	cmp	r3, #0
 8000ece:	d005      	beq.n	8000edc <HAL_RCC_ClockConfig+0x78>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8000ed0:	4b53      	ldr	r3, [pc, #332]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000ed2:	689b      	ldr	r3, [r3, #8]
 8000ed4:	4a52      	ldr	r2, [pc, #328]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000ed6:	f443 4360 	orr.w	r3, r3, #57344	; 0xe000
 8000eda:	6093      	str	r3, [r2, #8]
    }

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8000edc:	4b50      	ldr	r3, [pc, #320]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000ede:	689b      	ldr	r3, [r3, #8]
 8000ee0:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8000ee4:	687b      	ldr	r3, [r7, #4]
 8000ee6:	689b      	ldr	r3, [r3, #8]
 8000ee8:	494d      	ldr	r1, [pc, #308]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000eea:	4313      	orrs	r3, r2
 8000eec:	608b      	str	r3, [r1, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8000eee:	687b      	ldr	r3, [r7, #4]
 8000ef0:	681b      	ldr	r3, [r3, #0]
 8000ef2:	f003 0301 	and.w	r3, r3, #1
 8000ef6:	2b00      	cmp	r3, #0
 8000ef8:	d044      	beq.n	8000f84 <HAL_RCC_ClockConfig+0x120>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8000efa:	687b      	ldr	r3, [r7, #4]
 8000efc:	685b      	ldr	r3, [r3, #4]
 8000efe:	2b01      	cmp	r3, #1
 8000f00:	d107      	bne.n	8000f12 <HAL_RCC_ClockConfig+0xae>
    {
      /* Check the HSE ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000f02:	4b47      	ldr	r3, [pc, #284]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000f04:	681b      	ldr	r3, [r3, #0]
 8000f06:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000f0a:	2b00      	cmp	r3, #0
 8000f0c:	d119      	bne.n	8000f42 <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8000f0e:	2301      	movs	r3, #1
 8000f10:	e07f      	b.n	8001012 <HAL_RCC_ClockConfig+0x1ae>
      }
    }
    /* PLL is selected as System Clock Source */
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8000f12:	687b      	ldr	r3, [r7, #4]
 8000f14:	685b      	ldr	r3, [r3, #4]
 8000f16:	2b02      	cmp	r3, #2
 8000f18:	d003      	beq.n	8000f22 <HAL_RCC_ClockConfig+0xbe>
            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
 8000f1a:	687b      	ldr	r3, [r7, #4]
 8000f1c:	685b      	ldr	r3, [r3, #4]
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8000f1e:	2b03      	cmp	r3, #3
 8000f20:	d107      	bne.n	8000f32 <HAL_RCC_ClockConfig+0xce>
    {
      /* Check the PLL ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8000f22:	4b3f      	ldr	r3, [pc, #252]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000f24:	681b      	ldr	r3, [r3, #0]
 8000f26:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8000f2a:	2b00      	cmp	r3, #0
 8000f2c:	d109      	bne.n	8000f42 <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8000f2e:	2301      	movs	r3, #1
 8000f30:	e06f      	b.n	8001012 <HAL_RCC_ClockConfig+0x1ae>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000f32:	4b3b      	ldr	r3, [pc, #236]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000f34:	681b      	ldr	r3, [r3, #0]
 8000f36:	f003 0302 	and.w	r3, r3, #2
 8000f3a:	2b00      	cmp	r3, #0
 8000f3c:	d101      	bne.n	8000f42 <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8000f3e:	2301      	movs	r3, #1
 8000f40:	e067      	b.n	8001012 <HAL_RCC_ClockConfig+0x1ae>
      }
    }

    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8000f42:	4b37      	ldr	r3, [pc, #220]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000f44:	689b      	ldr	r3, [r3, #8]
 8000f46:	f023 0203 	bic.w	r2, r3, #3
 8000f4a:	687b      	ldr	r3, [r7, #4]
 8000f4c:	685b      	ldr	r3, [r3, #4]
 8000f4e:	4934      	ldr	r1, [pc, #208]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000f50:	4313      	orrs	r3, r2
 8000f52:	608b      	str	r3, [r1, #8]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 8000f54:	f7ff fc1c 	bl	8000790 <HAL_GetTick>
 8000f58:	60f8      	str	r0, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8000f5a:	e00a      	b.n	8000f72 <HAL_RCC_ClockConfig+0x10e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8000f5c:	f7ff fc18 	bl	8000790 <HAL_GetTick>
 8000f60:	4602      	mov	r2, r0
 8000f62:	68fb      	ldr	r3, [r7, #12]
 8000f64:	1ad3      	subs	r3, r2, r3
 8000f66:	f241 3288 	movw	r2, #5000	; 0x1388
 8000f6a:	4293      	cmp	r3, r2
 8000f6c:	d901      	bls.n	8000f72 <HAL_RCC_ClockConfig+0x10e>
      {
        return HAL_TIMEOUT;
 8000f6e:	2303      	movs	r3, #3
 8000f70:	e04f      	b.n	8001012 <HAL_RCC_ClockConfig+0x1ae>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8000f72:	4b2b      	ldr	r3, [pc, #172]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000f74:	689b      	ldr	r3, [r3, #8]
 8000f76:	f003 020c 	and.w	r2, r3, #12
 8000f7a:	687b      	ldr	r3, [r7, #4]
 8000f7c:	685b      	ldr	r3, [r3, #4]
 8000f7e:	009b      	lsls	r3, r3, #2
 8000f80:	429a      	cmp	r2, r3
 8000f82:	d1eb      	bne.n	8000f5c <HAL_RCC_ClockConfig+0xf8>
      }
    }
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8000f84:	4b25      	ldr	r3, [pc, #148]	; (800101c <HAL_RCC_ClockConfig+0x1b8>)
 8000f86:	681b      	ldr	r3, [r3, #0]
 8000f88:	f003 0307 	and.w	r3, r3, #7
 8000f8c:	683a      	ldr	r2, [r7, #0]
 8000f8e:	429a      	cmp	r2, r3
 8000f90:	d20c      	bcs.n	8000fac <HAL_RCC_ClockConfig+0x148>
  {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 8000f92:	4b22      	ldr	r3, [pc, #136]	; (800101c <HAL_RCC_ClockConfig+0x1b8>)
 8000f94:	683a      	ldr	r2, [r7, #0]
 8000f96:	b2d2      	uxtb	r2, r2
 8000f98:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8000f9a:	4b20      	ldr	r3, [pc, #128]	; (800101c <HAL_RCC_ClockConfig+0x1b8>)
 8000f9c:	681b      	ldr	r3, [r3, #0]
 8000f9e:	f003 0307 	and.w	r3, r3, #7
 8000fa2:	683a      	ldr	r2, [r7, #0]
 8000fa4:	429a      	cmp	r2, r3
 8000fa6:	d001      	beq.n	8000fac <HAL_RCC_ClockConfig+0x148>
    {
      return HAL_ERROR;
 8000fa8:	2301      	movs	r3, #1
 8000faa:	e032      	b.n	8001012 <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8000fac:	687b      	ldr	r3, [r7, #4]
 8000fae:	681b      	ldr	r3, [r3, #0]
 8000fb0:	f003 0304 	and.w	r3, r3, #4
 8000fb4:	2b00      	cmp	r3, #0
 8000fb6:	d008      	beq.n	8000fca <HAL_RCC_ClockConfig+0x166>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8000fb8:	4b19      	ldr	r3, [pc, #100]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000fba:	689b      	ldr	r3, [r3, #8]
 8000fbc:	f423 52e0 	bic.w	r2, r3, #7168	; 0x1c00
 8000fc0:	687b      	ldr	r3, [r7, #4]
 8000fc2:	68db      	ldr	r3, [r3, #12]
 8000fc4:	4916      	ldr	r1, [pc, #88]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000fc6:	4313      	orrs	r3, r2
 8000fc8:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8000fca:	687b      	ldr	r3, [r7, #4]
 8000fcc:	681b      	ldr	r3, [r3, #0]
 8000fce:	f003 0308 	and.w	r3, r3, #8
 8000fd2:	2b00      	cmp	r3, #0
 8000fd4:	d009      	beq.n	8000fea <HAL_RCC_ClockConfig+0x186>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8000fd6:	4b12      	ldr	r3, [pc, #72]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000fd8:	689b      	ldr	r3, [r3, #8]
 8000fda:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 8000fde:	687b      	ldr	r3, [r7, #4]
 8000fe0:	691b      	ldr	r3, [r3, #16]
 8000fe2:	00db      	lsls	r3, r3, #3
 8000fe4:	490e      	ldr	r1, [pc, #56]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000fe6:	4313      	orrs	r3, r2
 8000fe8:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8000fea:	f000 f821 	bl	8001030 <HAL_RCC_GetSysClockFreq>
 8000fee:	4602      	mov	r2, r0
 8000ff0:	4b0b      	ldr	r3, [pc, #44]	; (8001020 <HAL_RCC_ClockConfig+0x1bc>)
 8000ff2:	689b      	ldr	r3, [r3, #8]
 8000ff4:	091b      	lsrs	r3, r3, #4
 8000ff6:	f003 030f 	and.w	r3, r3, #15
 8000ffa:	490a      	ldr	r1, [pc, #40]	; (8001024 <HAL_RCC_ClockConfig+0x1c0>)
 8000ffc:	5ccb      	ldrb	r3, [r1, r3]
 8000ffe:	fa22 f303 	lsr.w	r3, r2, r3
 8001002:	4a09      	ldr	r2, [pc, #36]	; (8001028 <HAL_RCC_ClockConfig+0x1c4>)
 8001004:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings */
  HAL_InitTick (uwTickPrio);
 8001006:	4b09      	ldr	r3, [pc, #36]	; (800102c <HAL_RCC_ClockConfig+0x1c8>)
 8001008:	681b      	ldr	r3, [r3, #0]
 800100a:	4618      	mov	r0, r3
 800100c:	f7ff fb7c 	bl	8000708 <HAL_InitTick>

  return HAL_OK;
 8001010:	2300      	movs	r3, #0
}
 8001012:	4618      	mov	r0, r3
 8001014:	3710      	adds	r7, #16
 8001016:	46bd      	mov	sp, r7
 8001018:	bd80      	pop	{r7, pc}
 800101a:	bf00      	nop
 800101c:	40023c00 	.word	0x40023c00
 8001020:	40023800 	.word	0x40023800
 8001024:	0800120c 	.word	0x0800120c
 8001028:	20000000 	.word	0x20000000
 800102c:	20000004 	.word	0x20000004

08001030 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8001030:	b5b0      	push	{r4, r5, r7, lr}
 8001032:	b084      	sub	sp, #16
 8001034:	af00      	add	r7, sp, #0
  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
 8001036:	2100      	movs	r1, #0
 8001038:	6079      	str	r1, [r7, #4]
 800103a:	2100      	movs	r1, #0
 800103c:	60f9      	str	r1, [r7, #12]
 800103e:	2100      	movs	r1, #0
 8001040:	6039      	str	r1, [r7, #0]
  uint32_t sysclockfreq = 0U;
 8001042:	2100      	movs	r1, #0
 8001044:	60b9      	str	r1, [r7, #8]

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (RCC->CFGR & RCC_CFGR_SWS)
 8001046:	4952      	ldr	r1, [pc, #328]	; (8001190 <HAL_RCC_GetSysClockFreq+0x160>)
 8001048:	6889      	ldr	r1, [r1, #8]
 800104a:	f001 010c 	and.w	r1, r1, #12
 800104e:	2908      	cmp	r1, #8
 8001050:	d00d      	beq.n	800106e <HAL_RCC_GetSysClockFreq+0x3e>
 8001052:	2908      	cmp	r1, #8
 8001054:	f200 8094 	bhi.w	8001180 <HAL_RCC_GetSysClockFreq+0x150>
 8001058:	2900      	cmp	r1, #0
 800105a:	d002      	beq.n	8001062 <HAL_RCC_GetSysClockFreq+0x32>
 800105c:	2904      	cmp	r1, #4
 800105e:	d003      	beq.n	8001068 <HAL_RCC_GetSysClockFreq+0x38>
 8001060:	e08e      	b.n	8001180 <HAL_RCC_GetSysClockFreq+0x150>
  {
    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
    {
      sysclockfreq = HSI_VALUE;
 8001062:	4b4c      	ldr	r3, [pc, #304]	; (8001194 <HAL_RCC_GetSysClockFreq+0x164>)
 8001064:	60bb      	str	r3, [r7, #8]
       break;
 8001066:	e08e      	b.n	8001186 <HAL_RCC_GetSysClockFreq+0x156>
    }
    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
    {
      sysclockfreq = HSE_VALUE;
 8001068:	4b4b      	ldr	r3, [pc, #300]	; (8001198 <HAL_RCC_GetSysClockFreq+0x168>)
 800106a:	60bb      	str	r3, [r7, #8]
      break;
 800106c:	e08b      	b.n	8001186 <HAL_RCC_GetSysClockFreq+0x156>
    }
    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
    {
      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
      SYSCLK = PLL_VCO / PLLP */
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 800106e:	4948      	ldr	r1, [pc, #288]	; (8001190 <HAL_RCC_GetSysClockFreq+0x160>)
 8001070:	6849      	ldr	r1, [r1, #4]
 8001072:	f001 013f 	and.w	r1, r1, #63	; 0x3f
 8001076:	6079      	str	r1, [r7, #4]
      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 8001078:	4945      	ldr	r1, [pc, #276]	; (8001190 <HAL_RCC_GetSysClockFreq+0x160>)
 800107a:	6849      	ldr	r1, [r1, #4]
 800107c:	f401 0180 	and.w	r1, r1, #4194304	; 0x400000
 8001080:	2900      	cmp	r1, #0
 8001082:	d024      	beq.n	80010ce <HAL_RCC_GetSysClockFreq+0x9e>
      {
        /* HSE used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 8001084:	4942      	ldr	r1, [pc, #264]	; (8001190 <HAL_RCC_GetSysClockFreq+0x160>)
 8001086:	6849      	ldr	r1, [r1, #4]
 8001088:	0989      	lsrs	r1, r1, #6
 800108a:	4608      	mov	r0, r1
 800108c:	f04f 0100 	mov.w	r1, #0
 8001090:	f240 14ff 	movw	r4, #511	; 0x1ff
 8001094:	f04f 0500 	mov.w	r5, #0
 8001098:	ea00 0204 	and.w	r2, r0, r4
 800109c:	ea01 0305 	and.w	r3, r1, r5
 80010a0:	493d      	ldr	r1, [pc, #244]	; (8001198 <HAL_RCC_GetSysClockFreq+0x168>)
 80010a2:	fb01 f003 	mul.w	r0, r1, r3
 80010a6:	2100      	movs	r1, #0
 80010a8:	fb01 f102 	mul.w	r1, r1, r2
 80010ac:	1844      	adds	r4, r0, r1
 80010ae:	493a      	ldr	r1, [pc, #232]	; (8001198 <HAL_RCC_GetSysClockFreq+0x168>)
 80010b0:	fba2 0101 	umull	r0, r1, r2, r1
 80010b4:	1863      	adds	r3, r4, r1
 80010b6:	4619      	mov	r1, r3
 80010b8:	687b      	ldr	r3, [r7, #4]
 80010ba:	461a      	mov	r2, r3
 80010bc:	f04f 0300 	mov.w	r3, #0
 80010c0:	f7ff f88a 	bl	80001d8 <__aeabi_uldivmod>
 80010c4:	4602      	mov	r2, r0
 80010c6:	460b      	mov	r3, r1
 80010c8:	4613      	mov	r3, r2
 80010ca:	60fb      	str	r3, [r7, #12]
 80010cc:	e04a      	b.n	8001164 <HAL_RCC_GetSysClockFreq+0x134>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 80010ce:	4b30      	ldr	r3, [pc, #192]	; (8001190 <HAL_RCC_GetSysClockFreq+0x160>)
 80010d0:	685b      	ldr	r3, [r3, #4]
 80010d2:	099b      	lsrs	r3, r3, #6
 80010d4:	461a      	mov	r2, r3
 80010d6:	f04f 0300 	mov.w	r3, #0
 80010da:	f240 10ff 	movw	r0, #511	; 0x1ff
 80010de:	f04f 0100 	mov.w	r1, #0
 80010e2:	ea02 0400 	and.w	r4, r2, r0
 80010e6:	ea03 0501 	and.w	r5, r3, r1
 80010ea:	4620      	mov	r0, r4
 80010ec:	4629      	mov	r1, r5
 80010ee:	f04f 0200 	mov.w	r2, #0
 80010f2:	f04f 0300 	mov.w	r3, #0
 80010f6:	014b      	lsls	r3, r1, #5
 80010f8:	ea43 63d0 	orr.w	r3, r3, r0, lsr #27
 80010fc:	0142      	lsls	r2, r0, #5
 80010fe:	4610      	mov	r0, r2
 8001100:	4619      	mov	r1, r3
 8001102:	1b00      	subs	r0, r0, r4
 8001104:	eb61 0105 	sbc.w	r1, r1, r5
 8001108:	f04f 0200 	mov.w	r2, #0
 800110c:	f04f 0300 	mov.w	r3, #0
 8001110:	018b      	lsls	r3, r1, #6
 8001112:	ea43 6390 	orr.w	r3, r3, r0, lsr #26
 8001116:	0182      	lsls	r2, r0, #6
 8001118:	1a12      	subs	r2, r2, r0
 800111a:	eb63 0301 	sbc.w	r3, r3, r1
 800111e:	f04f 0000 	mov.w	r0, #0
 8001122:	f04f 0100 	mov.w	r1, #0
 8001126:	00d9      	lsls	r1, r3, #3
 8001128:	ea41 7152 	orr.w	r1, r1, r2, lsr #29
 800112c:	00d0      	lsls	r0, r2, #3
 800112e:	4602      	mov	r2, r0
 8001130:	460b      	mov	r3, r1
 8001132:	1912      	adds	r2, r2, r4
 8001134:	eb45 0303 	adc.w	r3, r5, r3
 8001138:	f04f 0000 	mov.w	r0, #0
 800113c:	f04f 0100 	mov.w	r1, #0
 8001140:	0299      	lsls	r1, r3, #10
 8001142:	ea41 5192 	orr.w	r1, r1, r2, lsr #22
 8001146:	0290      	lsls	r0, r2, #10
 8001148:	4602      	mov	r2, r0
 800114a:	460b      	mov	r3, r1
 800114c:	4610      	mov	r0, r2
 800114e:	4619      	mov	r1, r3
 8001150:	687b      	ldr	r3, [r7, #4]
 8001152:	461a      	mov	r2, r3
 8001154:	f04f 0300 	mov.w	r3, #0
 8001158:	f7ff f83e 	bl	80001d8 <__aeabi_uldivmod>
 800115c:	4602      	mov	r2, r0
 800115e:	460b      	mov	r3, r1
 8001160:	4613      	mov	r3, r2
 8001162:	60fb      	str	r3, [r7, #12]
      }
      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
 8001164:	4b0a      	ldr	r3, [pc, #40]	; (8001190 <HAL_RCC_GetSysClockFreq+0x160>)
 8001166:	685b      	ldr	r3, [r3, #4]
 8001168:	0c1b      	lsrs	r3, r3, #16
 800116a:	f003 0303 	and.w	r3, r3, #3
 800116e:	3301      	adds	r3, #1
 8001170:	005b      	lsls	r3, r3, #1
 8001172:	603b      	str	r3, [r7, #0]

      sysclockfreq = pllvco/pllp;
 8001174:	68fa      	ldr	r2, [r7, #12]
 8001176:	683b      	ldr	r3, [r7, #0]
 8001178:	fbb2 f3f3 	udiv	r3, r2, r3
 800117c:	60bb      	str	r3, [r7, #8]
      break;
 800117e:	e002      	b.n	8001186 <HAL_RCC_GetSysClockFreq+0x156>
    }
    default:
    {
      sysclockfreq = HSI_VALUE;
 8001180:	4b04      	ldr	r3, [pc, #16]	; (8001194 <HAL_RCC_GetSysClockFreq+0x164>)
 8001182:	60bb      	str	r3, [r7, #8]
      break;
 8001184:	bf00      	nop
    }
  }
  return sysclockfreq;
 8001186:	68bb      	ldr	r3, [r7, #8]
}
 8001188:	4618      	mov	r0, r3
 800118a:	3710      	adds	r7, #16
 800118c:	46bd      	mov	sp, r7
 800118e:	bdb0      	pop	{r4, r5, r7, pc}
 8001190:	40023800 	.word	0x40023800
 8001194:	00f42400 	.word	0x00f42400
 8001198:	017d7840 	.word	0x017d7840

0800119c <__libc_init_array>:
 800119c:	b570      	push	{r4, r5, r6, lr}
 800119e:	4d0d      	ldr	r5, [pc, #52]	; (80011d4 <__libc_init_array+0x38>)
 80011a0:	4c0d      	ldr	r4, [pc, #52]	; (80011d8 <__libc_init_array+0x3c>)
 80011a2:	1b64      	subs	r4, r4, r5
 80011a4:	10a4      	asrs	r4, r4, #2
 80011a6:	2600      	movs	r6, #0
 80011a8:	42a6      	cmp	r6, r4
 80011aa:	d109      	bne.n	80011c0 <__libc_init_array+0x24>
 80011ac:	4d0b      	ldr	r5, [pc, #44]	; (80011dc <__libc_init_array+0x40>)
 80011ae:	4c0c      	ldr	r4, [pc, #48]	; (80011e0 <__libc_init_array+0x44>)
 80011b0:	f000 f820 	bl	80011f4 <_init>
 80011b4:	1b64      	subs	r4, r4, r5
 80011b6:	10a4      	asrs	r4, r4, #2
 80011b8:	2600      	movs	r6, #0
 80011ba:	42a6      	cmp	r6, r4
 80011bc:	d105      	bne.n	80011ca <__libc_init_array+0x2e>
 80011be:	bd70      	pop	{r4, r5, r6, pc}
 80011c0:	f855 3b04 	ldr.w	r3, [r5], #4
 80011c4:	4798      	blx	r3
 80011c6:	3601      	adds	r6, #1
 80011c8:	e7ee      	b.n	80011a8 <__libc_init_array+0xc>
 80011ca:	f855 3b04 	ldr.w	r3, [r5], #4
 80011ce:	4798      	blx	r3
 80011d0:	3601      	adds	r6, #1
 80011d2:	e7f2      	b.n	80011ba <__libc_init_array+0x1e>
 80011d4:	08001224 	.word	0x08001224
 80011d8:	08001224 	.word	0x08001224
 80011dc:	08001224 	.word	0x08001224
 80011e0:	08001228 	.word	0x08001228

080011e4 <memset>:
 80011e4:	4402      	add	r2, r0
 80011e6:	4603      	mov	r3, r0
 80011e8:	4293      	cmp	r3, r2
 80011ea:	d100      	bne.n	80011ee <memset+0xa>
 80011ec:	4770      	bx	lr
 80011ee:	f803 1b01 	strb.w	r1, [r3], #1
 80011f2:	e7f9      	b.n	80011e8 <memset+0x4>

080011f4 <_init>:
 80011f4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80011f6:	bf00      	nop
 80011f8:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80011fa:	bc08      	pop	{r3}
 80011fc:	469e      	mov	lr, r3
 80011fe:	4770      	bx	lr

08001200 <_fini>:
 8001200:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001202:	bf00      	nop
 8001204:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001206:	bc08      	pop	{r3}
 8001208:	469e      	mov	lr, r3
 800120a:	4770      	bx	lr
