alternative design
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81
CAD/ClockClock/ClockClock-cache.lib
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81
CAD/ClockClock/ClockClock-cache.lib
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# MCU_ST_STM32L0_STM32L031K6Tx
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#
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DEF MCU_ST_STM32L0_STM32L031K6Tx U 0 20 Y Y 1 F N
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F0 "U" -500 850 50 H V L CNN
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F1 "MCU_ST_STM32L0_STM32L031K6Tx" 200 850 50 H V L CNN
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F2 "Package_QFP:LQFP-32_7x7mm_P0.8mm" -500 -900 50 H I R CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS STM32L031K6Tx
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$FPLIST
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LQFP*7x7mm*P0.8mm*
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$ENDFPLIST
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DRAW
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S -500 -900 400 800 0 1 10 f
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X VDD 1 -100 900 100 D 50 50 1 1 W
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X PA4 10 500 300 100 L 50 50 1 1 B
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X PA5 11 500 200 100 L 50 50 1 1 B
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X PA6 12 500 100 100 L 50 50 1 1 B
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X PA7 13 500 0 100 L 50 50 1 1 B
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X PB0 14 -600 -200 100 R 50 50 1 1 B
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X PB1 15 -600 -300 100 R 50 50 1 1 B
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X VSS 16 -100 -1000 100 U 50 50 1 1 W
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X VDD 17 0 900 100 D 50 50 1 1 W
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X PA8 18 500 -100 100 L 50 50 1 1 B
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X PA9 19 500 -200 100 L 50 50 1 1 B
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X PC14 2 -600 100 100 R 50 50 1 1 B
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X PA10 20 500 -300 100 L 50 50 1 1 B
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X PA11 21 500 -400 100 L 50 50 1 1 B
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X PA12 22 500 -500 100 L 50 50 1 1 B
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X PA13 23 500 -600 100 L 50 50 1 1 B
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X PA14 24 500 -700 100 L 50 50 1 1 B
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X PA15 25 500 -800 100 L 50 50 1 1 B
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X PB3 26 -600 -400 100 R 50 50 1 1 B
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X PB4 27 -600 -500 100 R 50 50 1 1 B
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X PB5 28 -600 -600 100 R 50 50 1 1 B
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X PB6 29 -600 -700 100 R 50 50 1 1 B
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X PC15 3 -600 0 100 R 50 50 1 1 B
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X PB7 30 -600 -800 100 R 50 50 1 1 B
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X BOOT0 31 -600 500 100 R 50 50 1 1 I
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X VSS 32 0 -1000 100 U 50 50 1 1 W
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X NRST 4 -600 700 100 R 50 50 1 1 I
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X VDDA 5 100 900 100 D 50 50 1 1 W
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X PA0 6 500 700 100 L 50 50 1 1 B
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X PA1 7 500 600 100 L 50 50 1 1 B
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X PA2 8 500 500 100 L 50 50 1 1 B
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X PA3 9 500 400 100 L 50 50 1 1 B
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ENDDRAW
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ENDDEF
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#
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# power_+3.3V
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#
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DEF power_+3.3V #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -150 50 H I C CNN
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F1 "power_+3.3V" 0 140 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS +3.3V
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DRAW
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P 2 0 1 0 -30 50 0 100 N
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P 2 0 1 0 0 0 0 100 N
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P 2 0 1 0 0 100 30 50 N
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X +3V3 1 0 0 0 U 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# power_GND
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#
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DEF power_GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -250 50 H I C CNN
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F1 "power_GND" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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#End Library
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1
CAD/ClockClock/ClockClock.kicad_pcb
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1
CAD/ClockClock/ClockClock.kicad_pcb
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(kicad_pcb (version 4) (host kicad "dummy file") )
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33
CAD/ClockClock/ClockClock.pro
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33
CAD/ClockClock/ClockClock.pro
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update=22/05/2015 07:44:53
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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74
CAD/ClockClock/ClockClock.sch
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74
CAD/ClockClock/ClockClock.sch
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EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 1
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L MCU_ST_STM32L0:STM32L031K6Tx U?
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U 1 1 604C17C5
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P 6000 2900
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F 0 "U?" H 5950 1811 50 0000 C CNN
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F 1 "STM32L031K6Tx" H 5950 1720 50 0000 C CNN
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F 2 "Package_QFP:LQFP-32_7x7mm_P0.8mm" H 5500 2000 50 0001 R CNN
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F 3 "http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00140359.pdf" H 6000 2900 50 0001 C CNN
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1 6000 2900
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1 0 0 -1
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$EndComp
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$Comp
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L power:+3.3V #PWR?
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U 1 1 604C2A16
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P 5950 1650
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F 0 "#PWR?" H 5950 1500 50 0001 C CNN
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F 1 "+3.3V" H 5965 1823 50 0000 C CNN
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F 2 "" H 5950 1650 50 0001 C CNN
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F 3 "" H 5950 1650 50 0001 C CNN
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1 5950 1650
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1 0 0 -1
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$EndComp
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Wire Wire Line
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5900 1750 5900 2000
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Wire Wire Line
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6000 2000 6000 1750
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Wire Wire Line
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6000 1750 5950 1750
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Wire Wire Line
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5950 1650 5950 1750
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Connection ~ 5950 1750
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Wire Wire Line
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5950 1750 5900 1750
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Wire Wire Line
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6100 2000 6100 1750
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Wire Wire Line
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6100 1750 6000 1750
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Connection ~ 6000 1750
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$Comp
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L power:GND #PWR?
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U 1 1 604C3752
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P 5900 4300
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F 0 "#PWR?" H 5900 4050 50 0001 C CNN
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F 1 "GND" H 5905 4127 50 0000 C CNN
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F 2 "" H 5900 4300 50 0001 C CNN
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F 3 "" H 5900 4300 50 0001 C CNN
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1 5900 4300
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1 0 0 -1
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$EndComp
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Wire Wire Line
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5900 4300 5900 4150
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Wire Wire Line
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6000 3900 6000 4150
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Wire Wire Line
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6000 4150 5900 4150
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Connection ~ 5900 4150
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Wire Wire Line
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5900 4150 5900 3900
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$EndSCHEMATC
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4
CAD/ClockClock/ClockClock.sch-bak
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4
CAD/ClockClock/ClockClock.sch-bak
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@@ -0,0 +1,4 @@
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EESchema Schematic File Version 2
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EELAYER 25 0
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EELAYER END
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$EndSCHEMATC
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7239
CAD/ClockClock/fp-info-cache
Normal file
7239
CAD/ClockClock/fp-info-cache
Normal file
File diff suppressed because it is too large
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