Check in initial electronics projects

This commit is contained in:
Scott Bezek
2021-11-01 22:40:10 -07:00
parent 26373a9b4e
commit 381df91b92
29 changed files with 8862 additions and 0 deletions

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(fp_lib_table
(lib (name lilygo_micro32)(type KiCad)(uri ${KIPRJMOD}/lib/lilygo_micro32.pretty)(options "")(descr ""))
(lib (name sk6812)(type KiCad)(uri ${KIPRJMOD}/lib/sk6812.pretty)(options "")(descr ""))
(lib (name tube_mounts)(type KiCad)(uri ${KIPRJMOD}/lib/tube_mounts.pretty)(options "")(descr ""))
)

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# T-Micro32_Plus
#
DEF T-Micro32_Plus U 0 40 Y Y 1 F N
F0 "U" -600 850 50 H V C CNN
F1 "T-Micro32_Plus" 0 700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S 650 -800 -650 800 0 1 0 f
X GND 1 -750 700 100 R 50 50 1 1 W
X IO25 10 -750 -200 100 R 50 50 1 1 B
X IO26 11 -750 -300 100 R 50 50 1 1 B
X IO27 12 -750 -400 100 R 50 50 1 1 B
X IO14 13 -750 -500 100 R 50 50 1 1 B
X IO12 14 -750 -600 100 R 50 50 1 1 B
X GND 15 -750 -700 100 R 50 50 1 1 W
X IO13 16 -350 -900 100 U 50 50 1 1 B
X IO37 17 -250 -900 100 U 50 50 1 1 I
X IO38 18 -150 -900 100 U 50 50 1 1 I
X NC 19 -50 -900 100 U 50 50 1 1 N
X 3V3 2 -750 600 100 R 50 50 1 1 W
X NC 20 50 -900 100 U 50 50 1 1 N
X IO7 21 150 -900 100 U 50 50 1 1 B
X IO8 22 250 -900 100 U 50 50 1 1 B
X IO15 23 350 -900 100 U 50 50 1 1 B
X IO2 24 750 -700 100 L 50 50 1 1 B
X IO0 25 750 -600 100 L 50 50 1 1 W
X IO4 26 750 -500 100 L 50 50 1 1 B
X NC 27 750 -400 100 L 50 50 1 1 N
X IO20 28 750 -300 100 L 50 50 1 1 B
X IO5 29 750 -200 100 L 50 50 1 1 B
X EN 3 -750 500 100 R 50 50 1 1 I
X NC 30 750 -100 100 L 50 50 1 1 N
X IO19 31 750 0 100 L 50 50 1 1 B
X VDD_SDIO 32 750 100 100 L 50 50 1 1 P
X IO21 33 750 200 100 L 50 50 1 1 B
X RXD 34 750 300 100 L 50 50 1 1 I
X TXD 35 750 400 100 L 50 50 1 1 O
X IO22 36 750 500 100 L 50 50 1 1 B
X NC 37 750 600 100 L 50 50 1 1 N
X GND 38 750 700 100 L 50 50 1 1 W
X IO36/SVP 4 -750 400 100 R 50 50 1 1 I
X IO39/SVN 5 -750 300 100 R 50 50 1 1 I
X IO34 6 -750 200 100 R 50 50 1 1 I
X IO35 7 -750 100 100 R 50 50 1 1 I
X IO32 8 -750 0 100 R 50 50 1 1 B
X IO33 9 -750 -100 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library

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(module T-Micro32 (layer F.Cu) (tedit 61131E02)
(fp_text reference REF** (at 2 -4.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value T-Micro32 (at 6.5 3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3 5.5) (end 3 12.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10 5.5) (end 3 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10 12.5) (end 10 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start 3 12.5) (end 10 12.5) (layer F.SilkS) (width 0.15))
(fp_line (start 12 -1.5) (end 13 -2) (layer F.SilkS) (width 0.15))
(fp_line (start 10 -1.5) (end 13 -3) (layer F.SilkS) (width 0.15))
(fp_line (start 8 -1.5) (end 12 -3.5) (layer F.SilkS) (width 0.15))
(fp_line (start 6 -1.5) (end 10 -3.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8 -3.5) (end 4 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -1.5) (end 6 -3.5) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1.5) (end 4 -3.5) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -2.5) (end 2 -3.5) (layer F.SilkS) (width 0.15))
(fp_line (start 13 15.5) (end 13 15) (layer F.SilkS) (width 0.15))
(fp_line (start 11 15.5) (end 13 15.5) (layer F.SilkS) (width 0.15))
(fp_line (start 0 15.5) (end 2 15.5) (layer F.SilkS) (width 0.15))
(fp_line (start 0 15) (end 0 15.5) (layer F.SilkS) (width 0.15))
(fp_line (start 13 -3.5) (end 13 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -3.5) (end 13 -3.5) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1) (end 0 -3.5) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at 0 0) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 0 1) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 0 2) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 0 3) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 0 4) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at 0 5) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at 0 6) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at 0 7) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at 0 8) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at 0 9) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at 0 10) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at 0 11) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 0 12) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 0 13) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at 0 14) (size 2.1 0.7) (drill (offset -0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at 3 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at 4 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at 5 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at 6 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at 7 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 8 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at 9 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at 10 15.5) (size 0.7 2.1) (drill (offset 0 0.3)) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at 13 14) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at 13 13) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at 13 12) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at 13 11) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at 13 10) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at 13 9) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at 13 8) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at 13 7) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at 13 6) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 13 5) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 34 smd rect (at 13 4) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 35 smd rect (at 13 3) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 36 smd rect (at 13 2) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 37 smd rect (at 13 1) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
(pad 38 smd rect (at 13 0) (size 2.1 0.7) (drill (offset 0.3 0)) (layers F.Cu F.Paste F.Mask))
)

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(module SK6812-SIDE-A (layer F.Cu) (tedit 6127EC07)
(fp_text reference REF** (at 2.032 -1.397) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SK6812-SIDE-A (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.7 -0.6) (end 4.3 -0.6) (layer F.SilkS) (width 0.1))
(fp_line (start 4.3 -0.6) (end 4.3 0.7) (layer F.SilkS) (width 0.1))
(fp_line (start 4.3 0.7) (end 3.7 1.4) (layer F.SilkS) (width 0.1))
(fp_line (start 3.7 1.4) (end -0.7 1.4) (layer F.SilkS) (width 0.1))
(fp_line (start -0.7 1.4) (end -0.7 -0.6) (layer F.SilkS) (width 0.1))
(pad 1 smd custom (at 0 0) (size 1 0.55) (layers F.Cu F.Paste F.Mask)
(zone_connect 0)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -0.05 -0.525) (xy 0.5 -0.525) (xy 0.5 0.675) (xy -0.05 0.675)) (width 0))
))
(pad 2 smd rect (at 1.35 0) (size 0.7 1.2) (drill (offset 0 0.075)) (layers F.Cu F.Paste F.Mask)
(zone_connect 0))
(pad 3 smd rect (at 2.375 0) (size 0.45 1.2) (drill (offset 0 0.075)) (layers F.Cu F.Paste F.Mask)
(zone_connect 0))
(pad 4 smd custom (at 3.6 0) (size 1 0.55) (layers F.Cu F.Paste F.Mask)
(zone_connect 0)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy 0.05 -0.525) (xy -0.5 -0.525) (xy -0.5 0.675) (xy 0.05 0.675)) (width 0))
))
)

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(module 5.5od_0.2thickness (layer F.Cu) (tedit 612A6DF6)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 5.5od_0.2thickness (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2.9 0) (layer F.Cu) (width 0.7))
(fp_circle (center 0 0) (end 2.9 0) (layer F.Mask) (width 0.8))
(pad "" thru_hole oval (at 0.762 0) (size 1 5.25) (drill oval 0.75 4.9) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at -0.889 -1.143) (size 1.98 1.98) (drill 1.12) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -0.889 1.143) (size 1.98 1.98) (drill 1.12) (layers *.Cu *.Mask))
)

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(module 5.5od_0.2thickness_no_pins (layer F.Cu) (tedit 612A700F)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 5.5od_0.2thickness_no_pins (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2.9 0) (layer F.Cu) (width 0.7))
(fp_circle (center 0 0) (end 2.9 0) (layer F.Mask) (width 0.8))
(fp_poly (pts (xy 0.879 2.27) (xy 0.769 2.27) (xy 0.769 -2.23) (xy 0.889 -2.23)) (layer Dwgs.User) (width 0.01))
(pad "" thru_hole oval (at 0.889 0) (size 0.6 5.05) (drill oval 0.35 4.8) (layers *.Cu *.Mask))
)

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Sensor_Magnetic_TLV493D
#
DEF Sensor_Magnetic_TLV493D U 0 20 Y Y 1 F N
F0 "U" -250 450 50 H V C CNN
F1 "Sensor_Magnetic_TLV493D" 200 450 50 H V C CNN
F2 "Package_TO_SOT_SMD:SOT-23-6" -50 -500 50 H I C CNN
F3 "" -150 500 50 H I C CNN
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
S -300 400 250 -300 0 1 10 f
X SCL/INT 1 -400 100 100 R 50 50 1 1 B
X GND 2 100 -400 100 U 50 50 1 1 W
X GND 3 0 -400 100 U 50 50 1 1 W
X VDD 4 0 500 100 D 50 50 1 1 W
X GND 5 -100 -400 100 U 50 50 1 1 W
X SDA/ADDR 6 -400 0 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# lilygo_micro32_T-Micro32_Plus
#
DEF lilygo_micro32_T-Micro32_Plus U 0 40 Y Y 1 F N
F0 "U" -600 850 50 H V C CNN
F1 "lilygo_micro32_T-Micro32_Plus" 0 700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S 650 -800 -650 800 0 1 0 f
X GND 1 -750 700 100 R 50 50 1 1 W
X IO25 10 -750 -200 100 R 50 50 1 1 B
X IO26 11 -750 -300 100 R 50 50 1 1 B
X IO27 12 -750 -400 100 R 50 50 1 1 B
X IO14 13 -750 -500 100 R 50 50 1 1 B
X IO12 14 -750 -600 100 R 50 50 1 1 B
X GND 15 -750 -700 100 R 50 50 1 1 W
X IO13 16 -350 -900 100 U 50 50 1 1 B
X IO37 17 -250 -900 100 U 50 50 1 1 I
X IO38 18 -150 -900 100 U 50 50 1 1 I
X NC 19 -50 -900 100 U 50 50 1 1 N
X 3V3 2 -750 600 100 R 50 50 1 1 W
X NC 20 50 -900 100 U 50 50 1 1 N
X IO7 21 150 -900 100 U 50 50 1 1 B
X IO8 22 250 -900 100 U 50 50 1 1 B
X IO15 23 350 -900 100 U 50 50 1 1 B
X IO2 24 750 -700 100 L 50 50 1 1 B
X IO0 25 750 -600 100 L 50 50 1 1 W
X IO4 26 750 -500 100 L 50 50 1 1 B
X NC 27 750 -400 100 L 50 50 1 1 N
X IO20 28 750 -300 100 L 50 50 1 1 B
X IO5 29 750 -200 100 L 50 50 1 1 B
X EN 3 -750 500 100 R 50 50 1 1 I
X NC 30 750 -100 100 L 50 50 1 1 N
X IO19 31 750 0 100 L 50 50 1 1 B
X VDD_SDIO 32 750 100 100 L 50 50 1 1 P
X IO21 33 750 200 100 L 50 50 1 1 B
X RXD 34 750 300 100 L 50 50 1 1 I
X TXD 35 750 400 100 L 50 50 1 1 O
X IO22 36 750 500 100 L 50 50 1 1 B
X NC 37 750 600 100 L 50 50 1 1 N
X GND 38 750 700 100 L 50 50 1 1 W
X IO36/SVP 4 -750 400 100 R 50 50 1 1 I
X IO39/SVN 5 -750 300 100 R 50 50 1 1 I
X IO34 6 -750 200 100 R 50 50 1 1 I
X IO35 7 -750 100 100 R 50 50 1 1 I
X IO32 8 -750 0 100 R 50 50 1 1 B
X IO33 9 -750 -100 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

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update=Tue 10 Aug 2021 02:10:54 PM PDT
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

View File

@@ -0,0 +1,71 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Sensor_Magnetic:TLV493D U?
U 1 1 616E0E0C
P 5900 2450
F 0 "U?" H 6180 2546 50 0000 L CNN
F 1 "TLV493D" H 6180 2455 50 0000 L CNN
F 2 "Package_TO_SOT_SMD:SOT-23-6" H 5850 1950 50 0001 C CNN
F 3 "http://www.infineon.com/dgdl/Infineon-TLV493D-A1B6-DS-v01_00-EN.pdf?fileId=5546d462525dbac40152a6b85c760e80" H 5750 2950 50 0001 C CNN
1 5900 2450
1 0 0 -1
$EndComp
$Comp
L lilygo_micro32:T-Micro32_Plus U?
U 1 1 616E21EC
P 2350 2350
F 0 "U?" H 2350 3315 50 0000 C CNN
F 1 "T-Micro32_Plus" H 2350 3224 50 0000 C CNN
F 2 "" H 2350 2350 50 0001 C CNN
F 3 "" H 2350 2350 50 0001 C CNN
1 2350 2350
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C?
U 1 1 616E37C4
P 6300 2100
F 0 "C?" H 6392 2146 50 0000 L CNN
F 1 "C_Small" H 6392 2055 50 0000 L CNN
F 2 "" H 6300 2100 50 0001 C CNN
F 3 "~" H 6300 2100 50 0001 C CNN
1 6300 2100
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR?
U 1 1 616E3FA7
P 1000 1050
F 0 "#PWR?" H 1000 900 50 0001 C CNN
F 1 "+3.3V" H 1015 1223 50 0000 C CNN
F 2 "" H 1000 1050 50 0001 C CNN
F 3 "" H 1000 1050 50 0001 C CNN
1 1000 1050
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR?
U 1 1 616E42FB
P 5550 1650
F 0 "#PWR?" H 5550 1500 50 0001 C CNN
F 1 "+3.3V" H 5565 1823 50 0000 C CNN
F 2 "" H 5550 1650 50 0001 C CNN
F 3 "" H 5550 1650 50 0001 C CNN
1 5550 1650
1 0 0 -1
$EndComp
$EndSCHEMATC

View File

@@ -0,0 +1,3 @@
(sym_lib_table
(lib (name lilygo_micro32)(type Legacy)(uri ${KIPRJMOD}/lib/lilygo_micro32.lib)(options "")(descr ""))
)