updated to v 1.2 usb

This commit is contained in:
2021-05-01 09:46:08 +02:00
parent a7684e4b5c
commit f753a36b7e
49 changed files with 111174 additions and 24138 deletions

View File

@@ -1,4 +1,4 @@
update=2021 March 01, Monday 21:41:52
update=2021 April 30, Friday 14:03:15
version=1
last_client=kicad
[general]
@@ -12,6 +12,16 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@@ -29,8 +39,14 @@ MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.254
ViaDiameter1=0.8128
ViaDrill1=0.4064
TrackWidth2=0.254
TrackWidth3=0.4064
ViaDiameter1=0.6
ViaDrill1=0.3
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
dPairWidth1=0.2032
dPairGap1=0.2032
dPairViaGap1=0.25
@@ -229,8 +245,8 @@ Enabled=0
Name=Default
Clearance=0.2032
TrackWidth=0.254
ViaDiameter=0.8128
ViaDrill=0.4064
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3048
uViaDrill=0.1016
dPairWidth=0.2032
@@ -239,21 +255,11 @@ dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=POWER
Clearance=0.2032
TrackWidth=0.4064
ViaDiameter=0.8128
ViaDrill=0.4064
TrackWidth=0.254
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3048
uViaDrill=0.1016
dPairWidth=0.2032
dPairGap=0.2032
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1