(module Converter_DCDC_Artesyn_ATA_SMD (layer F.Cu) (tedit 5BF2C1CB)
  (descr "DCDC-Converter, Artesyn, ATA Series, 3W Single and Dual Output, 1500VDC Isolation, 24.0x13.7x8.0mm https://www.artesyn.com/power/assets/ata_series_ds_01apr2015_79c25814fd.pdf https://www.artesyn.com/power/assets/trn_dc-dc_ata_3w_series_releas1430412818_techref.pdf")
  (tags "DCDC SMD")
  (attr smd)
  (fp_text reference REF** (at 0 -13.35) (layer F.SilkS)
    (effects (font (size 1 1) (thickness 0.15)))
  )
  (fp_text value Converter_DCDC_Artesyn_ATA_SMD (at 0 13.5) (layer F.Fab)
    (effects (font (size 1 1) (thickness 0.15)))
  )
  (fp_line (start -6.85 -11) (end -6.85 12) (layer F.Fab) (width 0.1))
  (fp_line (start -6.85 12) (end 6.85 12) (layer F.Fab) (width 0.1))
  (fp_line (start 6.85 12) (end 6.85 -12) (layer F.Fab) (width 0.1))
  (fp_line (start 6.85 -12) (end -5.85 -12) (layer F.Fab) (width 0.1))
  (fp_line (start 7.1 -12.25) (end -7.1 -12.25) (layer F.CrtYd) (width 0.05))
  (fp_line (start -9.9 -9.84) (end -9.9 9.84) (layer F.CrtYd) (width 0.05))
  (fp_line (start -7.1 12.25) (end 7.1 12.25) (layer F.CrtYd) (width 0.05))
  (fp_line (start 9.9 9.84) (end 9.9 -9.84) (layer F.CrtYd) (width 0.05))
  (fp_line (start 6.96 -12.11) (end -6.96 -12.11) (layer F.SilkS) (width 0.12))
  (fp_line (start -6.96 -12.11) (end -6.96 -9.84) (layer F.SilkS) (width 0.12))
  (fp_line (start -6.96 -9.84) (end -9.55 -9.84) (layer F.SilkS) (width 0.12))
  (fp_line (start 6.96 -12.11) (end 6.96 -9.84) (layer F.SilkS) (width 0.12))
  (fp_line (start 6.96 12.11) (end -6.96 12.11) (layer F.SilkS) (width 0.12))
  (fp_line (start -6.96 9.84) (end -6.96 12.11) (layer F.SilkS) (width 0.12))
  (fp_line (start 6.96 9.84) (end 6.96 12.11) (layer F.SilkS) (width 0.12))
  (fp_line (start -9.9 -9.84) (end -7.1 -9.84) (layer F.CrtYd) (width 0.05))
  (fp_line (start -7.1 -9.84) (end -7.1 -12.25) (layer F.CrtYd) (width 0.05))
  (fp_line (start 7.1 -12.25) (end 7.1 -9.84) (layer F.CrtYd) (width 0.05))
  (fp_line (start 7.1 -9.84) (end 9.9 -9.84) (layer F.CrtYd) (width 0.05))
  (fp_line (start 9.9 9.84) (end 7.1 9.84) (layer F.CrtYd) (width 0.05))
  (fp_line (start 7.1 9.84) (end 7.1 12.25) (layer F.CrtYd) (width 0.05))
  (fp_line (start -9.9 9.84) (end -7.1 9.84) (layer F.CrtYd) (width 0.05))
  (fp_line (start -7.1 9.84) (end -7.1 12.25) (layer F.CrtYd) (width 0.05))
  (fp_line (start -6.85 -11) (end -5.85 -12) (layer F.Fab) (width 0.1))
  (fp_line (start -6.96 -5.4) (end -6.96 5.39) (layer F.SilkS) (width 0.12))
  (fp_line (start 6.96 -7.93) (end 6.96 5.4) (layer F.SilkS) (width 0.12))
  (fp_text user %R (at 0 0) (layer F.Fab)
    (effects (font (size 1 1) (thickness 0.15)))
  )
  (pad 1 smd rect (at -8.25 -8.89) (size 2.8 1.4) (layers F.Cu F.Paste F.Mask))
  (pad 2 smd rect (at -8.25 -6.35) (size 2.8 1.4) (layers F.Cu F.Paste F.Mask))
  (pad 7 smd rect (at -8.25 6.35) (size 2.8 1.4) (layers F.Cu F.Paste F.Mask))
  (pad 8 smd rect (at -8.25 8.89) (size 2.8 1.4) (layers F.Cu F.Paste F.Mask))
  (pad 9 smd rect (at 8.25 8.89) (size 2.8 1.4) (layers F.Cu F.Paste F.Mask))
  (pad 10 smd rect (at 8.25 6.35) (size 2.8 1.4) (layers F.Cu F.Paste F.Mask))
  (pad 16 smd rect (at 8.25 -8.89) (size 2.8 1.4) (layers F.Cu F.Paste F.Mask))
  (model ${KISYS3DMOD}/Converter_DCDC.3dshapes/Converter_DCDC_Artesyn_ATA_SMD.wrl
    (at (xyz 0 0 0))
    (scale (xyz 1 1 1))
    (rotate (xyz 0 0 0))
  )
)