diff --git a/MFRC522.cpp b/MFRC522.cpp index aea006f..01adb66 100644 --- a/MFRC522.cpp +++ b/MFRC522.cpp @@ -14,7 +14,6 @@ * Constructor. */ MFRC522::MFRC522() { - } // End constructor /** @@ -45,11 +44,11 @@ void MFRC522::setSPIConfig() { * Writes a byte to the specified register in the MFRC522 chip. * The interface is described in the datasheet section 8.1.2. */ -void MFRC522::PCD_WriteRegister(byte reg, ///< The register to write to. One of the PCD_Register enums. - byte value ///< The value to write. - ) { +void MFRC522::PCD_WriteRegister( byte reg, ///< The register to write to. One of the PCD_Register enums. + byte value ///< The value to write. + ) { digitalWrite(_chipSelectPin, LOW); // Select slave - SPI.transfer(reg & 0x7E); // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3. + SPI.transfer(reg & 0x7E); // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3. SPI.transfer(value); digitalWrite(_chipSelectPin, HIGH); // Release slave again } // End PCD_WriteRegister() @@ -58,10 +57,10 @@ void MFRC522::PCD_WriteRegister(byte reg, ///< The register to write to. One of * Writes a number of bytes to the specified register in the MFRC522 chip. * The interface is described in the datasheet section 8.1.2. */ -void MFRC522::PCD_WriteRegister(byte reg, ///< The register to write to. One of the PCD_Register enums. - byte count, ///< The number of bytes to write to the register - byte *values ///< The values to write. Byte array. - ) { +void MFRC522::PCD_WriteRegister( byte reg, ///< The register to write to. One of the PCD_Register enums. + byte count, ///< The number of bytes to write to the register + byte *values ///< The values to write. Byte array. + ) { digitalWrite(_chipSelectPin, LOW); // Select slave SPI.transfer(reg & 0x7E); // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3. for (byte index = 0; index < count; index++) { @@ -225,43 +224,15 @@ void MFRC522::PCD_Init() { /** * Initializes the MFRC522 chip. */ -void MFRC522::PCD_Init(byte chipSelectPin, byte resetPowerDownPin) { +void MFRC522::PCD_Init( byte chipSelectPin, ///< Arduino pin connected to MFRC522's SPI slave select input (Pin 24, NSS, active low) + byte resetPowerDownPin ///< Arduino pin connected to MFRC522's reset and power down input (Pin 6, NRSTPD, active low) + ) { _chipSelectPin = chipSelectPin; - _resetPowerDownPin = resetPowerDownPin; - + _resetPowerDownPin = resetPowerDownPin; // Set the chipSelectPin as digital output, do not select the slave yet - pinMode(_chipSelectPin, OUTPUT); - digitalWrite(_chipSelectPin, HIGH); - - // Set the resetPowerDownPin as digital output, do not reset or power down. - pinMode(_resetPowerDownPin, OUTPUT); - - // Set SPI bus to work with MFRC522 chip. - setSPIConfig(); - - if (digitalRead(_resetPowerDownPin) == LOW) { //The MFRC522 chip is in power down mode. - digitalWrite(_resetPowerDownPin, HIGH); // Exit power down mode. This triggers a hard reset. - // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74�s. Let us be generous: 50ms. - delay(50); - } - else { // Perform a soft reset - PCD_Reset(); - } - - // When communicating with a PICC we need a timeout if something goes wrong. - // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]. - // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg. - PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds - PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25�s. - PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout. - PCD_WriteRegister(TReloadRegL, 0xE8); - - PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting - PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4) - PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset) + PCD_Init(); } // End PCD_Init() - /** * Performs a soft reset on the MFRC522 chip and waits for it to be ready again. */ @@ -406,14 +377,14 @@ bool MFRC522::PCD_PerformSelfTest() { * * @return STATUS_OK on success, STATUS_??? otherwise. */ -byte MFRC522::PCD_TransceiveData(byte *sendData, ///< Pointer to the data to transfer to the FIFO. - byte sendLen, ///< Number of bytes to transfer to the FIFO. - byte *backData, ///< NULL or pointer to buffer if data should be read back after executing the command. - byte *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned. - byte *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL. - byte rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0. - bool checkCRC ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated. - ) { +byte MFRC522::PCD_TransceiveData( byte *sendData, ///< Pointer to the data to transfer to the FIFO. + byte sendLen, ///< Number of bytes to transfer to the FIFO. + byte *backData, ///< NULL or pointer to buffer if data should be read back after executing the command. + byte *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned. + byte *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL. + byte rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0. + bool checkCRC ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated. + ) { byte waitIRq = 0x30; // RxIRq and IdleIRq return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC); } // End PCD_TransceiveData() @@ -425,15 +396,15 @@ byte MFRC522::PCD_TransceiveData(byte *sendData, ///< Pointer to the data to tr * @return STATUS_OK on success, STATUS_??? otherwise. */ byte MFRC522::PCD_CommunicateWithPICC( byte command, ///< The command to execute. One of the PCD_Command enums. - byte waitIRq, ///< The bits in the ComIrqReg register that signals successful completion of the command. - byte *sendData, ///< Pointer to the data to transfer to the FIFO. - byte sendLen, ///< Number of bytes to transfer to the FIFO. - byte *backData, ///< NULL or pointer to buffer if data should be read back after executing the command. - byte *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned. - byte *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits. - byte rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0. - bool checkCRC ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated. - ) { + byte waitIRq, ///< The bits in the ComIrqReg register that signals successful completion of the command. + byte *sendData, ///< Pointer to the data to transfer to the FIFO. + byte sendLen, ///< Number of bytes to transfer to the FIFO. + byte *backData, ///< NULL or pointer to buffer if data should be read back after executing the command. + byte *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned. + byte *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits. + byte rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0. + bool checkCRC ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated. + ) { byte n, _validBits; unsigned int i; @@ -524,8 +495,8 @@ byte MFRC522::PCD_CommunicateWithPICC( byte command, ///< The command to execut * @return STATUS_OK on success, STATUS_??? otherwise. */ byte MFRC522::PICC_RequestA(byte *bufferATQA, ///< The buffer to store the ATQA (Answer to request) in - byte *bufferSize ///< Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK. - ) { + byte *bufferSize ///< Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK. + ) { return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize); } // End PICC_RequestA() @@ -1221,7 +1192,10 @@ byte MFRC522::PICC_GetType(byte sak ///< The SAK byte returned from PICC_Select if (sak & 0x04) { // UID not complete return PICC_TYPE_NOT_COMPLETE; } - + //http://www.nxp.com/documents/application_note/AN10833.pdf + //3.2 Coding of Select Acknowledge (SAK) + //ignore 8-bit + sak&=0x7F; switch (sak) { case 0x09: return PICC_TYPE_MIFARE_MINI; break; case 0x08: return PICC_TYPE_MIFARE_1K; break; diff --git a/MFRC522.h b/MFRC522.h index a427381..00a0dd6 100644 --- a/MFRC522.h +++ b/MFRC522.h @@ -138,105 +138,105 @@ public: enum PCD_Register { // Page 0: Command and status // 0x00 // reserved for future use - CommandReg = 0x01 << 1, // starts and stops command execution - ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits - DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits - ComIrqReg = 0x04 << 1, // interrupt request bits - DivIrqReg = 0x05 << 1, // interrupt request bits - ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed - Status1Reg = 0x07 << 1, // communication status bits - Status2Reg = 0x08 << 1, // receiver and transmitter status bits - FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer - FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer - WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning - ControlReg = 0x0C << 1, // miscellaneous control registers - BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames - CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface - // 0x0F // reserved for future use + CommandReg = 0x01 << 1, // starts and stops command execution + ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits + DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits + ComIrqReg = 0x04 << 1, // interrupt request bits + DivIrqReg = 0x05 << 1, // interrupt request bits + ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed + Status1Reg = 0x07 << 1, // communication status bits + Status2Reg = 0x08 << 1, // receiver and transmitter status bits + FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer + FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer + WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning + ControlReg = 0x0C << 1, // miscellaneous control registers + BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames + CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface + // 0x0F // reserved for future use // Page 1: Command - // 0x10 // reserved for future use - ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving - TxModeReg = 0x12 << 1, // defines transmission data rate and framing - RxModeReg = 0x13 << 1, // defines reception data rate and framing - TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2 - TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation - TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver - RxSelReg = 0x17 << 1, // selects internal receiver settings - RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder - DemodReg = 0x19 << 1, // defines demodulator settings - // 0x1A // reserved for future use - // 0x1B // reserved for future use - MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters - MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters - // 0x1E // reserved for future use - SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface + // 0x10 // reserved for future use + ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving + TxModeReg = 0x12 << 1, // defines transmission data rate and framing + RxModeReg = 0x13 << 1, // defines reception data rate and framing + TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2 + TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation + TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver + RxSelReg = 0x17 << 1, // selects internal receiver settings + RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder + DemodReg = 0x19 << 1, // defines demodulator settings + // 0x1A // reserved for future use + // 0x1B // reserved for future use + MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters + MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters + // 0x1E // reserved for future use + SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface // Page 2: Configuration // 0x20 // reserved for future use - CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation - CRCResultRegL = 0x22 << 1, - // 0x23 // reserved for future use - ModWidthReg = 0x24 << 1, // controls the ModWidth setting? - // 0x25 // reserved for future use - RFCfgReg = 0x26 << 1, // configures the receiver gain - GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation - CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation - ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation - TModeReg = 0x2A << 1, // defines settings for the internal timer - TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg. - TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value - TReloadRegL = 0x2D << 1, - TCounterValueRegH = 0x2E << 1, // shows the 16-bit timer value - TCounterValueRegL = 0x2F << 1, + CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation + CRCResultRegL = 0x22 << 1, + // 0x23 // reserved for future use + ModWidthReg = 0x24 << 1, // controls the ModWidth setting? + // 0x25 // reserved for future use + RFCfgReg = 0x26 << 1, // configures the receiver gain + GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation + CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation + ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation + TModeReg = 0x2A << 1, // defines settings for the internal timer + TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg. + TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value + TReloadRegL = 0x2D << 1, + TCounterValueRegH = 0x2E << 1, // shows the 16-bit timer value + TCounterValueRegL = 0x2F << 1, // Page 3: Test Registers - // 0x30 // reserved for future use - TestSel1Reg = 0x31 << 1, // general test signal configuration - TestSel2Reg = 0x32 << 1, // general test signal configuration - TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7 - TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus - TestBusReg = 0x35 << 1, // shows the status of the internal test bus - AutoTestReg = 0x36 << 1, // controls the digital self test - VersionReg = 0x37 << 1, // shows the software version - AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2 - TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1 - TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2 - TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels - // 0x3C // reserved for production tests - // 0x3D // reserved for production tests - // 0x3E // reserved for production tests - // 0x3F // reserved for production tests + // 0x30 // reserved for future use + TestSel1Reg = 0x31 << 1, // general test signal configuration + TestSel2Reg = 0x32 << 1, // general test signal configuration + TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7 + TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus + TestBusReg = 0x35 << 1, // shows the status of the internal test bus + AutoTestReg = 0x36 << 1, // controls the digital self test + VersionReg = 0x37 << 1, // shows the software version + AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2 + TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1 + TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2 + TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels + // 0x3C // reserved for production tests + // 0x3D // reserved for production tests + // 0x3E // reserved for production tests + // 0x3F // reserved for production tests }; // MFRC522 commands. Described in chapter 10 of the datasheet. enum PCD_Command { - PCD_Idle = 0x00, // no action, cancels current command execution - PCD_Mem = 0x01, // stores 25 bytes into the internal buffer + PCD_Idle = 0x00, // no action, cancels current command execution + PCD_Mem = 0x01, // stores 25 bytes into the internal buffer PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number - PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test - PCD_Transmit = 0x04, // transmits data from the FIFO buffer - PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit - PCD_Receive = 0x08, // activates the receiver circuits - PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission - PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader - PCD_SoftReset = 0x0F // resets the MFRC522 + PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test + PCD_Transmit = 0x04, // transmits data from the FIFO buffer + PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit + PCD_Receive = 0x08, // activates the receiver circuits + PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission + PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader + PCD_SoftReset = 0x0F // resets the MFRC522 }; // MFRC522 RxGain[2:0] masks, defines the receiver's signal voltage gain factor (on the PCD). // Described in 9.3.3.6 / table 98 of the datasheet at http://www.nxp.com/documents/data_sheet/MFRC522.pdf enum PCD_RxGain { - RxGain_18dB = 0x00 << 4, // 000b - 18 dB, minimum - RxGain_23dB = 0x01 << 4, // 001b - 23 dB - RxGain_18dB_2 = 0x02 << 4, // 010b - 18 dB, it seems 010b is a duplicate for 000b - RxGain_23dB_2 = 0x03 << 4, // 011b - 23 dB, it seems 011b is a duplicate for 001b - RxGain_33dB = 0x04 << 4, // 100b - 33 dB, average, and typical default - RxGain_38dB = 0x05 << 4, // 101b - 38 dB - RxGain_43dB = 0x06 << 4, // 110b - 43 dB - RxGain_48dB = 0x07 << 4, // 111b - 48 dB, maximum - RxGain_min = 0x00 << 4, // 000b - 18 dB, minimum, convenience for RxGain_18dB - RxGain_avg = 0x04 << 4, // 100b - 33 dB, average, convenience for RxGain_33dB - RxGain_max = 0x07 << 4 // 111b - 48 dB, maximum, convenience for RxGain_48dB + RxGain_18dB = 0x00 << 4, // 000b - 18 dB, minimum + RxGain_23dB = 0x01 << 4, // 001b - 23 dB + RxGain_18dB_2 = 0x02 << 4, // 010b - 18 dB, it seems 010b is a duplicate for 000b + RxGain_23dB_2 = 0x03 << 4, // 011b - 23 dB, it seems 011b is a duplicate for 001b + RxGain_33dB = 0x04 << 4, // 100b - 33 dB, average, and typical default + RxGain_38dB = 0x05 << 4, // 101b - 38 dB + RxGain_43dB = 0x06 << 4, // 110b - 43 dB + RxGain_48dB = 0x07 << 4, // 111b - 48 dB, maximum + RxGain_min = 0x00 << 4, // 000b - 18 dB, minimum, convenience for RxGain_18dB + RxGain_avg = 0x04 << 4, // 100b - 33 dB, average, convenience for RxGain_33dB + RxGain_max = 0x07 << 4 // 111b - 48 dB, maximum, convenience for RxGain_48dB }; // Commands sent to the PICC. @@ -244,7 +244,7 @@ public: // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4) PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame. PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame. - PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision. + PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision. PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 2 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 3 @@ -252,14 +252,14 @@ public: // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9) // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector. // The read/write commands can also be used for MIFARE Ultralight. - PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A - PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B + PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A + PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight. PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight. - PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register. - PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register. + PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register. + PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register. PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register. - PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block. + PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block. // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6) // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight. PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC. @@ -267,32 +267,32 @@ public: // MIFARE constants that does not fit anywhere else enum MIFARE_Misc { - MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK. - MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes. + MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK. + MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes. }; // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more. enum PICC_Type { PICC_TYPE_UNKNOWN = 0, - PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4 + PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC) - PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes + PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C - PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus + PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure - PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete. + PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete. }; // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more. enum StatusCode { - STATUS_OK = 1, // Success + STATUS_OK = 1, // Success STATUS_ERROR = 2, // Error in communication STATUS_COLLISION = 3, // Collission detected STATUS_TIMEOUT = 4, // Timeout in communication. STATUS_NO_ROOM = 5, // A buffer is not big enough. - STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-) + STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-) STATUS_INVALID = 7, // Invalid argument. STATUS_CRC_WRONG = 8, // The CRC_A does not match STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK. @@ -319,7 +319,7 @@ public: ///////////////////////////////////////////////////////////////////////////////////// // Functions for setting up the Arduino ///////////////////////////////////////////////////////////////////////////////////// - MFRC522(); + MFRC522(); MFRC522(byte chipSelectPin, byte resetPowerDownPin); void setSPIConfig(); @@ -339,7 +339,7 @@ public: // Functions for manipulating the MFRC522 ///////////////////////////////////////////////////////////////////////////////////// void PCD_Init(); - void PCD_Init(byte, byte); + void PCD_Init(byte chipSelectPin, byte resetPowerDownPin); void PCD_Reset(); void PCD_AntennaOn(); void PCD_AntennaOff(); diff --git a/examples/ReadUidMultiReader/ReadUidMultiReader.ino b/examples/ReadUidMultiReader/ReadUidMultiReader.ino index a6ba6c8..1c40be1 100644 --- a/examples/ReadUidMultiReader/ReadUidMultiReader.ino +++ b/examples/ReadUidMultiReader/ReadUidMultiReader.ino @@ -10,6 +10,9 @@ * This sample shows how to read and write data blocks on a MIFARE Classic PICC * (= card/tag). * + * BEWARE: Data will be written to the PICC, in sector #1 (blocks #4 to #7). + * + * * Typical pin layout used: * ----------------------------------------------------------------------------------------- * MFRC522 Arduino Arduino Arduino Arduino Arduino @@ -17,7 +20,7 @@ * Signal Pin Pin Pin Pin Pin Pin * ----------------------------------------------------------------------------------------- * RST/Reset RST 9 5 D9 RESET/ICSP-5 RST - * SPI SS 1 SDA(SS) 5 53 D10 10 10 + * SPI SS 1 SDA(SS) 10 53 D10 10 10 * SPI SS 2 SDA(SS) 2 53 D10 10 10 * SPI MOSI MOSI 11 / ICSP-4 51 D11 ICSP-4 16 * SPI MISO MISO 12 / ICSP-1 50 D12 ICSP-1 14 @@ -28,9 +31,9 @@ #include #include -#define RST_PIN 9 // Configurable, see typical pin layout above +#define RST_PIN 10 // Configurable, see typical pin layout above #define SS_1_PIN 5 // Configurable, see typical pin layout above -#define SS_2_PIN 2 // Configurable, see typical pin layout above +#define SS_2_PIN 3 // Configurable, see typical pin layout above #define NR_OF_READERS 2 @@ -38,12 +41,11 @@ byte ssPins[] = {SS_1_PIN, SS_2_PIN}; MFRC522 mfrc522[NR_OF_READERS]; // Create MFRC522 instance. -MFRC522::MIFARE_Key key; - /** * Initialize. */ void setup() { + Serial.begin(115200); // Initialize serial communications with the PC while (!Serial); // Do nothing if no serial port is opened (added for Arduinos based on ATMEGA32U4) @@ -59,12 +61,14 @@ void setup() { */ void loop() { - for (uint8_t reader = 0; reader < NR_OF_READERS; reader++) { + for (uint8_t reader = 0; reader < NR_OF_READERS; reader++) { // Look for new cards - if (mfrc522[reader].PICC_IsNewCardPresent() && mfrc522[reader].PICC_ReadCardSerial()) { + if (mfrc522[reader].PICC_IsNewCardPresent() && mfrc522[reader].PICC_ReadCardSerial()) { + Serial.print(F("Reader: ")); + Serial.print(reader); // Show some details of the PICC (that is: the tag/card) - Serial.print(F("Card UID:")); + Serial.print(F(" Card UID:")); dump_byte_array(mfrc522[reader].uid.uidByte, mfrc522[reader].uid.size); Serial.println(); Serial.print(F("PICC type: "));